SGS Thomson Microelectronics ETC5067N, ETC5067FN, ETC5067D, ETC5064N, ETC5064FN Datasheet
...
ETC5064/64-X
ETC5067/67-X
November 1994
POWER AMP LIFIER
SERIALINTERFACECODEC/FILTERWITHRECEIVE
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
.COMPLETE CODEC AND FILTERING SYS-
TEMINCLUDING:
-
Transmit high-passandlow-passfiltering.
-
Receivelow-passfilterwithsinx/x correction.
-
ActiveRCnoise filter.
-
µ-law or A-law compatibleCODER and DECODER.
-
Internalprecision voltage reference.
-
SerialI/O interface.
-
Internalauto-zerocircuitry.
-
Receivepush-pullpower amplifiers.
.µ-LAW ETC5064
.A-LAW ETC5067
.MEETSOREXCEEDS ALL D3/D4 ANDCCITT
SPECIFICATIONS.
.± 5 V OPERATION.
.LOWOPERATINGPOWER-TYPICALLY70mW
.POWER-DOWNSTANDBYMODE-TYPICALLY
3mW
.AUTOMATICPOWERDOWN
.TTL ORCMOSCOMPATIBLEDIGITALINTER-
FACES
.MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
.0°CTO70°C OPERATION:ETC5064/67
.–40°CTO85°C OPERATION:ETC5064-X/67-X
DESCRIPTION
TheETC5064(µ-law),ETC5067(A-law) are monolithicPCM CODEC/FILTERS utilizing the A/D and
D/AconversionarchitectureshownintheBlockDiagramsand a serialPCM interface. Thedevices are
fabricatedusing double-polyCMOS process.
Similar to the ETC505Xfamily, these devicesfeaturean additionalReceive Power Amplifier to providepush-pullbalancedoutputdrivecapability.The
receivegain can be adjustedby means of two external resistorsfor an output level of up to ± 6.6 V
acrossa balanced600Ω load.
Also included is an Analog Loopback switch and
TS
X
output.
DIP20
(Plastic) N
PL CC2 0
FN
SO20
D
ORDERING NUMBERS:
ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X
1/18
BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
PIN CONNECTIONS (Top views)
DIP 20 &
SO20
PLCC20
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
2/18
PIN DESCRIPTION
Name
Pin
Type (*)
N Description
VPO
+
O 1 The Non-inverting Output of the Receive Power Amplifier
GNDA GND 2 Analog Ground. All signals are referenced to this pin.
VPO
-
O 3 The Inverting Output of the Receive Power Amplifier
VPI I 4 Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to V
BB
.
VF
R
O O 5 Analog Output of the Receive Filter.
V
CC
S 6 Positive Power Supply Pin. VCC=+5V±5%
FS
R
I 7 Receive Frame Sync Pulse which enableBCLKRto shift PCM data into
D
R
.FSRis an 8KHz pulse train. See figures 1 and 2 for timing details.
D
R
I 8 Receive Data Input. PCM data is shifted into DRfollowing the FSRleading
edge
BCLK
R
/CLKSEL I 9 The bit Clock which shifts data into DRafter the FSRleading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selectseither 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLK
X
is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
MCKL
R
/PDN I 10 Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK
X
, but should be synchronous with MCLKXfor
best performance. When MCLK
R
is connected continuously low, MCLKXis
selected for all internal timing. When MCLK
R
is connected continuously
high, the device is powered down.
MCLK
X
I 11 Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK
R
.
BCLK
X
I 12 The bit clock which shifts out the PCM data on DX. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLK
X
.
D
X
O 13 The TRI-STATEPCM data output which is enabled by FSX.
FS
X
I 14 Transmit frame sync pulse input whichenables BCLKXto shift out the
PCM data on D
X
.FSXis an 8KHz pulse train. See figures 1 and 2 for
timing details.
TS
X
O 15 Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
ANLB I 16 Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO
+
output of the receive power amplifier.
GS
X
O 17 Analog output of the transmit input amplifier. Used to set gain externally.
VF
X
I
-
I 18 Inverting input of the transmit input amplifier.
VF
X
I
+
I 19 Non-inverting input of the transmit input amplifier.
V
BB
S 20 Negative Power Supply Pin. VBB= -5V ±5%
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE is a trademark of National Semiconductor Corp.
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
3/18
FUNCTIO NAL DE SCRIPTION
POWER-UP
Whenpowerisfirstapplied,power-onresetcircuitry
initializes the device and places it into the powerdown mode. All non-essential circuits are deactivatedand the D
X
andVFRO outputsare put in high
impedancestates.Topower-upthedevice,alogical
low level or clock must be applied to the
MCLK
R
/PDN pin andFSXand/orFSRpulsesmust
bepresent.Thus2 power-downcontrolmodesare
available.The first is to pull the MCLK
R
/PDN pin
high;the alternativeis toholdboth FS
X
andFSRinputs continuouslylow. The device will power-down
approximately 2 ms after the last FS
X
pulse. The
TRI-STATEPCMdataoutput, D
X
, willremainin the
highimpedancestate untilthe secondFS
X
pulse.
SYNCHRONOUSOPERATION
For synchronousoperation,the same masterclock
and bit clock shouldbe used for boththe transmit
andreceivedirections.In thismode,a clockmustbe
appliedto MCLK
X
andthe MCLKR/PDNpin can be
used as a power-down control. A low level on
MCLK
R
/PDNpowersup thedevice anda high level
powersdownthedevice.In eithercase,MCLKXwill
beselectedasthemasterclockforboththetransmit
andreceivecircuits.A bitclockmustalsobeapplied
toBCLK
X
andtheBCLR/CLKSELcanbe usedtose-
lect theproper internal dividerfor a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automaticallycompensatesfor the 193 rd clock pulse each frame.
Withafixedlevel onthe BCLK
R
/CKSELpin,BCLK
X
willbe selectedasthe bit clock for boththe transmit
and receivedirections. Table 1 indicates the frequenciesof operation which can be selected, dependingonthestateofBCLK
R
/CLKSEL.Inthissyn-
chronousmode, the bit clock,BCLK
X
, may be from
64kHzto2.048MHz,butmustbesynchronouswith
MCLK
X
.
EachFS
X
pulsebegins the encodingcycle and the
PCM dat a from theprevious encodecycle isshiftout
of the enabled D
X
output on the positive edge of
BCLK
X
. After8 bit clock periods, the TRISTATED
X
outputis returnedto a high impedancestate.With an
FS
R
pulse, PCMdata is latched via the DRinputon
thenegat i veedgeofBCLK
X
(or on BCKLRifrunning).
FS
X
andFSRmustbe sy nc hronouswit hMCLKX/R.
ASYNCHRONOUSOPERATION
Forasynchronousoperation,separatetransmitand
receiveclocksmaybe applied.MCLK
X
andMCLK
R
mustbe2.048MHzforthe ETC5067or1.536MHz,
1.544MHz for the ETC5064, andneed not be synchronous.Forbesttransmissionperformance,however,MCLK
R
shouldbe synchronouswithMCLKX,
which iseasilyachievedby applyingonlystaticlogic
levelstotheMCLK
R
/PDNpin.Thiswillautomatically
connectMCLK
X
toallinternalMCLKRfunctions(see
pin description). For 1.544MHz operation,the deviceautomaticallycompensatesforthe 193rdclock
pulse each frame. FS
X
startseach encodingcycle
andmust besynchronouswith MCLK
X
andBCLKX.
FS
R
starts each decodingcycle and must be syn-
chronouswithBCLK
R
.BCLKRmust bea clock, the
logiclevels shown in Table 1 are not validin asynchronous mode. BCLK
X
and BCLKRmay operate
from 64kHzto 2.048 MHz.
SHORTFRAME SYNCOPERATION
The device can utilize either a short frame sync
pulseoralongframesyncpulse.Uponpowerinitialization,the deviceassumes a shortframemode. In
this mode,both frame sync pulses. FS
X
and FSR,
mustbe one bit clock periodlong, with timing relationshipsspecifiedin figure 2. With FS
X
highduring
a falling edge of BCLK
R
, the next rising edge of
BCLK
X
enablesthe DXTRI-STATE output buffer,
whichwilloutputthesignbit.Thefollowingsevenrising edgesclock out the remaining seven bits, and
the next falling edge disables the D
X
output. With
FS
R
highduringa falling edge ofBCLKR(BCLKXin
synchronousmode), thenextfallingedgeofBCLK
R
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both devicesmay utilizethe shortframe sync pulsein synchronousor asynchronousoperatingmode.
LONGFRAMESYNC OPERATION
To use the long frame mode, both the frame sync
pulses,FS
X
andFSR,mustbethreeormorebitclock
periods long, with timing relationships specified in
figure3. Basedonthe transmitframesyncFS
X
,the
devicewill sensewhether short or longframe sync
Table1: Selectionof MasterClock Frequencies.
BCLKR/CLKSEL
Master Clock
Frequency Selected
ETC5067
ETC5067-X
ETC5064
ETC5064-X
Clocked 2.048MHz 1.536MHz or
1.544MHz
0 1.536MHz or
1.544MHz
2.048MHz
1 (or open circuit) 2.048MHz 1.536MHz or
1.544MHz
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
4/18
pulses are being used. For 64 kHz operation, the
framesync pulsesmust be kept low fora minimum
of 160 ns (see Fig 1). The D
X
TRI-STATE output
bufferis enabledwiththe risingedge of FS
X
or the
rising edgeof BCLK
X
, whichever comes later, and
the first bitclocked out is the sign bit. The following
sevenBCLK
X
risingedgesclockout the remaining
sevenbits. The D
X
outputis disabled by thefalling
BCLK
X
edge following the eighth risingedge,or by
FS
X
goinglow,whichevercomeslater.Arisingedge
onthereceiveframesyncpulse,FS
R
, will cause the
PCM data at D
R
to be latched in on the next eight
falling edges of BCLK
R
(BCLKxin synchronous
mode).Bothdevicesmay utilizethelongframesync
pulsein synchronousor asynchronousmode.
TRANSMITSECTION
Thetransmitsectioninputisanoperationalamplifier
withprovisionforgainadjustmentusingtwoexternal
resistors,seefigure4.Thelownoiseandwidebandwidth allow gains in excess of 20 dB across the
audiopassband to be realized.The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpassfilterdirectlydrives the encodersampleand-holdcircuit. TheA/D is of compandingtypeaccordingto A-law(ETC5067and ETC5067-X)or µlaw (ETC5064 and ETC5064-X) coding conventions. A precision voltage reference is trimmed in
manufacturingto providean inputover load (t
MAX
)
of nominally2.5V peak (see table of Transmission
Characteristics).The FS
X
framesyncpulsecontrols
thesamplingofthefileroutput,andthenthesuccessive-approximationencodingcyclebegins.The8-bit
code is then loaded into a buffer and shifted out
throughD
X
atthenextFSXpulse.thetotal encoding
delaywillbe approximately165µs (dueto thetransmitfilter)plus125µs(due toencodingdelay),which
totals290µs.Any offsetvoltagedue to thefiltersor
comparator iscancelledby signbit integration.
RECEIVESECTION
The receive section consistof an expandingDAC
which drives a fifth order switched-capacitor low
passfilter clocked at256kHz. Thedecoderis A-law
(ETC5067 and ETC5067-X) or µ–law (ETC5064
and ETC5064-X)and the 5 th orderlow passfilter
corrects for the sin x/xattenuationdue tothe 8kHz
sampleand hold. The filter is then followedby a 2
nd order RC active post-filter and power amplifier
capableofdriving a600Ω loadtoa levelof 7.2dBm.
The receive section is unity-gain. Upon the occurenceof FS
R
, the data at theDRinputis clocked
in on the falling edge of the next eight BCLK
R
(BCKLX)periods.Attheendofthedecodertimeslot,
the decoding cycle begins,and 10µs later the decoderDACoutputis updated.Thetotaldecoder delay is about10µs (decoderup-date)plus 110µs (fil-
ter delay) plus 62.5µs (1/2 frame),which givesapproximately180µs.
RECEIVEPOWER AMPLIFIERS
Two invertingmode power amplifiersareprovided
for directly driving a matched line interface transformer.The gain of thefirst power amplifier can be
adjustedtoboostthe± 2.5Vpeakoutputsignalfrom
thereceivefilterup± 3.3Vpeakintoanunbalanced
300Ωload,or±4.0Vintoan unbalanced15kΩ load.
Thesecondpower amplifier isinternally connected
in unity-gain inverting mode to give 6dB of signal
gainforbalancedloads.Maximumpowertransferto
a 600Ω subscriber line termination is obtained by
differientiallydrivinga balancedtransformerwitha
√2 : 1 turns ratio,as shown in figure4.A totalpeak
powerof15.6dBmcan bedeliveredto theloadplus
termination.Both power amplifier can be powered
downindependentlyfromthePDNinputbyconnecting the VPI input to V
BB
saving approximately 12
mW of power.
ABSOLUTEMAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
VCCto GNDA 7 V
V
BB
VBBto GNDA -7 V
V
IN,VOUT
Voltage at any Analog Input or Output VCC+0.3to VBB-0.3 V
Voltage at any Digital Input or Output V
CC
+0.3to GNDA -0.3 V
T
oper
Operating Temperature Range: ETC5064/67
ETC5064-X/67-X
-25 to +125
-40 to +125
°C
°C
T
stg
Storage Temperature Range -65 to +150 °C
Lead Temperature (soldering, 10 seconds) 300 °C
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
5/18
ELECTRICALOPERATING CHARACTERISTICS
V
CC
=5.0V±5%,VBB=-5V±5%,GNDA=0V,TA=0°Cto70°C (ETC5064-X/67-X:TA=–40°Cto85°),unless
otherwisenoted;typicalcharacteristicsspecifiedat V
CC
=5.0V, VBB=-5.0V,TA=25°C; allsignals arerefer-
encedto GNDA.
DIGITAL INTERFACE (All devices)
Symbol Parameter Min. Typ. Max. Unit
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.2 V
V
OL
Output Low Voltage
I
L
= 3.2 mA D
X
IL= 3.2 mA, Open Drain TS
X
0.4
0.4
V
V
V
OH
Output High Voltage
IH = 3.2 mA D
X
2.4 V
I
IL
Input Low Current (GNDA ≤ VIN≤ VIL)all digital inputs
Except BCLK
R
–10 10 µA
I
IH
Input High Current (VIH≤ VIN≤ VCC) Except ANLB – 10 10 µA
I
OZ
Output Currentin High Impedance State (TRI-STATE)
(GNDA ≤ V
O
≤ VCC)D
X
–10 10 µA
ANALOG INTERFACE WITH TRANSMITINPUT AMPLIFIER (all devices)
Symbol Parameter Min. Typ. Max. Unit
I
I
XA Input Leakage Current VFxI+or VFxI
–
(– 2.5 V ≤ V ≤ + 2.5 V)
– 200 200 nA
R
I
XA Input Resistance VFXI+or VFXI
–
(– 2.5 V ≤ V ≤ + 2.5 V)
10 MΩ
R
O
XA Output Resistance (closed loop, unity gain) 1 3 Ω
R
L
XA Load Resistance GS
X
10 kΩ
C
L
XA Load Capacitance GS
X
50 pF
V
O
XA Output Dynamic Range (RL≥ 10 kΩ)GS
X
– 2.8 +2.8 V
A
V
XA Voltage Gain (VFXI+to GSX) 5000 V/V
F
U
XA Unity Gain Bandwidth 1 2 MHz
V
OS
XA Offset Voltage – 20 20 mV
V
CM
XA Common-mode Voltage – 2.5 2.5 V
CMRRXA Common-mode Rejection Ratio 60 dB
PSRRXA Power Supply Rejection Ratio 60 dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol Parameter Min. Typ. Max. Unit
R
O
RF Output Resistance VFRO13Ω
R
L
RF Load Resistance (VFRO=±2.5 V) 10 kΩ
C
L
RF Load Capacitance 25 pF
VOS
R
O Output DC Offset Voltage – 200 200 mV
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
6/18
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