SGS Thomson Microelectronics ESDA6V1W5 Datasheet
®
ESDA6V1W5
Application Specific Discretes
A.S.D.
MAIN APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Computers
Printers
Communication systems
GSM handsets and ac cessories
Other telephone sets
Set top boxes
FEATURES
4 unidirectional TRANSIL functions.
Breakdown voltage : VBR = 6.1 V min.
Low leakage current : < 1µA.
Very low PC B spac e consuming : 4.2 mm2 typically.
DESCRIPTION
The ESDA6V1W5 is a 4-bit wide monolithic
suppressor which is designed to protect component
connected to data and transmission lines against
ESD.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
QUAL TRANSIL ARRAY
FOR ESD PROTECTION
SOT323-5L
FUNCTIONAL DIAGRAM
1
2
3
5
4
BENEFITS
High ESD protection level : up to 25 kV.
High integration.
Suitable for high density boards.
COMPLIES WITH THE FOLLOWING STANDARDS :
IEC 1000-4-2 level 4
MIL STD 883C-Method 3015-6 : class 3.
(human body model)
September 1999 - Ed: 1A
ESD RESPONSE TO IEC1000-4-2
(air discharge 16 kV , p ositive surge)
1/7
ESDA6V1W5
ABSOLUTE MAXIMUM RATINGS
(T
amb
= 25° C)
Symbol Parameter Test conditions Value Unit
V
PP
P
PP
T
op
T
j
T
stg
T
L
ELECTRICAL CHARACTERISTICS
ESD discharge MIL STD 883C - Method 3015-6
IEC1000-4-2, air discharge
IEC1000-4-2, contact discharge
25
16
9
Peak pulse power (8/20 µs) 150 W
Operating temperature range - 40 to + 85 °C
Junction temperature 150 °C
Storage temperature range - 55 to + 150 °C
Lead solder temperature (10 secondes duration) 260 °C
(T
= 25°C)
amb
Symbol Parameter
V
RM
V
BR
V
CL
Stand-off voltage
Breakdown voltage
Clamping voltage
I
kV
I
RM
I
PP
α
T Voltage temperature coefficient
Leakage current
Peak pulse current
C Capacitance per line
Rd Dynamic resistance
V
F
Types VBR @ I
ESDA6V1W5
note 1
: Square pulse Ipp = 15A, tp=2.5µs.
note 2
: ∆ VBR = αT* (Tamb -25°C) * VBR (25°C)
Forward voltage drop
min. max. max. typ. max. typ. max.
VVmA
6.1 7.2 1 1 3 350 6 90 1.25 200
R
V
V
CL
I
@ V
RM
AVm
µ
RM
V
BR
slope : 1 / R
Rd
note 1 note 2 0V bias
Ω
RM
I
RM
I
R
d
TC V
α
10-4/°CpF V mA
I
PP
@ I
F
V
F
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CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DY NAM IC RE SIS TANCE
The ESDA family has been des igned t o c lamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage V
CL
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
= VBR + Rd I
V
CL
PP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEAS UREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.
I
Ipp
ESDA6V1W5
.
2µs
tp = 2.5µs
2.5µs duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20µs, the
2.5µs rectangular surge is well adapted. In addition
both rise and fall times are optimized to avoid any
parasitic phenomenon during the measurement of
Rd.
t
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