With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
risesabovethe operating voltage ofthedevice, the TVS arraybecomesa low impedance pathdivertingthe
transient current to ground.
Bidirectional protection for 0V biased signals.
DRIVER
1
2
3
6
5
4
CONNECTOR
The ESDA6V1-4BC6 array is the ideal product for use as board level protection of ESD sensitive
semiconductor components.
The tiny SOT23-6L package allows design flexibility in the design of “crowded” boards where the space
saving is at a premium. This enables to shorten the routing and can contribute to improve ESD
performance.
2. Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
■
The ESDA6V1-4BC6 should be placed as near as possible to the input terminals or connectors.
■
Minimise the path length between the ESD suppressor and the protected device
■
Minimise all conductive loops, including power and ground loops
■
The ESD transient return path to ground should be kept as short as possible.
■
Use ground planes whenever possible.
2/5
ESDA6V1-4BC6
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25°C)
SymbolTest conditionsValueUnit
V
PP
P
PP
T
j
T
stg
T
L
T
op
Note 1: Variation of parameters is given by curves.
ELECTRICAL CHARACTERISTICS (T
ESD discharge - MIL STD 883C - Method 3015-6
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
Peak pulse power (8/20µs)
Junction temperature
Storage temperature range
Lead solder temperature (10 second duration)
Operating temperature range (note 1)
= 25°C)
amb
25
15
8
80W
150°C
-55 to +150°C
260°C
-40 to +125°C
I
SymbolParameter
V
V
V
I
RM
BR
CL
RM
I
PP
C
Rd
Stand-off voltage
Breakdown voltage
Clamping voltage
Leakage current
Peak pulse current
Capacitance
Dynamic resistance
V
BR
V
Rd
RM
I
I
RM
PP
V
CL
kV
V
V
@IRIRM@V
BR
Type
min.max.max.typ.max.typ.
VVmAµAV Ω 10
ESDA6V1-4BC6
Note 1 : Square pulse, Ipp = 3A, tp=2.5µs.
6.181130.45345
Fig. 1: Relative variation of peak pulse power
versus initial junction temperature.
P [T initial] / P [T initial=25°C]
PP jPP j
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0255075100125150
T (°C)
j
RM
RdαTC
note 10V bias
-4
/°CpF
Fig. 2: Peak pulsepower versus exponential pulse
duration.
P (W)
PP
1000
100
t (µs)
10
110100
p
Tjinitial = 25°C
3/5
ESDA6V1-4BC6
Fig. 3: Clamping voltage versus peak pulse
current (typical values, rectangular waveform).
I (A)
PP
100.0
10.0
1.0
t = 2.5µs
V (V)
0.1
05101520253035404550
CL
p
T
initial = 25°C
j
Fig. 5: Relative variationof leakage current versus
junction temperature (typical values).
I [T ] / I [T =25°C]
Rj Rj
100
10
Fig. 4: Junction capacitance versus line voltage
applied (typical values).
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