SGS Thomson Microelectronics ESDA6V1-4BC6 Datasheet

®
ESDA6V1-4BC6
Application Specific Discretes
A.S.D.™
APPLICATIONS
Where transient overvoltage protection in ESD sensitive equipment is required, such as :
COMPUTERS
PRINTERS
COMMUNICATION SYSTEMS
VIDEO EQUIPMENT
Thisdevice is particularly adaptedto the protection of symmetrical signals.
DESCRIPTION
The ESDA6V1-4BC6 is a monolithic array designed to protect up to 4 lines in a bidirectional way against ESD transients.
The device is ideal for situations where board space is at a premium.
SUPPRESSOR FOR ESD PROTECTION
QUAD BIDIRECTIONAL TRANSIL
SOT23-6L (SC-74)
FUNCTIONAL DIAGRAM
SOT23-6L
FEATURES
4 BIDIRECTIONAL TRANSIL FUNCTIONS
ESD PROTECTION FOR DATA, SIGNAL AND
BUS
V
CC
STAND OFF VOLTAGE RANGE: 5 V
LOW LEAKAGE CURRENT
PEAK PULSE POWER (8/20µs); 80W
CHANNEL SEPARATION: 80dB typ.@20KHz
BENEFITS
High ESD protection level
High integration
Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS:
- IEC61000-4-2: 15 kV (air discharge) 8 kV (contact discharge)
- MIL STD 883E-Method 3015-7: class3
(human body model)
1
2
3
6
5
4
November 2002- Ed: 1A
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ESDA6V1-4BC6
1. ESD protection by ESDA6V1-4BC6
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient
risesabovethe operating voltage ofthedevice, the TVS arraybecomesa low impedance pathdivertingthe transient current to ground.
Bidirectional protection for 0V biased signals.
DRIVER
1
2
3
6
5
4
CONNECTOR
The ESDA6V1-4BC6 array is the ideal product for use as board level protection of ESD sensitive semiconductor components.
The tiny SOT23-6L package allows design flexibility in the design of “crowded” boards where the space saving is at a premium. This enables to shorten the routing and can contribute to improve ESD performance.
2. Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended :
The ESDA6V1-4BC6 should be placed as near as possible to the input terminals or connectors.
Minimise the path length between the ESD suppressor and the protected device
Minimise all conductive loops, including power and ground loops
The ESD transient return path to ground should be kept as short as possible.
Use ground planes whenever possible.
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ESDA6V1-4BC6
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25°C)
Symbol Test conditions Value Unit
V
PP
P
PP
T
j
T
stg
T
L
T
op
Note 1: Variation of parameters is given by curves.
ELECTRICAL CHARACTERISTICS (T
ESD discharge - MIL STD 883C - Method 3015-6
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge Peak pulse power (8/20µs) Junction temperature Storage temperature range Lead solder temperature (10 second duration)
Operating temperature range (note 1)
= 25°C)
amb
25 15
8
80 W
150 °C
-55 to +150 °C 260 °C
-40 to +125 °C
I
Symbol Parameter
V V
V
I
RM BR
CL
RM
I
PP
C
Rd
Stand-off voltage Breakdown voltage
Clamping voltage
Leakage current Peak pulse current Capacitance Dynamic resistance
V
BR
V
Rd
RM
I
I
RM
PP
V
CL
kV
V
V
@IRIRM@V
BR
Type
min. max. max. typ. max. typ.
VVmAµAV 10
ESDA6V1-4BC6
Note 1 : Square pulse, Ipp = 3A, tp=2.5µs.
6.181130.45 3 45
Fig. 1: Relative variation of peak pulse power versus initial junction temperature.
P [T initial] / P [T initial=25°C]
PP j PP j
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 0 25 50 75 100 125 150
T (°C)
j
RM
Rd αTC
note 1 0V bias
-4
/°C pF
Fig. 2: Peak pulsepower versus exponential pulse duration.
P (W)
PP
1000
100
t (µs)
10
1 10 100
p
Tjinitial = 25°C
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ESDA6V1-4BC6
Fig. 3: Clamping voltage versus peak pulse
current (typical values, rectangular waveform).
I (A)
PP
100.0
10.0
1.0
t = 2.5µs
V (V)
0.1 0 5 10 15 20 25 30 35 40 45 50
CL
p
T
initial = 25°C
j
Fig. 5: Relative variationof leakage current versus junction temperature (typical values).
I [T ] / I [T =25°C]
Rj Rj
100
10
Fig. 4: Junction capacitance versus line voltage applied (typical values).
C(pF)
50 45 40 35 30 25 20 15 10
5 0
0123456
V (V)
R
F = 1MHz
V = 30mV
OSC
= 25°C
T
j
Fig. 6: Analog crosstalk test configuration.
50
V
G
Port 1
I/O1
unloaded
GND
T (°C)
j
1
25 50 75 100 125
Symbol Parameter
αch Pintopic channel
separation
Note 2 : According to figure 6 schematic.
Conditions
(see note 2)
F = 20 KHz 80 dB
F = 10 MHz 34
ORDER CODE
ESDA 6V1 4B C6
ESD ARRAY
V min.
BR
50
I/O6
Port 2
Values
Unit
Min. Typ. Max.
PACKAGE: C6: SOT23-6L (SC-74)
Bidirectional
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PACKAGE MECHANICAL DATA
SOT23-6L
ESDA6V1-4BC6
e
D
e
C
FOOTPRINT
A
E
A2
REF. DIMENSIONS
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0 0.10 0 0.004
b
A2 0.90 1.30 0.035 0.0512
b 0.35 0.50 0.0137 0.02
c 0.09 0.20 0.004 0.008 D 2.80 3.00 0.11 0.118 E 1.50 1.75 0.059 0.0689 e 0.95 0.0374 H 2.60 3.00 0.102 0.118
θ
H
A1
L
L 0.10 0.60 0.004 0.024
θ 10° 10°
MARKING
0.60
0.024
Type Marking
1.20
0.047
ESDA6V1-4BC6 BS77
Packaging: Standard packaging is tape and reel.
3.50
2.30
0.138
0.090
Informationfurnished is believed tobe accurate andreliable.However, STMicroelectronics assumesno responsibility for theconsequences of useofsuch information norforany infringement ofpatents or other rightsof third parties whichmay result from itsuse. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap­proval of STMicroelectronics.
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mm inch
0.95
0.037
1.10
0.043
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