SGS Thomson Microelectronics DSM2180F3 Datasheet
DSM (Digital Signal Processor System Memory)
For Analog Devices ADSP-218X Family (5V Supply)
FEATURES SUMMARY
■ Glueless Connection to DSP
– Easily add memory, logic, and I/O to DSP
■ 128K Byte Flash Memory
– For Bootloading and/or Data Overlay Memory
– Programmable Decoding and Paging Logic
allows accessing Flash memory as Byte DMA
(BDMA) and as External Da ta Overlay memory
– Rapid ly acc ess F lash memory with BDMA f o r
booting and loading internal DSP Overlay
memory. Alternati vely access t he same Flash
memory a s Exte rn al Data Over la y memo ry to
efficiently write Flash memory with code updates and data, a byte at a time with no DMA
setup overhead
– Individual 16K Byte Flash memory sectors
match size of DSP External Data Overlay
window for efficient data management. Integrated page logic provides easy DSP access
to all 128K Bytes.
– DSM connects to lower byte of 16-bit DSP
data bus. Byte-wide acc esses to 8-bi t B DMA
space. Half-word accesses to 16-bit Data
Memory Overlay and 16-bit I/O Mem space.
■ 5V Devices (±10%)
■ Up to 16 Multifunction I/O Pins
– Increase total DSP system I/O capability
– I/O controlled by DSP software or PLD logic
– 8mA I/O pin drive at 5 Vcc
■ Genera l pu rpo s e P LD
– Over 3,000 Gates of PLD with 16 macro cells
– Use for peripheral glue logic to keypads, con-
trol panel, displays, LCD, UART devices, etc.
– Eliminate PLDs and external logic devices
– Create state machines, chip selects, simp le
shifters and counters, clock dividers, delays
– Simple PSDsoft Express
TM
software ...Free
DSM2180F3
Figure 1. Packages
PQFP52 (T)
PLCC52 (K)
■ In-System Programming (ISP) with JTAG
– Program entire chip in 10-20 seconds with no
involvement of the DSP
– Eliminate sockets for pre-programm ed me m-
ory and logic devices
– Efficient manufacturing allows easy product
testing and Just-In-Time inventory
CC
TM
cable with PC
=5V
– Use low-cost FlashLINK
■ Content Security
– Programmable Security Bit blocks access of
device programmers and readers
■ Zero-Power Techno lo gy
–75 µA standby at V
■ Small Packaging
– 52-pin PQFP or 52-pin PLCC
■ Memory Spee d
–90 ns
1/63December 2001
DSM2180F3
TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DSP Address/Data/Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable Logic (PLDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
JTAG ISP Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Security and NVM Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Specifying Mem Map with PSDsoft ExpressTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Runtime control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
Programming Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash Memory Sector Protect.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DSM Security Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/63
DSM2180F3
DSP Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Port B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power On Reset, Warm Reset, Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programming In-Circuit using JTAG ISP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table: Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table: DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table: CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table: CPLD Macrocell Synchronous Clock Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table: CPLD Macrocell Asynchronous Clock Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table: Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table: Reset (Reset) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5
Table: ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular. . . . . . . . . . . . . . . . . . . . . . . . 57
Table: Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table: PQFP52 - 52 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table: Pin Assignments – PQFP52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3/63
DSM2180F3
SUMMARY DESCRIPTION
These are system memory devices for use with
Digital Signal Processors from the popular Analog
Devices ADSP-218X family. DSM means Digital
signal processor System Memory. A DSM device
brings in-system programmable Flash memory,
programmable logic, and additional I/O to DSP
systems. The result is a simple and flexible twochip solution for DSP designs. DSM devices provide the flexibility of Flash memory and smart
JTAG programming technique s for both manu facturing and the field. On-chip integrated memory
decode logic and memory paging logic make it
easy to add large amounts of external Flash memory to the ADSP-218X family for bootloading upon
power-up and/or overlay memory. The DSP accesses this Flash memory using either its Byte
DMA (BDMA) interface or as external data overlay
memory (no DMA setup overhead).
Figure 2. PLCC Connections
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PD2
PD1
PD0
PC7
PC6
PC5
PC4
V
GND
PC3
PC2
PC1
PC0
4
567
8
9
10
11
12
13
14
15
CC
16
17
18
19
20
21222324252627282930313233
PA7
PA6
PA5
PA4
52
2
3
1
PA3
PA2
PA1
GND
JTAG In-System Programming (ISP) reduces development time, simplifies manufacturing flow,
and lowers the cost of field upgrades. The JTAG
ISP interface eliminates the need for sockets and
pre-programmed memory and logic devices. For
manufacturing, end products may be as sembled
with a blank DSM device soldered to the circuit
board and programmed at the end of the manufacturing line in 10 to 20 seconds with no involvement
of the DSP. This allows efficient means to test
RESET
PB7
CNTL2
CNTL0
CNTL1
47
48
49
50
51
AD15
46
AD14
45
AD13
44
AD12
43
AD11
42
AD10
41
AD9
40
AD8
39
V
38
CC
AD7
37
AD6
36
AD5
35
AD4
34
PA0
AD2
AD1
AD3
AD0
AI02857
product and manage inventory by rapidly programming test code, then application code as determined by inventory requirements (Just -In Time
inventory). Additionally, JTAG ISP reduces development time by turning fast iterations of DSP code
in the lab. Code updates in the field require no disassembly of product. The FlashLINK
TM
JTAG programming cable costs $59 USD and plugs into any
PC or note-book parallel port.
Figure 3. PQFP Connections
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
CNTL1
CNTL2
RESET
CNTLO
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 V
CC
30 AD7
29 AD6
28 AD5
27 AD4
PA0
AD0
AD1
AD2
AD3
AI02858
PD2
PD1
PD0
PC7
PC6
PC5
PC4
V
GND
PC3
PC2
PC1
PC0
52515049484746454443424140
1
2
3
4
5
6
7
8
CC
9
10
11
12
13
14151617181920212223242526
PA7
PA6
PA5
PA4
PA3
PA2
PA1
GND
In addition to ISP Flash memory, DSM devices
add programmable logic (PLD) and up to 16 configurable I/O pins to the DSP system. The state of
each I/O pin can be driven by DSP software or
PLD logic. PLD and I/O configuration are programmable by JTAG I SP, just like the Flash m emory.
The PLD consists of more than 3000 gates and
has 16 macro cell registers. Common uses for the
PLD include chip selects for external devices (i.e.
UART), state-machines, simple shifters and
counters, keypad and control panel interfaces,
clock dividers, handshake delay, muxes, etc. This
eliminates the need for small external PLDs and
logic devices. Configuration of PLD, I/O, and Flash
memory mapping are easily entered in a pointand-click environment using the software development tool, PSDsoft Express
TM
. This software is
available at no charge from www.psdst.com.
4/63
Figure 4. System Block Diagram, Two-Chip Solution
DSM2180F3
AI04910
I/O, PLD, CHIP SELECTS
8 I/O
DSM2180F3
DSP SYSTEM MEMORY
MEM PAGE CONTROL
ADDR & DECODE LOGIC
22 ADDRESS
PORTS
128k X 8
FLASH MEMORY
8 DATA
ISP, I/O, PLD, CHIP SEL
ALL
8 I/O
I/O BUS
16 MACROCELL PLD
JTAG
PORTS
I/O CONTROL
ISP TO
AREAS
POWER MANAGEMENT
CONTENT SECURITY
WR, RD, BMS, DMS, IOMS
ANALOG
DEVICES
13 FLAGS / 4 INTR
The two-chip combination of a DSP and a DSM
device is ideal for systems which have limitations
on size, EMI levels, and power consumption. DSM
memory and logic are “zero-power”, meaning they
DSP
SERIAL
ADSP-218X
DEVICE
FAMILY
SERIAL
DEVICE
automatically go to standby between memory accesses or logic input changes , producing low active and standby current consumption, which is
ideal for battery powered products.
5/63
DSM2180F3
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copying. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again. The DSP will always have
access to Flash memory contents through the 8-bit
data port even while the security bit is set.
Table 1. DSM2180F3 DSP Memory System Devices
Part Number
DSM2180F3-90 128K Bytes Eight 16K Byte Sectors 16 macro cells Up to 16 5V ±10% 90 ns
ISP Flash
Memory
Flash Partitioning PLD I/O Ports
V
CC
and I/O
Mem Speed
Table 2. Compatible Analog Devices DSPs
DSP Part Numbers
ADSP- 2181, 2184, 2185, 2186 5.0 5.0V
Operating Voltage, V
CC
I/O Capability
6/63
ARCHITECTURAL OVERVIEW
Major functional blocks are shown in Figure 5.
DSP Address/Data/Control Interface
These DSP signals attach directly to the DSM inputs for a glueless connection. An 8-bit data c onnection is formed and all 22 DSP address lines
can be decoded while the DSP operates in full
memory mode. DSP memory strobes;
and
IOMS are used for BDMA, dat a, & I/O access
respectively (no program memory access,
BMS, DMS,
PMS).
Flash Memory
The 1 Mbit (128K x 8) Flash memory is divided into
eight equally-sized 1 6K byte s ect ors t hat are i ndividually selectable through the Decode PLD. Each
Flash memory sector can be located at any address as defined by the user with PSDsoft Express. The flexibility of the Decode PLD and Page
Register logic allow the DSP to access Flash
memory as Byte DMA (BDMA) or as external data
overlay memory across several memory pages.
BDMA transfers are good for initial bootloading
and for loading internal overlay memory at runtime, but BDMA is not efficient writing to Flash
memory because Flash memory is unlocked, written, and status is check ed one byt e at a time, requiring an initialization of the BDMA channel for
each and every byte transfer. The DSM device al-
DSM2180F3
lows the DSP to al ternat ively access F l ash memory as data overlay m emory (using
BMS). Writing Flash memory this way is faster and
requires simpler code. Note: During a DSP data
access using the
DMS strobe, only the upper b yte
of a 16-bit DSP data word is used.
DSM Flash memory sector size of 16K bytes
matches the DSP external Data M emory Overlay
window size of 16K locations (two 8K windows
when DMOVLAY register is used, see Analog Devices ADSP-218X data sheets). This alignment
provides convenient data management. Also,
each 16K byte sector can be loaded with contents
from different firmware or data files specified in
PSDsoft Express
TM
.
Miscellaneous: The DSP can erase Flash memory
by individual sectors or the entire Flash memory
array may be erased at one time. The Flash memory automatically goes to standby between D SP
read or write accesses to conserve power. Maximum access times include sector decodi ng time.
Maximum erase cycles is 100K and data retention
is 15 years minimum. Flash memory, as well as
the entire DSM device may be program med with
the JTAG ISP interface with no DSP involvement.
DMS instead of
7/63
DSM2180F3
Figure 5. B lo ck D ia gram
SECURITY
DSP
ADDR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PC2
PC7
DSP
CONTROL
CNTL0
CNTL1
CNTL2
PD0
PD1
PD2
RST\
LOCK
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP
PAGE REG
fs5
fs4
DECODE PLD
EXTERNAL
CHIP SELECTS
COMPLEX PLD
PLD INPUT BUS
PIN FEEDBACK
NODE FEEDBACK
(DPLD)
(CPLD)
AND
ARRAY
FS0-7
CSIOP
EXTERNAL CHIP SELECTS, ESC0-2
3 OPTIONAL OUTPUTS TO PORT D
A
B
B
C
16 OUTPUT MICRO<>CELLS
B
C
fs3
fs2
fs1
fs0
8 SEGMENTS, 16 KB
POWER MANAGEMENT
A
A
A
B
B
B
B
B
B
C
C
C
B
B
B
C
C
C
16 INPUT
MICRO<>CELLS
128 KBytes TOTAL
RUNTIME CONTROL
CSIOP REGISTER FILE
C
B
C
FLASH MEMORY
fs7
fs6
A
A
A
A
B
B
B
B
B
B
B
B
C
C
C
B
B
B
C
C
C
ALLO-
CATOR
JTAG-ISP
TO ALL AREAS
OF CHIP
DSM2180F3
DSP SYSTEM
MEMORY
DSP
DATA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O PORT
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O PORT
PC0
PC1
PC3
PC4
PC5
PC6
AI04911
Programm a b le Logic (PLDs)
The DSM family contains two PLDS that m ay optionally run in Turbo or Non-Turbo mode. PLDs operate faster (less propagation delay) while in
Turbo mode but consume more power than NonTurbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode setting is controlled at runtime by DSP software.
Decode PLD (DPLD). This is programmable logic used to select one of the eight individual Flash
memory segments or the group of control registers
within the DSM device. The DPLD can also optionally drive external chip select signals on Port D
pins. DPLD input signals include: DSP address
and control signals, Page Register outputs, DSM
Port Pins, CPLD logic feedback.
Complex PLD (CPLD). This programmable logic
is used to c reate bo th combinatorial and sequential general purpose logic. The C PLD contains 16
Output Macrocells (OMCs) and 16 Input Macrocells (IMCs). PSD macrocell registers a re unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This di rect access is good
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD inputs include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
OMCs: The general structure of the CPLD is similar in nature to a 22V10 PLD device wit h t he familiar sum-of-products (AND-OR) construct. True
and compliment versions of 64 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term O R gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flipflop within in each OMC to realize sequential logic.
OMCs can be used a s a buried nodes with feedback to the AND array or OMC output can be routed to pins on Port B or PortC.
IMCs: Inputs from pins on Port B or Port C are
routed to IMCs for conditioning (clocking or latching) as they enter the chip, which is good for sampling and debouncing inputs. Alternatively, IMCs
can pass Port input signals directly to P LD inputs
8/63
DSM2180F3
without clocking or latching. The DSP may read
the IMCs at any time.
Runtime Control Registers
A block of 256 byt es is decoded inside the DSM
device as DSM control and status registers. 27
registers are used in the block of 256 locations to
control the output state of I/O pins, to read I/O
pins, to control p ower managem ent, to read /write
macrocells, and other functions at runtime. See
Table 4 for description. The base address of these
256 locations is referred to in this data sheet as
csiop
(Chip Select I/O Port). Individual registers
within this block are accessed with an offset from
csiop
the base address. The DSP accesses
ters using I/O memory with the
IOMS strobe.
regis-
csiop
registers are accessed as bytes, so only the lower
half of a DSP I/O word is used during access.
Memory Page Register
This 8-bit register can be l oaded and read b y the
csiop
DSP at runtime as one of the
registers. Its
outputs feed directly into the PLDs. The page register is a powerful feature that allows the DSP to
access all 128K Bytes of DSM Flash memory in
16K byte pages. This s ize matches the 16K location data overlay window the AD SP-218X family.
Page register outputs may also be used as CP LD
inputs for general use.
I/O Po r t s
The DSM has 19 individually configurable I/O pins
distributed over the three ports (Ports B, C, and D).
Each I/O pin can be individually configured for different functions such as standard MCU I/O p orts
or PLD I/O on a pin by pin basis. (MCU I/O means
that for each pin, its output state can be controlled
or its input value can be read by the DSP at runt-
csiop
ime using the
registers like an MCU would
do.)
Port C hosts the JTAG ISP signals. Sinc e JTAG-
ISP does not occur frequently during the life of a
product, those Port C pins are under-utilized. In
applications that need every I/O pin, JTAG signals
can be multiplexed with general I/O signals to use
them for I/O when not performing ISP. See section
titled “Programming In-Circuit using JTAG ISP” on
page 41 for muxing JTAG pins on Port C, and Application Note
AN1153
The static configuration of all Port pins is d efined
with the PSDsoft Express
.
TM
software development tool. The dynami c ac tion of th e P orts p ins is
controlled by DSP runtime software.
JTAG ISP Port
In-System Programming (ISP) can be pe rformed
through the JTAG signals on Port C. This serial interface allows programming of the entire DSM
device or subsections (t hat is, only Flash me mory
but not the PLDs) without the participation of the
DSP. A blank DSM device soldered to a circuit
board can be completely programmed in 10 to 20
seconds. The basic JTAG signals; TMS, TCK,
TDI, and TDO form the IEEE-1149.1 interface.
The DSM device does not implement the IEEE-
1149.1 Boundary Scan funct ions. The DSM uses
the JTAG interface for ISP only. However, the
DSM device can reside i n a st andard J TAG ch ain
with other JT AG devic es and it will r emain in BY PASS mode while other devices perform Boundary Scan.
ISP programming time can be reduced as much as
30% by using two more signals on Port C, TSTAT
and TERR
The FlashLINK
in addition to TMS, TCK, TDI and TDO.
TM
JTAG programming cable is
available from STMicroelectronics for $59USD
and PSDsoft Express software is available at no
charge from www.psdst.com. That is all that is
needed to program a DSM device using the parallel port on any PC or note-book. See section titled
“Programming In-Circuit using JTAG ISP” on page
41.
Power Management
csiop
The DSM has bits in
control registers that
are configured at run -time by the DSP to reduce
power consumption of the CPLD. The Turbo bit in
the PMMR0 register can be set to logic 1 and the
CPLD will go to Non-Turbo mode, meaning it will
latch its outputs and go to sleep until the next transition on its inputs. There is a slight penalty in PLD
performance (longer propagation delay), but significant power savings are realized.
csio p
Additionally, bits in two
registers can be set
by the DSP to selectively block signals from entering the CPLD which reduces power consumption.
See section titled “Power Management” on page
39.
Security and NVM Sector Protection
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copying. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again.
Additionally, the content s of ea ch in dividual F lash
memory sector can be write protected (sector protection) by configuration with PSDsoft Express
TM
This is typically used to protect DSP boot code
from being corrupted by inadvertent writes to
Flash memory from the DSP.
Pin Assign m ent s
Pin assignment are shown for the 52-pin PLCC
package in F igure 2, and the 5 2-pin PQFP package in Figure 3.
.
9/63
DSM2180F3
Table 3. Pin Description
Pin Name Type Description
ADIO0-15 In Sixteen address inputs from the DSP.
CNTL0 In Active low write strobe input (WR
CNTL1 In Active low read strobe input (RD
CNTL2 In Active low Byte Memory Select (BMS
Reset
PA0-7 I/O Eight data bus signals connected to DSP pins D8 - D15.
PB0-7 I/O
PC0-7 I/O
PD0-2 I/O
V
CC
GND Ground pins
Active low reset input from system. Resets DSM I/O Ports, Page Register contents, and other
In
DSM configuration registers. Must be logic Low at Power-up.
Eight configurable Port B signals with the following functions:
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. CPLD Output Macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs (Input Macrocells).
Note: Each of the four Port B signals PB0-PB3 may be configured at run-time as either standard
CMOS or for high slew rate. Each of the four Port B signals PB3-PB7 may be configured at
run-time as either standard CMOS or Open Drain Outputs.
Eight configurable Port C signals with the following functions:
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. CPLD Output Macrocell (McellBC0-7) output.
3. Input to the PLDs (Input Macrocells).
4. Pins PC0, PC1, PC5, and PC6 can optionally form the JTAG IEEE-1149.1 ISP serial
interface as signals TMS, TCK, TDI, and TDO respectively.
5. Pins PC3 and PC4 can optionally form the enhanced JTAG signals TSTAT and TERR
respectively. Reduces ISP programming time by up to 30% when used in addition to the
standard four JTAG signals: TDI, TDO, TMS, TCK.
6. Pin PC3 can optionally be configured as the Ready/Busy output to indicate Flash memory
programming status during parallel programming. May be polled by DSP or used as DSP
interrupt to indicate when Flash memory byte programming or erase operations are
complete.
Note 1: Port C pin PC2 input (or any PLD input pin) can be connected to DSP D18 output which
Note 2: Port C pin PC7 input (or any PLD input pin) can be connected to DSP D19 output which
Note 3: When used as general I/O, each of the eight Port C signals may be configured at run-time
Note 4: The JTAG ISP pins may be multiplexed with other I/O functions.
Three configurable Port D signals with the following functions:
Note 1: It is recommended to connect Port D pin PD0 input to DSP IOMS
Note 2: It is recommended to connect Port D pin PD1 input to DSP DMS
Note 3: It is recommended to connect Port D pin PD2 input to DSP PWDACK output if the DSP
Supply Voltage
functions as DSP address A16 in DSP Full Memory Mode. See Figure 6.
functions as DSP address A17 in DSP Full Memory Mode. See Figure 6.
as either standard CMOS or Open Drain Outputs.
1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. Input to the PLDs (no associated Input Macrocells, routes directly into PLDs).
3. CPLD output (External Chip Select). Does not consume Output Macrocells.
4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD.
5. Pin PD2 can optionally be configured as CSI
memory. Flash memory is disabled to conserve more power when CSI
connect CSI
active low I/O Memory Select strobe. See Figure 6.
low Data Memory Select strobe. See Figure 6.
Power Down mode is used. See Figure 6.
to ADSP-218X PWDACK output signal.
) from the DSP
) from the DSP.
) signal from the DSP.
, an active low Chip Select Input to select Flash
is logic high. Can
output which is the
output which is the active
10/63
TYPICAL CONNECTIONS
Figure 6 shows a typical connection scheme.
Many connection possibilities exist since most
DSM pins are multipurpose. The sc hem e i llustrated is ideal for a design that needs fast JTAG ISP,
Eight additional general I/O with PLD capability,
access to Flash mem ory as By te DM A or as Dat a
Overlay memory, and the DSP uses Power Down
mode. If your design needs more I/O, or Byte DM A
access to Flash memory is all that is needed (no
Data Overlay), or lowest power consumption is not
an issue, then consider the following options.
Port C JTAG: Figure 6 shows all six JTAG signals in use full time (not multiplexed with I/0). Using six-pin JTAG can reduce ISP time by as much
as 30% compared to four-pin JTAG. Alternatively,
four-pin JTAG (TMS, TCK, TDI, TDO) can be used
if more general I/O pins are needed and the few
extra seconds of programming time is not crucial,
freeing up pins PC3 and PC4. Other JTAG options
include mutiplexing JTAG pins with general I/O
(see “Programming In-Circuit using JTAG ISP” on
page 41 and Application Not e
ing JTAG at all. If no JTAG is used, the DSM device has to be programmed on a conventional
AN1153
) or not us-
DSM2180F3
programmer before it is installed on the circuit
board. Using no JTAG makes more I/O available.
Pin PD 1 . If Flash memory will be accessed only
using Byte DMA mode in your design, and no external Data Overlay memory accesses are used,
then pin PD1 can be used for other purposes
(MCUI/O, common CPLD clock input, external
chip select, or PLD input)
Pin PD 2 . If the DSP will not use Power Down
mode, then PD2 can be used for other purposes
(MCUI/O, external chip select, PLD input)
Pins PC2 and PC7. In Figure 6, these two pins
are used as dedicated address inputs connect ed
to DSP address outputs. This wil l route DSP address signals A16 and A17 directly into the DPLD.
Be aware that any free pin on Port B, Port C, or
Port D may be used for DSP address inputs, it
does not have to be pins PC2 and PC7.
Pin PB0. This pin is shown as a chip select for an
external peripheral device such as a 16450 or
16550 UART. Equivalent ly, any free pin on Ports
B, C, or D may be used for this.
11/63
DSM2180F3
Figure 6. Typical Connections
DEVICE
OPTIONAL
PARALLEL
(UART, ETC)
AI04912
CONNECTOR
JTAG-ISP
DATA
WRITE
DATA8..15
_WR
READ
_RD
ADDR0..2
_SELECT
ADDRESS
DSM2180F3
DATA8
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CHIP SEL
PB3
PB2
PB1
PB0
PA1
PA4
PA2
D10
DATA11
D11
PA3
DATA12
D12
DATA13
D13
PA6
PA5
PA7
WRITE
DATA14
DATA15
D14
D15
PA0
DATA9
DATA10
D9
D8
PD1
CNTL1
CNTL0
CNTL2
PD0
READ
I/O MEM SELECT
BYTE MEM SELECT
DATA MEM SELECT
_RD
_WR
_BMS
_DMS
_IOMS
PB7
PB6
PB5
PB4
ADIO0
ADIO1
ADIO2
ADDR1
ADDR0
ADDR2
ADDR3
N/C
A0A1A2A3A4A5A6A7A8
_PMS
_CMS N/C
ADIO3
ADIO4
ADDR4
ADIO5
ADIO6
ADDR6
ADDR5
ADIO7
ADDR7
TMS
TCK
PC1
PC0
ADIO8
ADIO9
ADDR8
ADDR9
A9
TSTAT
PC3
ADIO10
ADDR10
A10
_TERR
TDI
TDO
PC4
PC5
ADIO11
ADIO12
ADDR13
ADDR11
ADDR12
A11
A12
GND
_RESET
PC6
ADIO13
ADIO14
ADIO15
ADDR14
ADDR15
A13
D16
D17
PC2
PC7
ADDR17
ADDR16
D18
D19
_RESET
_RESET
POWER DOWN
_RESET
PWDACK PD2/_CSI
12/63
_BR
ADSP-218X
BUS_REQUEST
BUS_GRANT
_BG
_BGH
_PWD
GRANT_HUNG
PWR_DOWN_IN
CLKIN
XTAL
XTAL
CLOCK or
I/O
FL0
I/O
FL1
I/O
FL2
PF3
PF0/MODEA
PF1/MODEB
PF2/MOCEC
I/O
I/O
I/O
I/O
INTR/I_O
_IRQL0/PF5
_IRQL1/PF6
_IRQ2/PF7
_IRQE/PF4
INTR/I_O
INTR/I_O
INTR/I_O
SPORT0
SERIAL CHN
SERIAL
DEVICE
SPORT1
SERIAL CHN
SERIAL
DEVICE
_RESET
MEMORY MAP
Figure 7 shows a typical system memory map.
The nomenclature
Flash memory segm ent desi gnators.
fs0..fs7
are individual 16K Byte
csiop
designates the DSM control register block. The DSP
runs in Full Memory Mode. Memory contents of
the DSM device may lie in one or more of t hree different DSP address spaces; I/O space, Byte DMA
space, and/or External Data Overlay Memory
space. Since the DSM device is a byte-wide memory, it typically is not used in DSP Program Memory space (
PMS active).
The designer may easily specify memory mapping
in a point-and-click software environment using
PSD so ft E x pr es s
TM
. Since the memory mapping is
implemented with the DPLD and the Page Register, many possibilities exist. Figure 7 shows a typical memory map with the following attributes:
I/O Address Space. The 256 byte locations for
csiop
DSM control registers (
address space, selected by the DSP
) reside in DSP I/O
IOMS signal.
Since DSP I/O accesses are by 16 bits, not 8 bits,
the upper byte of a 16-bit DSP I/O access must be
ignored.
Byte DMA Address Space. The DSP m ay bootload or fetch overlay bytes from 128K Bytes of
Flash memory using the DSP BDMA channel. The
DSP may also write to Flash memory using the
Byte DMA channel. DSM Flash memory is accessed in 128K continuous byte address locations
DSM2180F3
through the BDMA channel and is selected whenever the DSP
Flash memory in the DSM device must be unlocked and written by the DSP one byte at a time,
checking status after each write (typical Flash
memory programming algorithm). A DMA channel
is not optimum for this scenario since the c han nel
must be initialized on each byte access. That is
why the 128K Bytes of F lash memory also lie in
DSP Data Overlay Memory space as described
next.
Data Overlay Memory Address Space. All
128K Bytes of Flash mem ory also reside in DSP
External Data Overlay Memory space, selected by
DMS, allowing more efficient byte writes to Flash
memory. The DSP uses its external data overlay
window of 8K locations to access external memory
as data. The DSP doubles the size of this window
to 16K locations by manipu lating its A13 address
line using its DMOVLAY register (See ADSP-218X
data sheets for details). Since all 128K Bytes of
Flash memory must be accessed through a window of only 16K locations, the DSP uses the Page
Register inside the DSM device to page through 8
pages of 16K Bytes as shown in Figure 7. Since
DSP Data accesses are by 16 bits, not 8 bi ts, t he
upper byte of a 16-bit DS P Data access m ust be
ignored.
BMS signal is active.
13/63
DSM2180F3
Figure 7. Typ ic a l Sy st em Mem ory Map
)
DMS
1FFFF
03FFF
A13 = 1
00000
A13 = 0
fs7
PAGE 7
A13 = 1
A13 = 0
fs6
PAGE 6
A13 = 1
A13 = 0
fs5
PAGE 5
A13 = 1
A13 = 0
fs4
PAGE 4
A13 = 1
A13 = 0
fs3
PAGE 3
A13 = 1
fs2
Flash Memory Paged Over 8 Pages
PAGE 2
PAGE 1
A13 = 0
A13 = 1
fs1
A13 = 1
AI04913
A13 = 0
A13 = 0
Space (
DSP Data Memory
)
BMS
fs7
16 KBytes
1FFFF
Flash Memory
1C000
1BFFF
Space (
DSP Byte DMA Memory
)
IOMS
Space (
DSP I/O Memory
1FFFF
fs6
16 KBytes
Flash Memory
18000
17FFF
fs5
16 KBytes
Flash Memory
14000
13FFF
fs4
16 KBytes
Nothing
Mapped
Flash Memory
10000
0FFFF
Nothing
Mapped
fs3
16 KBytes
Flash Memory
0C000
0BFFF
fs2
16 KBytes
Flash Memory
08000
07FFF
fs1
16 KBytes
PAGE 0
03FFF
Flash Memory
04000
03FFF
_cs_uart
8 UART REGS
00200
00208
fs0
16 KBytes
(8 KWords)
00000
fs0
16 KBytes
Flash Memory
00000
csiop
256 CONTROL REGS
00000
000FF
14/63
DSM2180F3
SPECIFYI N G MEM MAP WI TH PSD SO FT EXPRESS
The memory map shown in Figure 7 can be easily
specified with PSDsoft Express
click environment. PSDsoft Ex press
TM
in a point-and-
TM
will gener-
TM
ments of the ABEL language. Figure 8 shows the
resulting equations generated by PSDsoft ExpressTM.
ate Hardware Definition Language (HDL) state-
Figure 8. HDL Statements Generated from PSDsoft Express to Implement Memory M ap
csiop = ((address >= ^h0000) & (address <= ^h00FF) & (!_ioms & _dms & _bms));
fs0 = ((address >= ^h0000) & (address <= ^h3FFF) & (_ioms & _dms & !_bms))
# ((page == 0) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs1 = ((address >= ^h4000) & (address <= ^h7FFF) & (_ioms & _dms & !_bms))
# ((page == 1) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs2 = ((address >= ^h8000) & (address <= ^hBFFF) & (_ioms & _dms & !_bms))
# ((page == 2) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs3 = ((address >= ^hC000) & (address <= ^hFFFF) & (_ioms & _dms & !_bms))
# ((page == 3) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs4 = ((address >= ^h10000) & (address <= ^h13FFF) & (_ioms & _dms & !_bms))
# ((page == 4) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs5 = ((address >= ^h14000) & (address <= ^h17FFF) & (_ioms & _dms & !_bms))
# ((page == 5) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs6 = ((address >= ^h18000) & (address <= ^h1BFFF) & (_ioms & _dms & !_bms))
# ((page == 6) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
fs7 = ((address >= ^h1C000) & (address <= ^h1FFFF) & (_ioms & _dms & !_bms))
# ((page == 7) & (address >= ^h0000) & (address <= ^h3FFF) & (_ioms & !_dms &
! _cs_uart = ((address >= ^h0200) & (address <= ^h0207) & (!_ioms & _dms & _bms));
_bms));
_bms));
_bms));
_bms));
_bms));
_bms));
_bms));
_bms));
Specifying these equations using PSDsoft Ex-
TM
press
is very simple. Figure 9 shows how to
specify the equation for the 16K Byt e Fl ash memory segment,
. Notice how
fs2
can reside in two
fs2
different address spaces depending on the state of
the control signals from the DSP (
IOMS, DMS, or
BMS) and the memory page number coming from
the DSM Page Register outputs. This specification
process is repeated for all other Flash memory
csiop
segments, the
register block, and any exter-
nal chip select signals (UART , etc.).
15/63
DSM2180F3
Figure 9. PSDsoft ExpressTM Memory Mapping
AI03779
16/63
RUNTIME CONTROL REGISTER DEFINITION
There are up to 256 addresses decoded inside the
DSM device for control and status information. 27
of these locations contain registers that the DSP
can access at runtime. The base address of this
block of 256 locations is referred to in this manual
as
csiop
(Chip Select I/O Port). Table 4 lists the 27
registers and their offsets (in hex) from the
csiop
base address needed to access individual DSM
control and status registers. Th e DSP will a ccess
these registers in I/O memory space using its
IOMS
DSM2180F3
strobe. These registers are accesses in bytes, so
the DSP should ignore the u pper by te of its 16-bit
I/O access.
Note1: All
reset.
Note2: Do not write to unused locations within the
csiop
logic zero.
csiop
registers are cleared to logic 0 at
block of 256 registers. They should remain
Table 4.
Data In 01 10 11
Data Out 05 12 13
Direction 07 14 15
Drive Select 09 16 17
Input Macrocells 0B 18 Read to obtain state of IMCs. No writes.
Enable Out 0D 1A 1B
Output Macrocells AB 20
Output Macrocells BC 21
Mask Macrocells AB 22
Mask Macrocells BC 23
CSIOP
Register Name Port B Port C P ort D Other Description
Registers and their Offsets (in hex)
MCUI/O input mode. Read to obtain current logic level of
Port pins. No writes.
MCU I/O output mode. Write to set logic level on Port
pins. Read to check status.
MCU I/O mode. Configures Port pin as input or output.
Write to set direction of Port pins.
Logic 1 = out, Logic 0 = in. Read to check status.
Write to configure Port pins as either standard CMOS or
Open Drain on some pins, while selecting high slew rate
on other pins. Read to check status.
Read to obtain the status of the output enable logic on
each I/O Port driver. No writes.
Read to get logic state of output of OMC bank AB.
Write to load registers of OMC bank AB.
Read to get logic state of output of OMC bank BC.
Write to load registers of OMC bank BC.
Write to set mask for loading OMCs in bank AB. A logic
1 in a bit position will block reads/writes of the
corresponding OMC. A logic 0 will pass OMC value.
Read to check status.
Write to set mask for loading OMCs in bank BC. A logic
1 in a bit position will block reads/writes of the
corresponding OMC. A logic 0 will pass OMC value.
Read to check status.
Flash Sector Protect C0
Security Bit C2
JTAG Enable C7
PMMR0 B0 Power Management Register 0. Write and read.
PMMR2 B4 Power Management Register 2. Write and read.
Page E0 Memory Page Register. Write and read.
Read to determine Flash Sector Protection Setting. No
writes.
Read to determine if DSM devices Security Bit is active.
Logic 1 = device secured. No writes.
Write to enable JTAG Pins (optional feature). Read to
check status.
17/63
DSM2180F3
DETAILED OPERATION
Figure 5 shows major functional areas of the device :
■ Flash Memory
■ PLDs (DPLD, CPLD, Page Register)
■ DSP Bus Interface (Address, Data, Control)
■ I/O Por ts
■ Runtime Control Registers
■ JTAG ISP Interface
The following describes these functions in more
detail.
Flash Memory
The Flash memory array is divided evenly into
eight equal 16K byt e sectors. Each sector is selected by the DPLD can be separately protected
from program and erase cycles. This configuration
is specified by using PSDsoft Express
Memory Sector Select Signals. The DPLD generates the Select signals for all the internal memory blocks (see Figure 14). Each of the eight sectors
of the Flash memory has a Select signal (
FS7
) which contains up to three product terms.
Having three product terms for each Selec t signal
allows a given sector to be mapped into multiple
areas of system memory.
Ready/Busy
output the Ready/
output on Ready/
(PC3 ). This signal can be used to
Busy status of the device. The
Busy (PC3) is a 0 (Busy) when
Flash memory is being written,
memory is being erased. The output is a 1 (Ready)
when no Write or Erase cycle is in progress. This
signal may be polled by the DSP or used as a DSP
interrupt to indicate when an erase or program cycle is complete.
TM
.
or
when Flash
FS0-
Memory Operation. The Flash memory is accessed through the DSP Address, Data, and Control Bus Interface. The DSP can access Flash
memory as BDMA mode or as External Data
Memory Overlay. But from the DSM perspective, it
sees either type of access as a series of byte operations (reads and writes). If the DSP accesses
the DSM in BDMA mode, then the DSP BDMA
channel must be initia lized and run for eac h byte
(or block of bytes) read from Flash memory or it
must initialize the DMA channel for each byte written to Flash mem ory. Alternat ively, if t he DS P ac cesses the DSM in External Data Memory Overlay
mode, then the DSP mu st only ensure the PSD
Page Register and the DSP DMOVLAY register
contains the correct va lue, then it performs a normal data read or data write operat ion without the
burden of initializing the BDMA channel for each
operation (upper byte of 16-bit word is ignored).
DSPs and MCUs cannot write to Flash memory as
it would an SRAM device. Flash memory must first
be “unlocked” with a special sequence of byte
write operations to invoke an internal algorithm,
then a single data byte is written to the Flash memory array, then programming status is chec ked by
a byte read operation or by checking the Ready/
Busy
pin (PC3). Table 5 lists all of the special instruction sequences to program (write) data to the
Flash memory a rray, erase the array, and check
for different types of s tatus from t he array. T hese
instruction sequences are different combinations
of individual byte write and byte read operations.
Once the Flash memory array is programmed
(written) and then it is in “Read Array” mode, the
DSP will read from Flash memory just as if would
from any 8-bit ROM or SRAM device.
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DSM2180F3
Table 5. Instruction Sequences
Instruction
Sequence
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
1,2,3,4
Read byte
Read Memory
Contents
5
from any
valid Flash
memory addr
Read identifier
Read Flash
Identifier
6,7
Write AAh to
XX555h
Write 55h
to XXAAAh
Write 90h
to XX555h
with addr lines
A6,A1,A0 =
0,0,1
Read Memory
Sector Protection
6,7,8
Status
Program a Flash
Byte
Flash Bulk Erase
Flash Sector
10
Erase
Write AAh to
XX555h
Write AAh to
XX555h
Write AAh to
9
XX555h
Write AAh to
XX555h
Write 55h
to XXAAAh
Write 55h
to XXAAAh
Write 55h
to XXAAAh
Write 55h
to XXAAAh
Write 90h
to XX555h
Write A0h
to XX555h
Write 80h
to XX555h
Write 80h
to XX555h
Read identifier
with addr lines
A6,A1,A0 =
0,1,0
Write
(program)
data to addr
Write AAh to
XX555h
Write AAh to
XX555h
Write 55h
to XXAAAh
Write 55h
to XXAAAh
Write 10h
to XX555h
Write 30h
to another
Sector
Write 30h
to another
Sector
Write B0h to
Suspend Sector
11
Erase
address that
activates any
of FS0 - FS7
Write 30h to
Resume Sector
12
Erase
addr that
activates any
of FS0 - FS7
Write F0h to
Reset Flash
6
address that
activates any
of FS0 - FS7
Note: 1. All v al ues are in hexad ecimal, X = Don’t Care
2. A desired internal Flash memory sector select signal (FS0 - FS7) must be active for each write or read cycle. Only one of FS0 - FS7
will be active at any given time depending on the address presented by the DSP and the memory mapping defined in PSDsoft Expres s . F S 0 - F S 7 are active high logic in ternally.
3. DS P addres ses A17 through A 12 are Don’t Care duri ng the inst ruction s equence de coding . Only addre ss bit s A11-A0 are used
during Flash memory instruction sequence decoding bus cycles. The individual sector select signal (FS0 - FS7) which is active during the instruction sequ ences determi nes the comple te address.
4. For write operations, addresses are latched on the falling edge of Write Strobe (WR
Write Strobe (WR
5. No Unlock or Inst ruction cycles are required when the dev i ce is in the Read A rray mode. Operation is like reading a ROM de vice.
6. The Reset Flash instruction is required to return to the normal Read Array mode if the Error Flag (DQ5) bit goes High, or after reading the Flash I dentifier or af t er reading the Sector Prote ct i on Status.
7. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruction sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Identifier or Sector Protection Status.
8. T he data is 00h f or an unprote cted sector, and 01h for a pr otected s ector. In the fo urth cycle, the Sector Sel ect is acti ve, and
(A1,A0)= (1,0)
9. Directing this comma nd to any in dividua l active Flash memory seg ment (FS 0 - FS7) will invoke th e bulk era se of all eight Flash
memory sectors.
10. DSP writes command sequece to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. The byte
30h must be ad dressed to one of the ot her Flas h memory s egment s (FS0 - FS 7) for each addition al segme nt (write 30h to any
address within a desired sector). No more than 80uS can elapse between subseq uent additiona l sector erase commands.
11. The system m ay per form R ead and P ro gram cyc les i n non- era sin g sec tors , rea d the Flas h ID o r r ead t he Se ctor Prot ect Sta tus,
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase mode.
, CNTL0)
, CNTL0), Dat a i s latched on the rising edge of
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