SGS Thomson Microelectronics CB45000 Datasheet
FEATURES
■ 0.35 micron 5 layer metal HCMOS6 process,
retrograde well technology, low resistance
salicided active areas and polysilicide gates.
■ 3.3 V optimized transistor with 5 V I/O inter-
face capability
■ 2 - input NAND delay of 160 ps (typ) with
fanout = 2.
■ Broad I/O functionality including Low Voltage
CMOS, Low Voltage TTL and LVDS. Driving
capability to ISA, EISA, PCI, MCA, and SCSI
interface levels
■ High drive I/O; capability of sinking up to 24
mA with slew rate control, current spike suppression and impedance matching.
■ Generators to support Single Port RAM,
Dual Port RAM, and ROM with BIST options.
■ DRAM integration in ASIC methodology
■ Extensive embedded function library includ-
ing ST DSP and micro cores, third party
micros and Synopsys synthetic libraries.
■ Fully independent power and ground config-
urations for inputs, core and outputs.
■ I/O ring capability up to 1000 pads.
■ Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts typical value
CB45000 SERIES
HCMOS6 STANDARD CELLS
■ Oscillators for wide frequency spectrum.
■ Broad range of 500+ SSI cells
■ Design For Test features including IEEE
1149.1 JTAG Boundary Scan architecture.
■ Cadence, Mentor and Synopsys based
design systems with interfaces from multiple
workstations.
■ Broad ceramic and plastic package range.
CB45000 Super-Integration
Cost Effective Product
ROM
DSP
■ Architecture Partitioning
■ Trouble free integration
■ Application Specific
Your Product is Unique
ST20DPRAM
March 1998 1/16
■ User specified cell integration
■ Design Confidentiality
■ IP fully re-usable
CB45000 SERIES
GENERAL DESCRIPTION
The CB45000 standard cell series uses a high
performance, low voltage, 5 level metal,
HCMOS6 0.35 micron process to achieve subnanosecond internal speeds while offering very
low power dissipation and high noise immunity.
With an average routed logic density of 14000
2
gates/mm
, the CB45000 family allows the
design of highly complex devices. The potential
available gate count ranges above 3 Million
equivalent gates. De vices can operate o v er a Vdd
voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over
750 signals and 1000 pins based upon the
package technology utilized. A flexible I/O
approach has been developed to provide an
Figure 1
Process Overview
optimum solution for today’s complex system
problems of drive levels and specialized interface
standards.
The product offers a variable bonding approach
supporting pad spacings from 80µ upwards and
supports staggered pad rows to address today’s
bonding technologies. Additional flexibility to
support 65µ and 50µ pad spacing will be
available in the near future.
The I/O can be configured for circuits ranging
from low voltage CMOS and TTL to low swing
differential circuits (LVDS) and the 1Gigabit per
second high speed link. Standards like SCSI, 3.3
and 5 Volt PCI and other 5.0 Volt interfaces are
currently being addressed.
Metal 3 : Al-Cu
Metal 5 : Al-Cu
Metal 4 : Al-Cu
Metal 2 : Al-Cu
Metal 1 : W
2/16
CB45000 SERIES
TECHNOLOGY OVERVIEW
A major feature of the HCMOS6 process is
salicided active areas. This results in source
drain areas that are on the order of one to two
ohms resistance as opposed to the hundreds or
thousands of ohms of source drain resistance in
non-salicided technologies. This very low
resistance is one reason that very low transistor
widths could be utilized in the cell design since
drive is not lost due to source drain resistance.
This use of low width transistors results in lower
capacitance loading of the gates due to the
smaller areas utilized. Low resistance, low
capacitance, and small gates results in low power
usage for inverters as compared to previous
technologies. The reduction in power
consumption allows the usage of salicided active
stripes to distribute power internally to the simple
cell, replacing, in some cases, the usage of the
first metal layer. This saves silicon area by
allowing greater density, permeability and
routability of the cells resulting in greater overall
circuit density.
The other major feature of the HCMOS6 process
is five metal layer interconnect using CMP
(Chemical Mechanical Polishing) planarization.
The use of CMP for improved planar ity between
metal layers allows the use of additional
interconnect layers without yield degradation,
improving density whilst retaining low costs.
The power distribution methodology provides
separate internal distributions to improve product
noise margin and reduce power loss. The three
supplies are:
■ Internal Vdd and Vss
Serves the core cells and the prebuffer sections of the I/O
■ External Vdd and Vss
Serves the output transistors only
■ Receiver Vdd and Vss
Serves the first stages of the receiver cells.
Optional distributions for 5.0V interface and other
standards can be utilized as necessary.
3/16
CB45000 SERIES
10 Ê
LIBRARY
The CB45000 Series library is organized into four
categories:
■ SSI cell library
■ IO Cell library
■ Macrofunctions
■ Module generators
SSI CELL LIBRARY OVERVIEW
The design of the CB45000 family has been
optimized to allow extremely high density, high
speed and low power designs. For these reasons
a wide range of cells with different ranges of
driving capability are available in the library.
The library cells have been optimized in term of
functional and electrical parameters in order to
have:
■ Good balancing
■ Maximum speed
■ Optimum Threshold voltage
m
■ Symmetric Vdd/Vss Noise margin
■ Minimum Power-Speed figure
The geometrical aspect of the cells was
configured to allow extremely dense design, fully
exploiting the features of the Place and Route
tool in terms of horizontal and vertical routing
grids. For Place and Route, up to five levels of
metal are utilized. Intracell wiring is limited as far
as possible to first metal, with second, third and
fourth metal levels dedicated to interconnect
wiring and power distribution. The fifth metal is
used for power and clock bussing.
CORE LOGIC
The propagation delays shown in the CB45000
data book are given for nominal processing, 3.3V
operation, and 25 C temperature conditions.
However there are additional factors that affect
the delay characteristics of the macrocells. These
include loading due to fanout and interconnect
routing, voltage supply, junction temperature of
the device, processing tolerance and input signal
transition time.
Prior to physical layout, the design system can
estimate the delays associated with any critical
path. The impact of the placement and routing
can be accurately RC back annotated from the
layout for final simulations of critical timing. The
effects of junction temperature, (K
) and voltage
T
supply (KV) on the delay numbers are
summarized in Table 2 and Table 2. A third factor,
is associated with process variation. This
multiplier has a minimum of 0.8 and a maximum
of 1.2.
Figure 2. ND2 Core Cell
4/16
Table 1 Junction Temperature Multipliers
TemperatureoCK
T
-55 0.77
-40 0.83
25 1.00
70 1.13
85 1.17
125 1.27
CB45000 SERIES
Table 2 Voltage Multipliers
V
DD
K
V
2.7 1.20
3.0 1.11
3.3 1.00
3.6 0.94
I/O BUFFER LIBRARY
The CB45000 does not use traditional I/O cell
design; SGS-THOMSON was one of the pioneers
of the emerging “Flexible I/O” approach and the
CB45000 features variable bonding and a flexible
output transistor scheme based on a predefined
Figure 3
Flexible IO Buffer Technology
EDGE OF DIE
GUARDRING
set of I/O transistor subcells.
These subcells can be quickly configured using
metallization layers to confor m to a variety of I/O
specifications whilst maintaining optimal ESD
protection levels and latch-up prevention
characteristics.
The I/O circuitry also includes subcells of
specialized transistors that are used to form the
slew rate control sections of each I/O line.
Current spike suppression logic ensures that
conducting transistors are turned off before the
opposing set are turned on.
The bond pad itself is variable in terms of pitch
and size and even supports staggered bonding
methodologies. This is becoming far more
Programmable pad locations allows
one IO cell library to be used for both
staggered and linear bonding.
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
EDGE OF DIE
GUARDRING
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
ESD CLAMP
STRUCTURES
OUTPUT
DRIVE
TRANSISTORS
DIODES
LOGIC CIRCUITS
TEST INTERFACE
SLEW CONTROL
DIE CORE
DIE CORE
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