SGS Thomson Microelectronics 74VHCT16373ATTR Datasheet
WITH 3-STATE OUTPUTS NON INVERTING
■ HIGH SPEED:
t
= 5.0 ns (TYP.) at VCC=5V
PD
■ LOW POWER DISSIPATION:
I
=4µA (MAX.) at TA=25°C
CC
■ COMPATIBLE WITHTTL OUTPUTS:
V
=2V (MIN.) VIL= 0.8 (MAX.)
IH
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=8mA(MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
PHL
■ OPERATING VOLTA GE RANGE:
V
(OPR) = 4.5V to 5.5V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: V
= 0.9V (MAX.)
OLP
74VHCT16373A
16-BIT D-TYPE LATCH
TSSOP
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74VHCT16373ATTR
PIN CONNECTION
DESCRIPTION
The 74VHCT16373A is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-la yer meta l
wiring C
2
MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE
).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE
) input is low, the nQ outputs will
be in a normal lo gic s tate (high or low logic level);
when nOE
is at h igh level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 t o 7V can be accepted on inputs with no
regard to t he supply voltage. This device can be
usedto interface 5V to 3V.
All inputs and outpu ts are equipped with protection circuits against static discharge, giving them
2KV ESD immunity and transient excess vo ltage.
1/10February 2003
74VHCT16373A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
13,14,16,17,
19, 20, 22, 23
24 2OE
25 2LE Latch Enable Input
36,35,33,32,
30, 29, 27, 26
47,46,44,43,
41, 40, 38, 37
48 1LE Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
1Q0 to 1Q7 3-State Outputs
2Q0 to 2Q7 3-State Outputs
2D0 to 2D7 Data Inputs
1D0 to 1D7 Data Inputs
GND Ground (0V)
CC
3 State Output Enable
Input (Active LOW)
3 State Output Enable
Input (Active LOW)
Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUT
OE
HXX Z
L L X NO CHANGE *
LHL L
LHH H
X : Don‘tCare
Z : High Impedance
* : Qoutputs are latched at the time when the LE input is taken low
logiclevel.
LE D Q
IEC L OGIC SYMBOLS
2/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
74VHCT16373A
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage -0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0 V
-0.5 to +7.0 V
V
-20 mA
± 20 mA
± 25 mA
± 75 mA
-65 to +150 °C
300 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
dt/dv Input Rise and Fall Time (note 1) (Vcc= 5.0±0.5V)
Supply Voltage
CC
Input Voltage
I
Output Voltage 0 to V
O
Operating Temperature
op
4.5 to 5.5 V
0 to 5.5 V
CC
-55 to 125 °C
0 to 20 ns/V
V
1) VINfrom0.8V to 2.0V
3/10
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