SGS Thomson Microelectronics 74VHC573 Datasheet

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74VHC573

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

■ HIGHSPEED:t

■ LOW POWER DISSIPATION:

=4 µA (MAX.) at TA=25oC

I

CC

■ HIGHNOISEIMMUNITY:

V

NIH=VNIL

■ POWERDOWNPROTECTIONON INPUTS

■ SYMMETRICALOUTPUTIMPEDANCE:

|=IOL=8 mA(MIN)

|I

OH

■ BALANCEDPROPAGATIONDELAYS:

t

≅ t

PLH

■ OPERATINGVOLTAGERANGE:

V

(OPR)= 2Vto5.5V

CC

■ PINANDFUNCTION COMPATIBLEWITH

=28%VCC(MIN.)

PHL

=5.0ns(TYP.)atVCC=5V

PD

74SERIES573

■ IMPROVEDLATCH-UPIMMUNITY

■ LOWNOISE:V

= 0.9V(Max.)

OLP

DESCRIPTION

The 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiringC

2

MOStechnology.

This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).

While the LE input is held at a high level, the Q

M

(Micro Package)

(TSSOPPackage)

T

ORDERCODES :

74VHC573M 74VHC573T

outputswill follow thedata inputs precisely.
When the LE is taken low, the Q outputs will be

latchedpreciselyat thelogic level of D input data.
While the (OE) input is low, the 8 outputs will be

in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.

Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.

All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGICSYMBOLS

June 1999

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74VHC573

INPUT EQUIVALENTCIRCUIT PIN DESCRIPTION

PI N No SYMB OL NAME AND FU NCTION

1 OE 3 State Output Enable

2, 3, 4,
5, 6, 7,

8, 9

12, 13, 14,
15, 16, 17,

18, 19

11 LE Latch Enable

10 GND Ground (0V)
20 V

TRUTH TABLE

INPUTS OUTPUTS

OE LE D Q

HXXZ

L L X NO CHANGE *
LHLL
LHHH

X:Don’tcare
Z:Highimpedance
*Qoutputsarelatched atthetime whentheLEinputistakenlowlogiclevel.

D0 to D7 Data Inputs

Q0 to Q7 3 State Latch Outputs

CC

Input (Active LOW)

Input

Positive Supply Voltage

LOGICDIAGRAM

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74VHC573

ABSOLUTE MAXIMUM RATINGS

Symb o l Paramet er Val u e Uni t

V

V

V

I

I

OK

I

or I

I

CC

T

T

AbsoluteMaximumRatingsarethosevaluesbeyond whichdamage tothedevicemayoccur.Functionaloperationunderthese conditionisnotimplied.

RECOMMENDEDOPERATINGCONDITIONS

Symb o l Paramet er Value Un it

V

V

V

T

dt/dv

1)VINfrom30%to70%ofV

Supply Voltage -0.5 to +7.0 V

CC

DC Input Voltage -0.5 to +7.0 V

I

DC Output Voltage -0.5 to VCC+ 0.5 V

O

DC Input Diode Current - 20 mA

IK

DC Output Diode Current ± 20 mA
DC Output Current

O

DC VCCor Ground Current

GND

Storage Temperature -65 to +150

stg

Lead Temperature (10 sec) 300

L

Supply Voltage 2.0 to 5.5 V

CC

Input Voltage 0 to 5.5 V

I

Output Voltage 0 to V

O

Operating Temperature -40 to +85

op

(V

CC
CC

=3.3±0.3V)
=5.0±0.5V)

Input Rise and Fall Time (see note 1) (V

CC

25 mA

±

75 mA

±

CC

0 to 100

0to20

o

C

o

C

V

o

C

ns/V
ns/V

DC SPECIFICATIONS

Symb o l Para met er Test C o n diti ons Val u e Uni t

=25oC -40 to 85oC

V

CC

(V)

High Level Input

V

IH

Voltage

V

Low Level Input

IL

Voltage

V

High Level Output

OH

Voltage

2.0 1.5 1.5

3.0 to 5.5 0.7V

2.0 0.5 0.5

3.0 to 5.5 0.3V

2.0 IO=-50µA 1.9 2.0 1.9

3.0 I

4.5 I

3.0 I

4.5 I

Low Level Output

V

OL

Voltage

2.0 IO=50 µ A 0.0 0.1 0.1

3.0 I

4.5 I

3.0 I

4.5 I

High Impedance

I

OZ

Output Leakage

5.5

VO=VCCor GND

Current
Input Leakage Current 0 to 5.5 VI= 5.5V or GND

I

I

Quiescent Supply

I

CC

5.5 VI=VCCorGND 4 40

Current

=-50µA 2.9 3.0 2.9

O

=-50 µA 4.4 4.5 4.4

O

=-4 mA 2.58 2.48

O

=-8 mA 3.94 3.8

O

=50µA 0.0 0.1 0.1

O

=50 µA 0.0 0.1 0.1

O

=4 mA 0.36 0.44

O

=8 mA 0.36 0.44

O

VI=VIHor V

IL

T

A

Min. Typ. Max. Min. Max.

CC

0.7V

CC

0.3V

CC

±0.25 ±2.5 µA

0.1

±

1.0

±

CC

µ
µ

V

V

V

V

A
A

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