1/12February 2003
■ 3.6V TOLERANT INPUTS AND OUTPUTS
■ HIGH SPEED :
t
PD
= 3.4 ns (MAX.) at VCC=3.0to3.6V
t
PD
= 4.8 ns (MAX.) at VCC=2.3to2.7V
■ POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=IOL= 12mA (MIN) at VCC=3.0V
|I
OH
|=IOL=8mA(MIN)atVCC=2.3V
■ 26Ω SERIE RESISTORS IN OUTPUTS
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.3V to 3.6V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H162374
■ BUS HOLD PROVIDED ON DATA INPUTS
■ LATCH-UP P ERFO RMANCE EXCEEDS
300mA (JESD 17)
■ ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74VCXH162374 is a low voltage CMOS 16
BIT D-TYPEFLIP-FLOP with3 STATEOUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C
2
MOS
technology. It is ideal for low power and very high
speed 2.3 to 3.6V applications; it can be interfac ed
to 3.6V signal environment for both inputs and
outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two out put enable
inputs (nOE
).
Onthepositivetransitionofthe(nCK),thenQ
outputs will be set to t he logic state that were
setup at the nD inputs.
While the (nOE
) input is low, the 8 outputs (nQ)
will be in a normal state (HIGH or LOW logic lev el)
and while high level the outputs will be in a high
impedance state.
Any output control does not affect the internal
operation of flip flops ; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Bus hold on data inputs is provided in order to
eliminate the need for exte rnal pull-up or
pull-down resistor.
74VCXH162374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AN D OUTPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74VCXH162374TTR
TSSOP
PIN CO NNE CTION