1/9July 2001
■ HIGH SPEED:
t
PD
= 5.0 ns (TYP.) at VCC = 3.3V
■ 5V TOLERANT INPUTS
■ POWER-DOWN PROTECTION ON INPUTS
■ INPUT VOLTAG E LEVEL:
V
IL
= 0.8V, VIH = 2V at VCC =3V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at VCC =3.3V
■ SYMMETRICAL OUTPUT IMPED ANCE:
|I
OH
| = IOL = 4 mA (MIN) at VCC =3V
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX541 is a low voltage CMOS OCTAL
BUS BUFFER with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The 3 STATE control gate opera tes as two input
AND such that if either G1
or G2 are high, all eight
outputs are in the high impedance state.
In order to enhance PC board layout, the
74VHC541 offers a pinout having inputs and
outputs on opposite sides of the package.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX541
LOW VOLTAGE CMOS OCTAL BUS BUFFER
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVX541M 74LVX541MTR
TSSOP 74LVX541TTR
TSSOPSOP