SGS Thomson Microelectronics 74LVX373TTR, 74LVX373MTR, 74LVX373M Datasheet

74LVX373

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH

(3-STATE NON INV.) WITH 5V TOLERANT INPUTS

■ HIGH SPEED:

t

=5.8ns (TYP.) at VCC = 3.3V

PD

■ 5V TOLERANT INPUTS

■ POWER-DOWN PROTECTION ON INPUTS

■ INPUT VOLTAGE LEVEL:

V

= 0.8V, VIH = 2V at VCC =3V

IL

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ LOW NOISE:

V

= 0.3V (TYP.) at VCC =3.3V

OLP

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 4 mA (MIN) at VCC =3V

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATING VOLTAGE R ANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

PHL

(OPR) = 2V to 3.6V (1.2V Data Retention)

74 SERIES 373

■ IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C

2

MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE
While the LE in put is held at a high level, the Q
outpu ts w ill f ollo w t he da ta input precisely .

PIN CONNECTION AND IEC LOGIC SYMBOLS

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74LVX373M 74LVX373MTR

TSSOP 74LVX373TTR

When the LE i s taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE

) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving

).

them 2KV ESD immunity and transient excess
voltage.

1/10July 2001

74LVX373

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1OE

3, 4, 7, 8, 13,

14, 17, 18

2, 5, 6, 9, 12,

15, 16,19

11 LE Latch Enable Input
10 GND Ground (0V)
20 V

TRUTH TABLE

INPUTS OUTPUT

D0 to D7 Data Inputs

Q0 to Q7 3-State Outputs

CC

3 State Output Enable
Input (Active LOW)

Positive Supply Voltage

OE

LE D Q

HXXZ

L L X NO CHANGE*
LHLL
LHHH

X : Don’t Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level

LOGIC DIAGRAM

This log i c diagram has not be used to estimat e propagation del ays

2/10

74LVX373

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

I

or I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V

V

T

dt/dv

1) Truth T abl e guaranteed: 1.2V to 3.6V

2) V

from 0.8V to 2.0V

IN

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 2) (V

CC

= 3V)

-0.5 to +7.0 V

-0.5 to +7.0 V

- 20 mA

± 20 mA
± 25 mA
± 50 mA

-65 to +150 °C
300 °C

2 to 3.6 V
0 to 5.5 V

CC

-55 to 125 °C
0 to 100 ns/V

V

V

DC SPECIFICATIONS

Symbol Parameter

V

V

V

V

I

I

High Level Input

IH

Voltage

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

High Impedance

OZ

Output Leakage
Current

I

Input Leakage

I

Current
Quiescent Supply

CC

Current

Test Condition Value

V

(V)

CC

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

T

2.0 1.5 1.5 1.5

2.0 2.0 2.0

3.6

2.4 2.4 2.4

2.0 0.5 0.5 0.5

3.6 0.8 0.8 0.8

2.0

3.0

2.0

3.0

3.6

3.6

3.6

IO=-50 µA
I

=-50 µA

O

I

=-4 mA

O

IO=50 µA
I

=50 µA

O

I

=4 mA

O

= VIH or V

V

I

IL

VO = VCC or GND

= 5V or GND

V

I

= VCC or GND

V

I

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

2.58 2.48 2.4

0.0 0.1 0.1 0.1

0.0 0.1 0.1 0.1

0.36 0.44 0.55

±0.25 ± 2.5 ± 5 µA

± 0.1 ± 1 ± 1 µA

44040µA

Unit

V3.0

V3.0 0.8 0.8 0.8

V3.0

V3.0

3/10

74LVX373

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

V
V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)

V

CC

(V)

3.3

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

Dynamic High

V

IHD

Voltage Input

3.3 2.0

= 50 pF

C

L

(note 1, 3)
Dynamic Low

V

ILD

Voltage Input

3.3 0.8

(note 1, 3)

1) Worst c ase package.

2) Max number of output s defined as (n). Dat a i nputs are driven 0V to 3.3V, (n -1) outputs switc hi ng and one out put at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V

), f=1MHz.

IHD

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)

Test Condition Value

T

Symbol Parameter

t

Propagation Delay

PLH
PHL

Time
LE to Q

t

3.3

3.3
t
t

Propagation Delay

PLH

Time

PHL

D to Q

3.3

3.3

PZL
PZH

Output Enable
Time

t
t

3.3

3.3
t

t

t

OSLH

t

OSHL

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the same directio n, either HIGH or LO W

2) Param eter guarante ed by design
(*) Vol tage rang e i s 3.3V ±

Output Disable

PLZ

Time

PHZ

LE pulse Width,

t

W

HIGH
Setup Time D to LE

t

S

HIGH or LOW
Hold Time D to LE

t

h

HIGH or LOW
Output to Output

Skew Time (note
1,2)

3.3

3.3

3.3

3.3

3.3

0.3V

C

V

CC

(V)

2.7

2.7

2.7

2.7

L

(pF)

15 7.5 14.5 1.0 17.5 1.0 18.5
50 10.0 18.0 1.0 21.0 1.0 22.0

(*)

15 6.8 10.3 1.0 12.0 1.0 13.0

(*)

50 9.3 13.8 1.0 15.5 1.0 16.5
15 7.7 15.0 1.0 18.5 1.0 19.5
50 10.2 18.5 1.0 22.0 1.0 23.0

(*)

15 5.8 9.7 1.0 11.5 1.0 12.5

(*)

50 8.5 13.2 1.0 15.0 1.0 16.0

2.7 15 7.7 15.0 1.0 18.5 1.0 19.5

2.7 50 10.2 18.5 1.0 22.0 1.0 23.0

(*)

15 6.0 9.7 1.0 11.5 1.0 12.5

(*)

50 8.5 13.2 1.0 15.0 1.0 16.0

2.7 50 9.8 18.0 1.0 21.0 1.0 22.0

(*)

50 8.2 12.8 1.0 14.5 1.0 15.5

2.7 50 6.5 7.5 7.5

(*)

50 5.0 5.0 5.0

2.7 50 6.0 6.0 6.0

(*)

50 4.0 4.0 4.0

2.7 50 1.0 1.0 1.0

(*)

50 1.0 1.0 1.0

2.7 50 0.5 1.0 1.5 1.5

(*)

50 0.5 1.0 1.5 1.5

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

), 0V to threshold

ILD

-40 to 85°C -55 to 125°C

Unit

V

Unit

ns

ns

ns

ns

ns

ns

ns

ns

4/10

74LVX373

CAPACITIVE CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

C

C

C

Input Capacitance

IN

Output

OUT

Capacitance
Power Dissipation

PD

Capacitance

V

CC

(V)

3.3 5 10 10 pF

3.3 10 pF

= 10MHz

3.3

f

IN

= 25°C

A

Min. Typ. Max. Min. Max. Min. Max.

40 pF

(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I

TEST CIRCUIT

-40 to 85°C -55 to 125°C

= CPD x VCC x fIN + ICC/8 (per c ircuit )

CC(opr)

Unit

TEST SWITCH

t

, t

PLH

PHL

, t

t

PZL

PLZ

t

, t

PZH

PHZ

CL =15/50pF or equivalent (includes jig and probe capacitance)

= R1 = 1KΩ or equivalent

R

L

= Z

R

of pulse generator (typically 50Ω)

T

OUT

Open

V

CC

GND

5/10

74LVX373

WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)

WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)

6/10

WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

74LVX373

7/10

74LVX373

SO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096

b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012

C 0.5 0.020

c1 45° (typ.)

D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419

e 1.27 0.050
e3 11.43 0.450

F 7.40 7.60 0.291 0.300

L 0.50 1.27 0.020 0.050

M 0.75 0.029
S8° (max.)

mm. inch

8/10

PO13L

74LVX373

TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0° 8°0° 8°

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

K

c

L

E

D

E1

PIN 1 IDENTIFICATION

1

0087225C

9/10

74LVX373

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previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.

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