1/10July 2001
■ HIGH SPEED:
f
MAX
= 150 MHz (TYP.) at VCC = 3.3V
■ 5V TOLERANT INPUTS
■ POWER-DOWN PROTECTION ON INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, VIH = 2V at VCC =3V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at TA=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at VCC =3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = IOL = 4 mA (MIN) at VCC =3V
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLT AG E R ANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX273 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP WITH CLEAR fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
Information signals applied to D inputs are
transferred to the Q o utputs on the positive going
edge of the clock pulse.
When the CLE AR
input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX273
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
WITH CLEAR (5V TOLERANT INPUTS)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVX273M 74LVX273MTR
TSSOP 74LVX273TTR
TSSOPSOP