1/9July 2001
■ HIGH SPEED :
t
PD
= 6.0ns (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ INPUT VOLTAGE LEVEL :
V
IL
=0.8V , VIH=2V at VCC=3V
■ LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at TA=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at VCC = 3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOL TAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
■ IMPROVED LATCH-UP IMMUNITY
■ POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX139 is a low voltage CMOS DUAL 2
TO 4 DECODER/DEMULTIPLEXER fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
The active low enable input can be used for gating
or as a data input for demultiplexing applications.
While the enable input is held high, all four outputs
are high independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX139
LOW VOLTAGE CMOS
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVX139M 74LVX139MTR
TSSOP 74LVX139TTR
TSSOPSOP
74LVX139
2/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
X : Don’t Care
n: 1, 2.
LOGIC DIAGRAM
PIN No SYMBOL NAME AND FUNCTION
1, 15 1G
, 2G Enable Inputs
2, 3 1A, 1B Address Inputs
4, 5, 6, 7 1Y0
to 1Y3 Outputs
12, 11, 10, 9 2Y0
to 2Y3 Outputs
14, 13 2A, 2B Address Inputs
8 GND Ground (0V)
16 V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
ENABLE SELECT
nG
nB nA nY0 nY1 nY2 nY3
HXXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
LHHHHHL
74LVX139
3/9
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) Truth T abl e guarante ed: 1.2V to 3.6 V
2) V
IN
from 0.8V to 2.0V
DC SPECIFICATIONS
Symbol Parameter Value Unit
V
CC
Supply Voltage
-0.5 to +7.0 V
V
I
DC Input Voltage
-0.5 to +7.0 V
V
O
DC Output Voltage -0.5 to VCC + 0.5
V
I
IK
DC Input Diode Current
- 20 mA
I
OK
DC Output Diode Current
± 20 mA
I
O
DC Output Current
± 25 mA
I
CC
or I
GND
DC VCC or Ground Current
± 50 mA
T
stg
Storage Temperature
-65 to +150 °C
T
L
Lead Temperature (10 sec)
300 °C
Symbol Parameter Value Unit
V
CC
Supply Voltage (note 1)
2 to 3.6 V
V
I
Input Voltage
0 to 5.5 V
V
O
Output Voltage 0 to V
CC
V
T
op
Operating Temperature
-55 to 125 °C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3.3V)
0 to 100 ns/V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
IH
High Level Input
Voltage
2.0 1.5 1.5 1.5
V3.0 2.0 2.0 2.0
3.6 2.4 2.4 2.4
V
IL
Low Level Input
Voltage
2.0 0.5 0.5 0.5
V3.0 0.8 0.8 0.8
3.6 0.8 0.8 0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50 µA
1.9 2.0 1.9 1.9
V3.0
I
O
=-50 µA
2.9 3.0 2.9 2.9
3.0
I
O
=-4 mA
2.58 2.48 2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50 µA
0.0 0.1 0.1 0.1
V3.0
I
O
=50 µA
0.0 0.1 0.1 0.1
3.0
I
O
=4 mA
0.36 0.44 0.55
I
I
Input Leakage
Current
3.6
V
I
= 5.5V or GND
± 0.1 ± 1 ± 1 µA
I
CC
Quiescent Supply
Current
3.6
V
I
= VCC or GND
22020µA
74LVX139
4/9
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst c ase package .
2) Max number of outp ut s defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HI GH or LOW
2) Param eter guaran teed by design
(*) Vol tage range is 3.3V ±
0.3V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3 0.5
V
V
OLV
-0.5 -0.3
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3 2
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3 0.8
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
t
PLH tPHL
Propagation Delay
Time
A, B to Y
2.7 15 7.5 12.0 14.0 16.0
ns
2.7 50 9.4 15.0 17.0 19.0
3.3
(*)
15 6.0 8.5 10.0 11.5
3.3
(*)
50 7.6 11.0 12.5 14.5
t
PLH tPHL
Propagation Delay
Time
G
to Y
2.7 15 7.3 12.0 14.0 16.0
ns
2.7 50 9.2 15.0 17.0 19.0
3.3
(*)
15 5.8 8.5 10.0 11.5
3.3
(*)
50 7.2 11.0 12.5 14.5
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
2.7 50 0.5 1.0 1.5 1.5
ns
3.3
(*)
50
0.5 1.0 1.5 1.5
74LVX139
5/9
CAPACITIVE CHARACTERISTICS
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I
CC(opr)
= CPD x VCC x fIN + ICC/2 (per
Decoder)
TEST CIRCUIT
CL =15/50pF or equivalent (i ncludes jig and probe cap acitance)
R
T
= Z
OUT
of pulse generator (typically 50Ω)
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
C
IN
Input Capacitance
3.3 5 pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.3
f
IN
= 10MHz
13 pF
74LVX139
6/9
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
74LVX139
7/9
DIM.
mm. inch
MIN. TYP MAX. MIN. TYP. M AX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S8° (max.)
SO-16 MECHANICAL DATA
PO13H
74LVX139
8/9
DIM.
mm. inch
MIN. TYP MAX. MIN. TYP. M AX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.9 5 5.1 0.193 0.197 0.201
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
TSSOP16 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
0080338D
74LVX139
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by implication or otherwise unde r any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
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