SGS Thomson Microelectronics 74LVQ74MTR, 74LVQ74M, 74LVQ74TTR Datasheet
1/11July 2001
■ HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at VCC = 3.3V
■ COMPA TIBLE WITH TTL OU TP U TS
■ LOW POWER DISSIPATION:
I
CC
=2 µA (MAX.) at TA=25°C
■ LOW NOISE:
V
OLP
= 0.2 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = IOL = 12mA (MIN) at VCC = 3.0V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ74M 74LVQ74MTR
TSSOP 74LVQ74TTR
TSSOPSOP
74LVQ74
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
X : Don ’t Care
LOGIC DIAGRAM
This logic di agram has not be used to estimat e propagation delays
PIN No SYMBOL NAME AND FUNCTION
1, 13 1CLR
, 2CLR
Asynchronous Reset -
Direct Input
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input (LOW to
HIGH, Edge Triggered)
4, 10 1PR
, 2PR Asynchronous Set - Direct
Input
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q
, 2Q Complement Flip-Flop
Outputs
7 GND Ground (0V)
14 V
CC
Positive Supply Voltage
INPUTS OUTPUTS
FUNCTION
CLR
PR DCKQ Q
L H X X L H CLEAR
H L X X H L PRESET
LLXXHH
HHL LH
HHH HL
HHX
Q
n
Q
n
NO CHANGE
74LVQ74
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth T abl e guarante ed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
DC SPECIFICATIONS
1) Maxim um test duration 2ms, one output loaded at time
2) Incid ent wave swi tc hi ng is guara nt eed on transmi ssion line s wi t h i mpedance s as low as 75Ω
Symbol Parameter Value Unit
V
CC
Supply Voltage
-0.5 to +7 V
V
I
DC Input Voltage -0.5 to VCC + 0.5
V
V
O
DC Output Voltage -0.5 to VCC + 0.5
V
I
IK
DC Input Diode Current
± 20 mA
I
OK
DC Output Diode Current
± 20 mA
I
O
DC Output Current
± 50 mA
I
CC
or I
GND
DC VCC or Ground Current
± 400 mA
T
stg
Storage Temperature
-65 to +150 °C
T
L
Lead Temperature (10 sec)
300 °C
Symbol Parameter Value Unit
V
CC
Supply Voltage (note 1)
2 to 3.6 V
V
I
Input Voltage 0 to V
CC
V
V
O
Output Voltage 0 to V
CC
V
T
op
Operating Temperature
-55 to 125 °C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10 ns/V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
IH
High Level Input
Voltage
3.0 to
3.6
2.0 2.0 2.0 V
V
IL
Low Level Input
Voltage
0.8 0.8 0.8 V
V
OH
High Level Output
Voltage
3.0
I
O
=-50 µA
2.9 2.99 2.9 2.9
V
I
O
=-12 mA
2.58 2.48 2.48
I
O
=-24 mA
2.2 2.2
V
OL
Low Level Output
Voltage
3.0
IO=50 µA
0.002 0.1 0.1 0.1
V
I
O
=12 mA
0 0.36 0.44 0.44
I
O
=24 mA
0.55 0.55
I
I
Input Leakage
Current
3.6
V
I
= VCC or GND
± 0.1 ± 1 ± 1 µA
I
CC
Quiescent Supply
Current
3.6
V
I
= VCC or GND
22020µA
I
OLD
Dynamic Output
Current (note 1, 2)
3.6
V
OLD
= 0.8 V max
36 25 mA
I
OHD
V
OHD
= 2 V min
-25 -25 mA
74LVQ74
4/11
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst c ase package.
2) Max number of outputs defined as (n). Data inp ut s are driven 0V to 3 .3V, (n-1) out puts switching and one out put at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Param eter guaran teed by design
(*) Vol tage range is 3.3V ±
0.3V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.2 0.8
V
V
OLV
-0.8 -0.2
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3 2 V
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3 0.8 V
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
2.7 7.7 12.0 14.0 16.0
ns
3.3
(*)
6.3 9.0 10.5 12.0
t
PLH
t
PHL
Propagation Delay
Time PR
or CLR to
Q
2.7 6.9 12.0 14.0 16.0
ns
3.3
(*)
5.8 9.0 10.5 12.0
t
w
Pulse Width CK ,
HIGH or LOW
2.7 4.0 1.5 4.0 5.0
ns
3.3
(*)
3.0 1.5 3.0 4.0
t
w(L)
Pulse Width PR or
CLR
, LOW
2.7 4.0 1.5 4.0 5.0
ns
3.3
(*)
3.0 1.5 3.0 4.0
t
s
Setup Time D to CK
HIGH or LOW
2.7 4.0 -0.2 4.0 5.0
ns
3.3
(*)
3.0 -0.2 3.0 4.0
t
h
Hold Time D to CK
HIGH or LOW
2.7 2.0 0.2 2.0 2.0
ns
3.3
(*)
2.0 0.2 2.0 2.0
t
REM
Recovery Time PR
or CLR
to Q
2.7 1.0 -1.0 1.0 1.0
ns
3.3
(*)
1.0 -1.0 1.0 1.0
f
MAX
Maximum Clock
Frequency
2.7 100 200 100 80
MHz
3.3
(*)
120 250 120 100
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
2.7 0.2 1.0 1.0 1.0
ns
3.3
(*)
0.2 1.0 1.0 1.0
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