SGS Thomson Microelectronics 74LVQ373 Datasheet

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74LVQ373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTSNON INVERTING

■ HIGHSPEED:t

■

COMPATIBLEWITHTTLOUTPUTS

■ LOW POWERDISSIPATION:

I

=4µA (MAX.)at TA=25oC

CC

■ LOWNOISE:V

■ 75Ω TRANSMISSIONLINEOUTPUTDRIVE

=6 ns(TYP.)atVCC=3.3V

PD

= 0.4V(TYP.)atVCC=3.3V

OLP

CAPABILITY

■ SYMMETRICALOUTPUTIMPEDANCE:

|I

|=IOL=12mA(MIN)

OH

■ PCIBUSLEVELSGUARANTEEDAT 24mA

■ BALANCEDPROPAGAT IONDELAYS:

≅

t

t

PLH

PHL

■ OPERATINGVOLTAGERANGE:

V

(OPR)= 2Vto3.6V (1.2VData Retention)

CC

■ PINANDFUNCTION COMPATIBLEWITH

74SERIES373

■

IMPROVEDLATCH-UP IMMUNITY

DESCRIPTION

The LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C

2

MOS

technology.Itis ideal for low power and low noise

3.3Vapplications.
These 8 bit D-Type latchs are controlled by a

latch enable input (LE) and an output enable

M

(Micro Package)

(TSSOPPackage)

T

ORDERCODES :

74LVQ373M 74LVQ373T

input (OE).
While the LE input is held at a high level, the Q

outputswill follow the data input precisely.
When the LE is taken low, the Q outputs will be

latchedpreciselyat thelogic level of D input data.
While the (OE) input is low, the 8 outputs will be

in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.

It has better speed performanceat 3.3V than 5V
LS-TTL family combined with the true CMOS low
powerconsuption.

All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGICSYMBOLS

February 1999

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74LVQ373

INPUT AND OUTPUTEQUIVALENT CIRCUIT PIN DESCRIPTION

PI N No SYMB OL NAME AND F U NCTION

1 OE 3 State Output Enable

2, 5, 6, 9,

12, 15, 17,

18

3, 4, 7, 8,

13, 14, 17,

18
11 LE Latch Enable

10 GND Ground (0V)
20 V

TRUTH TABLE

INPUTS OUTPUTS

OE LE D Q

HXXZ

L L X NO CHANGE *
LHLL
LHHH

X:Don’tcare
Z:Highimpedance
*Q outputarelatchedatthetimewhentheLE input is takenlowlogic level.

D0 to D7 Data Inputs

Q0 to Q7 3 State Outputs

CC

Input (Active LOW)

Input

Positive Supply Voltage

LOGICDIAGRAM

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74LVQ373

ABSOLUTE MAXIMUM RATINGS

Symb o l Parameter Val u e Uni t

V

V

V

I

I

OK

I

or I

I

CC

T

T

AbsoluteMaximumRatingsarethosevaluesbeyond whichdamagetothedevice mayoccur. Functionaloperationunderthesecondition isnotimplied.

RECOMMENDED OPERATINGCONDITIONS

Symb o l Parameter Value Un it

V

V

V

T

t

r,tf

1) TruthTable guaranteed: 1.2Vto 3.6V
from0.8V to 2V

2)V

IN

Supply Voltage -0.5 to +7 V

CC

DC Input Voltage -0.5 to VCC+ 0.5 V

I

DC Output Voltage -0.5 to VCC+ 0.5 V

O

DC Input Diode Current ± 20 mA

IK

DC Output Diode Current ± 20 mA
DC Output Current

O

DC VCCor Ground Current

GND

Storage Temperature -65 to +150

stg

Lead Temperature (10 sec) 300

L

Supply Voltage (note 1) 2 to 3.6 V

CC

Input Voltage 0 to V

I

Output Voltage 0 to V

O

Operating Temperature: -40 to +85

op

50 mA

±

400 mA

±

CC
CC

Input Rise and Fall Time (VCC= 3V) (note 2) 0 to 10 ns/V

o

C

o

C

V
V

o

C

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