SGS Thomson Microelectronics 74LVQ163TTR, 74LVQ163MTR, 74LVQ163M Datasheet
74LVQ163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
■ HIGH SPEED:
f
= 180 MHz (TYP.) at VCC = 3.3 V
MAX
■ COMPA TIBLE WITH TTL OU TP U TS
■ LOW POWER DISSIPATION:
I
= 4 µA (MAX.) at TA=25°C
CC
■ LOW NOISE:
V
= 0.3V (TYP.) at VCC = 3.3V
OLP
■ 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 12mA (MIN) at VCC = 3.0 V
OH
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
≅ t
t
PLH
■ OPERATING VOLTAGE RANGE:
V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
PHL
(OPR) = 2V to 3.6V (1.2V Data Retention)
74 SERIES 163
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ163 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
TSSOPSOP
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ163M 74LVQ163MTR
TSSOP 74LVQ163TTR
control inputs, Master Reset (CLEAR
Enable Input (LOAD
), Count Enable Input (PE)
), Parallel
and Count Enable Carry Input (TE), determine the
mode of operation as shown in t he T ruth Table . A
LOW signal on CLEAR
overrides counting and
parallel loading and allows all output s to go LOW
on the next rising edge of CLOCK . A LOW signal
on LOAD
overrides counting and allows
information on Parallel Data Qn inputs to be
loaded into the flip-flops on the next rising edge of
CLOCK. With LOAD
and CLEAR, PE and TE
permit counting when both are high. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/13July 2001
74LVQ163
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 CLEAR
2 CLOCK Clock Input (Positive Edge
3, 4, 5, 6 A, B, C, D Data Inputs
7 PE Count Enable Input
10 TE Count Enable Carry Input
9LOAD
14, 13, 12, 11QA to QD Flip-Flop Outputs
15 CARRY OUT Terminal Count Output
8 GND Ground (0V)
16 V
TRUTH TABLE
CC
Synchronous Master
Reset
Trigger)
Parallel Enable Input
Positive Supply Voltage
INPUTS OUTPUTS
CLEAR
L X X X L L L L RESET TO "0"
H L X X A B C D PRESET DATA
H H X L NO CHANGE NO COUNT
H H L X NO CHANGE NO COUNT
HHHH COUNT UP COUNT
H X X X NO CHANGE NO COUNT
X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOAD PE TE CK
FUNCTION
2/13
LOGIC DIAGRAM
74LVQ163
3/13
74LVQ163
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
4/13
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7 V
V
V
± 20 mA
± 20 mA
± 50 mA
± 300 mA
-65 to +150 °C
300 °C
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