1/8July 2001
■ HIGH SPEED:
t
PD
= 5.5ns (TYP.) at VCC = 3.3 V
■ COMPATIBLE WI TH TTL OUTPUTS
■ LOW POWER DISSIPATION:
I
CC
= 2µA (MAX.) at TA=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = IOL = 12mA (MIN) at VCC = 3.0V
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOL TAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00
■ IMPROVE D L AT CH-UP IMMUN IT Y
DESCRIPTION
The 74LVQ00 is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output , which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ00
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVQ00M 74LVQ00MTR
TSSOP 74LVQ00TTR
TSSOPSOP
74LVQ00
2/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth T abl e guarante ed: 1.2V to 3.6 V
2) V
IN
from 0.8V to 2V
PIN No SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A to 4A Data Inputs
2, 5, 10, 13 1B to 4B Data Inputs
3, 6, 8, 11 1Y to 4Y Data Outputs
7 GND Ground (0V)
14
V
CC
Positive Supply Voltage
ABY
LLH
LHH
HLH
HHL
Symbol Parameter Value Unit
V
CC
Supply Voltage
-0.5 to +7 V
V
I
DC Input Voltage -0.5 to VCC + 0.5
V
V
O
DC Output Voltage -0.5 to VCC + 0.5
V
I
IK
DC Input Diode Current
± 20 mA
I
OK
DC Output Diode Current
± 20 mA
I
O
DC Output Current
± 50 mA
I
CC
or I
GND
DC VCC or Ground Current
± 200 mA
T
stg
Storage Temperature
-65 to +150 °C
T
L
Lead Temperature (10 sec)
300 °C
Symbol Parameter Value Unit
V
CC
Supply Voltage (note 1)
2 to 3.6 V
V
I
Input Voltage 0 to V
CC
V
V
O
Output Voltage 0 to V
CC
V
T
op
Operating Temperature
-55 to 125 °C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10 ns/V
74LVQ00
3/8
DC SPECIFICATIONS
1) Maxim um test duration 2ms, one out put loaded at time
2) Incid ent wave sw i tc hi ng is guara nt eed on transmi ssion lines with impedances a s low as 75Ω
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst c ase package .
2) Max number of outp ut s defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
IH
High Level Input
Voltage
3.0 to
3.6
2.0 2.0 2.0 V
V
IL
Low Level Input
Voltage
0.8 0.8 0.8 V
V
OH
High Level Output
Voltage
3.0
IO=-50 µA
2.9 2.99 2.9 2.9
V
I
O
=-12 mA
2.58 2.48 2.48
I
O
=-24 mA
2.2 2.2
V
OL
Low Level Output
Voltage
3.0
I
O
=50 µA
0.002 0.1 0.1 0.1
V
I
O
=12 mA
0 0.36 0.44 0.44
I
O
=24 mA
0.55 0.55
I
I
Input Leakage
Current
3.6
V
I
= VCC or GND
± 0.1 ± 1 ± 1 µA
I
CC
Quiescent Supply
Current
3.6
V
I
= VCC or GND
22020µA
I
OLD
Dynamic Output
Current (note 1, 2)
3.6
V
OLD
= 0.8 V max
36 25 mA
I
OHD
V
OHD
= 2 V min
-25 -25 mA
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3 0.8
V
V
OLV
-0.8 -0.3
V
IHD
Dynamic High
Voltage Input (note
1, 3)
3.3 2 V
V
ILD
Dynamic Low
Voltage Input (note
1, 3)
3.3 0.8 V