1/9February 2002
■ 5V TOLERANT INPUTS
■ HIGH SPEED: t
PD
= 4.2ns (MAX.) at VCC = 3V
■ POWER DOWN PROTECTION ON INPU T S
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = IOL = 24mA (MIN) at VCC = 3V
■ PCI BUS LEVELS GUARANT EED AT 2 4 mA
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 541
■ LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
■ ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC541A is a lo w voltage CMOS OCTAL
BUS BUFFER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology. It is ideal fo r 1.6 5 to 3. 6
V
CC
operations and low power and low noise
applications.
The 3 STATE control gate opera tes as two input
AND such that if either G1
or G2 are high, all eight
outputs are in the high impedance state.
In order to enhance PC board layout, the
74LVC541A offers a pinout having inputs and
outputs on opposite sides of the package.
This device is designed to interface di rectly High
Speed CMOS systems with TTL and NMOS
components.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVC541A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74LVC541AM 74LVC541AMTR
TSSOP 74LVC541ATTR
TSSOPSOP
PRELIMINARY DATA