SGS Thomson Microelectronics 74LCX573TTR, 74LCX573M Datasheet

1/10September 2001

■ 5V TOLERANT INPUTS AND OUTPUTS

■ HIGH SPEED :

t

PD

= 8.0 ns (MAX.) at VCC = 3V

■ POWER DOWN PROTECTION ON INPUT S

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

OH

| = IOL = 24mA (MIN) at VCC = 3V

■ PCI BUS LEVELS GUARANT EED AT 2 4 mA

■ BALANCED PROPAGATION DELAYS:

t

PLH

≅ t

PHL

■ OPERATING VOLTAGE RANGE:

V

CC

(OPR) = 2.0V to 3.6V (1.5V Data

Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

DESCRIPTION

The 74LCX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C

2

MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE

).
While the LE inputs is held at a high level, t he Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data. While the (OE

) input i s lo w,
the 8 outputs will be in a normal logic state (high or
low logic level) and while (OE

) is in hig h le ve l, t h e
outputs will be in a high impedance state.
It has same speed performance at 3. 3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.

74LCX573

OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE TUBE T & R

SOP 74LCX573M 74LCX573MTR

TSSOP 74LCX573TTR

TSSOPSOP

74LCX573

2/10

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION TRUTH TABLE

X : Don’t Care
Z : High Impedance
* : Q Outputs are latched at the time when th e LE input is taken

LOW.

LOGIC DIAGRAM

This log i c diagram has not be used to esti m ate propaga tion delays

PIN No SYMBOL NAME AND FUNCTION

1OE

3 State Output Enable
Input (Active LOW)

2, 3, 4, 5, 6,

7, 8, 9

D0 to D7 Data Inputs

12, 13, 14,
15, 16, 17,

18, 19

Q0 to Q7 3-State Latch Outputs

11 LE Latch Enable Input
10 GND Ground (0V)
20 V

CC

Positive Supply Voltage

INPUT OUTPUT

OE

LE D Q

HXX Z

L L X NO CHANGE*
LHL L
LHH H

74LCX573

3/10

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

1) I

O

absolute ma xim um rating mu st be observed

2) V

O

< GND

RECOMMENDED OPERATING CONDITIONS

1) Truth T abl e guaranteed: 1.5V to 3.6V

2) V

IN

from 0.8V to 2V at VCC = 3.0V

Symbol Parameter Value Unit

V

CC

Supply Voltage

-0.5 to +7.0 V

V

I

DC Input Voltage

-0.5 to +7.0 V

V

O

DC Output Voltage (OFF State)

-0.5 to +7.0 V

V

O

DC Output Voltage (High or Low State) (note 1) -0.5 to VCC + 0.5

V

I

IK

DC Input Diode Current

- 50 mA

I

OK

DC Output Diode Current (note 2)

- 50 mA

I

O

DC Output Current

± 50 mA

I

CC

DC Supply Current per Supply Pin

± 100 mA

I

GND

DC Ground Current per Supply Pin

± 100 mA

T

stg

Storage Temperature

-65 to +150 °C

T

L

Lead Temperature (10 sec)

300 °C

Symbol Parameter Value Unit

V

CC

Supply Voltage (note 1)

2.0 to 3.6 V

V

I

Input Voltage

0 to 5.5 V

V

O

Output Voltage (OFF State)

0 to 5.5 V

V

O

Output Voltage (High or Low State) 0 to V

CC

V

I

OH

, I

OL

High or Low Level Output Current (VCC = 3.0 to 3.6V)

± 24 mA

I

OH

, I

OL

High or Low Level Output Current (VCC = 2.7V)

± 12 mA

T

op

Operating Temperature

-55 to 125 °C

dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V