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OCTAL D-TYPE FLIP FLOP WITH CLEAR
■ HIGHSPEED:
=190MHzns(TYP.)atVCC=5V
f
MAX
■ LOW POWER DISSIPATION:
I
=8µA (MAX.)at TA=25oC
CC
■ COMPATIBLEWITHTTLOUTPUTS
V
=2V(MIN),VIL=0.8V(MAX)
IH
■
50ΩTRANSMISSIONLINEDRIVING
CAPABILITY
■ SYMMETRICALOUTPUTIMPEDANCE:
|I
|=IOL=24mA(MIN)
OH
■ BALANCEDPROPAGATIONDELAYS:
≅
t
t
PLH
PHL
■ OPERATINGVOLTAGERANGE:
V
(OPR)= 4.5Vto 5.5V
CC
■ PINANDFUNCTION COMPATIBLEWITH
74SERIES273
■
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The ACT273 is a high-speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
2
MOS technology.It is ideal for low
74ACT273
PRELIMINARY DATA
M
B
(PlasticPackage)
ORDER CODES :
74ACT273B
74ACT273M
74ACT273T
Information signals applied to D inputs are
transfered to the Q output on the positive going
edgeof theclock pulse.
Whenthe CLEAR input is held low, the Q outputs
are held low independentelyof the otherinputs .
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOSoutput voltagelevels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
(Micro Package)
T
(TSSOPPackage)
PIN CONNECTION AND IEC LOGICSYMBOLS
May 1999
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74ACT273
INPUT AND OUTPUTEQUIVALENTCIRCUIT
TRUTH TABLE
INPUTS OUTPUTS FUNCTION
CLE AR D CLOCK Q
L X X L CLEAR
HL L
HH H
HX Q
X:Don’tCare
PIN DESCRIPTION
PI N No SYM BO L NAM E AND F U NCTIO N
1 CLEAR Asyncronous Master
Reset (Active LOW)
2,5,6,9,12,
15, 16,19
3,4,7,8,13,
14, 17,18
11 CLOCK Clock Input
10 GND Ground (0V)
20 V
n
Q0toQ7 Flip-Flop Outpus
D0toD7 Data Inputs
(LOW-to-HIGH, EdgeTriggered)
Positive Supply Voltage
CC
NOCHANGE
LOGICDIAGRAMS
Thislogic diagram has notbeused to esimate propagation delays
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74ACT273
ABSOLUTE MAXIMUM RATINGS
Symb o l Para met er Val u e Uni t
V
V
V
I
I
OK
I
orI
I
CC
T
T
AbsoluteMaximumRatingsarethosevaluesbeyond whichdamagetothedevicemayoccur. Functionaloperationundertheseconditionisnotimplied.
RECOMMENDED OPERATINGCONDITIONS
Symb o l Parameter Val u e Uni t
V
V
V
T
dt/dv Input Rise and Fall Time V
1)VINfrom0.8Vto 2.0V
Supply Voltage -0.5to+7 V
CC
DC Input Voltage -0.5toVCC+0.5 V
I
DC Output Voltage -0.5toVCC+0.5 V
O
DC Input Diode Current ±20 mA
IK
DC Output Diode Current ±20 mA
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature -65to+150
stg
Lead Temperature (10 sec) 300
L
Supply Voltage 4.5to5.5 V
CC
Input Voltage 0toV
I
Output Voltage 0toV
O
Operating Temperature: -40to+85
op
= 4.5 to 5.5V (note 1) 8 ns/V
CC
50 mA
±
400 mA
±
CC
CC
o
C
o
C
V
V
o
C
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74ACT273
DC SPECIFICATIONS
Symbol Parameter Test Conditi ons Value Un it
T
V
CC
(V)
High Level Input Voltage 4.5 VO=0.1Vor
V
IH
5.5 2.0 1.5 2.0
Low Level Input Voltage 4.5 VO=0.1Vor
V
IL
5.5 1.5 0.8 0.8
High Level Output
V
OH
Voltage
4.5
5.5 I
V
V
4.5 I
5.5 I
Low Level Output
V
OL
Voltage
4.5
5.5 I
V
V
4.5 I
5.5 I
Input Leakage Current 5.5 VI=VCCorGND ±0.1 ±1 µA
I
I
Max ICC/Input 5.5 VI=VCC-2.1V 0.6 1.5 mA
I
CCT
Quiescent Supply
I
CC
5.5 VI=VCCorGND 4 40
-0.1V
V
CC
V
-0.1V
CC
IO=-50µA 4.4 4.49 4.4
(*)
=
I
or
IH
V
IL
(*)
I
or
IH
V
IL
=-50µA 5.4 5.49 5.4
O
=-24 mA 3.86 3.76
O
=-24 mA 4.86 4.76
O
IO=50µA 0.001 0.1 0.1
=
=50mA 0.001 0.1 0.1
O
=24mA 0.36 0.44
O
=24mA 0.36 0.44
O
Current
Dynamic Output Current
I
OLD
(note 1, 2)
I
OHD
1) Maximumtest duration 2ms, one output loaded at time
2)Incidentwaveswitchingis guaranteedontransmissionlineswithimpedances aslowas50Ω.
5.5 V
=1.65V max 75 mA
OLD
V
=3.85Vmin -75 mA
OHD
=25oC -40 to 85oC
A
Min. Typ. Max. Min. Max.
2.0 1.5 2.0
1.5 0.8 0.8
µ
V
V
V
V
A
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