SGS Thomson Microelectronics 74ACT16373TTR Datasheet
74ACT16373
16-BIT D-TYPE L ATCH
WITH 3-STATE OUTPUTS (NON INVERTED)
■ HIGH SPEED:t
■ LOW POWER DISSIPATION:
I
=8µA(MAX.) at TA=25°C
CC
■ COMPATIBLE WITH TTL OUTPUTS
V
=2V(MIN.),VIL= 0 .8V (MAX.)
IH
■ 50ΩTRANSMISSION LINE DRIVING
= 5.3ns (TYP.) at VCC=5V
PD
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL= 24mA (MIN)
OH
■ OPERATING VOLTAGE RANGE:
V
(OPR) = 4.5V to 5.5V
CC
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT16373 is an advanced high-speed
CMOS 16-BIT D-TYPE LATCH (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS tecnology.
This 16 bit D-Type latch is controlled by two lat c h
enable inputs (LE) and two output enable inputs
(OE
). The dev ice can be used as two 8-bit latches
or one 16-bit latch.
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. W hen
the LE is taken low, the Q outputs will be latched
precisely at the levels set up at the D inputs. While
the (OE
) input is low, the outputs will be in a
normal logic state (high or low logic level) and
while OE
is in high level the outputs will be in a
high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outpu ts are equipped with
protection circuits against static discharge, giving
them 2KV ESD im munity and transient excess
voltage.
TSSOP
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74ACT16373TTR
PIN CONNECTION
1/10February 2003
74ACT16373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 1OE
2, 3,5, 6,8,9,
11, 12
13,14,16,17,
19, 20, 22, 23
24 2OE
25 2LE Latch Enable Input
36,35,33,32,
30, 29, 27, 26
47,46,44,43,
41, 40, 38, 37
48 1LE Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
1Q0 to 1Q7 3-State Outputs
2Q0 to 2Q7 3-State Outputs
2D0 to 2D7 Data Inputs
1D0 to 1D7 Data Inputs
GND Ground (0V)
CC
3 State Output Enable
Input (Active LOW)
3 State Output Enable
Input (Active LOW)
Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUT
OE
HXX Z
L L X NO CHANGE *
LHL L
LHH H
X : Don‘tCare
Z : High Impedance
* : Q outputs are latched atthetimewhenthe LEinputistakenlow
logic level.
LE D Q
IEC LOGIC SYMBOLS
2/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
74ACT16373
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage -0.5 to VCC+ 0.5
I
DC Output Voltage -0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7 V
V
V
± 20 mA
± 20 mA
± 50 mA
± 400 mA
-65 to +150 °C
300 °C
3/10
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