SGS Thomson Microelectronics 74ACT163 Datasheet
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
■ HIGHSPEED:
=200MHz(TYP.)at VCC=5V
f
MAX
■ LOW POWER DISSIPATION:
=4 µA (MAX.) at TA=25oC
I
CC
■ COMPATIBLEWITHTTLOUTPUTS
=2V(MIN),VIL=0.8V(MAX)
V
IH
■ 50Ω TRANSMISSIONLINEDRIVING
CAPABILITY
■ SYMMETRICALOUTPUTIMPEDANCE:
|=IOL=24mA(MIN)
|I
OH
■ BALANCEDPROPAGATIONDELAYS:
≅ t
t
PLH
PHL
■ OPERATINGVOLTAGERANGE:
(OPR)= 4.5Vto 5.5V
V
CC
■ PINANDFUNCTIONCOMPATIBLEWITH
74SERIES163
■ IMPROVEDLATCH-UPIMMUNITY
DESCRIPTION
The ACT163 is a high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layermetal wiring C
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL. It is a 4 bit binary counter with
SynchronousClear.
The circuits have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
2
MOS technology.It is
74ACT163
B
(PlasticPackage)
(Micro Package)
ORDERCODES :
74ACT163B 74ACT163M
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine
the mode of operation as shown in the Truth
Table. A LOW signal on CLEAR overrides
counting and parallel loading and allows all
output to go LOW on the next rising edge of
CLOCK. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
Qn inputs to be loaded into the flip-flops on the
next rising edge of CLOCK. With LOAD and
CLEAR, PE and TE permit counting when both
are HIGH. Conversely, a LOW signal on either
PE and TE inhibitscounting.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOSoutput voltagelevels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
M
PIN CONNECTION AND IECLOGIC SYMBOLS
December 1998
1/11
74ACT163
INPUT AND OUTPUTEQUIVALENTCIRCUIT
PIN DESCRIPTION
PI N No SYM BO L NAM E AND FU NCTION
1 CLEAR MasterReset
2 CLOCK ClockInput(LOW-to-HIGH,
Edge-Triggered)
3, 4, 5, 6 A, B, C, D Data Inputs
7 ENABLE P CountEnable Input
10 ENABLE T Count EnableCarry Input
9 LOAD Parallel EnableInput
14, 13,12,11QA to QD Flip-FlopOutpus
10 ENABLE T Count EnableCarry Input
8 GND Ground(0V)
16 V
CC
PositiveSupply Voltage
TRUTH TABLE
INPUTS OUTPUTS FUNCTION
CLRLDPE TECKQAQBQCQD
LXXX LLLL RESET TO ”0”
H L X X A B C D PRESET DATA
H H X L NO CHANGE NO COUNT
H H L X NO CHANGE NO COUNT
H H H H COUNT UP COUNT
X X X X NO CHANGE NO COUNT
NOTE: X:Don’tCare
A,B, C,D: Logiclevelofdatainput
CARRY=TE • QA• QB• QC • QD
LOGICDIAGRAMS
2/11
TIMINGCHART
74ACT163
3/11
74ACT163
ABSOLUTE MAXIMUM RATINGS
Symb o l Para met er Val u e Uni t
V
V
V
I
I
OK
I
or I
I
CC
T
T
AbsoluteMaximumRatingsarethosevaluesbeyond whichdamage tothedevice mayoccur.Functionaloperation underthesecondition isnotimplied.
RECOMMENDEDOPERATINGCONDITIONS
Symb o l Param eter Val u e Uni t
V
V
V
T
dt/dv InputRiseand FallTime V
1)VINfrom0.8V to2.0V
SupplyVoltage -0.5 to +7 V
CC
DC InputVoltage -0.5 to VCC+ 0.5 V
I
DC OutputVoltage -0.5 to VCC+ 0.5 V
O
DC InputDiode Current ± 20 mA
IK
DC OutputDiode Current ± 20 mA
DC OutputCurrent
O
DC VCCorGround Current
GND
Storage Temperature -65 to +150
stg
LeadTemperature (10 sec) 300
L
SupplyVoltage 4.5 to5.5 V
CC
InputVoltage 0 to V
I
OutputVoltage 0 to V
O
OperatingTemperature: -40 to +85
op
=4.5to5.5V(note1) 8 ns/V
CC
50 mA
±
300 mA
±
CC
CC
o
C
o
C
V
V
o
C
DC SPECIFICATIONS
Symbol Parameter Test Conditions Value Unit
=25oC -40 to 85oC
V
CC
(V)
HighLevelInputVoltage 4.5 VO= 0.1V or
V
IH
5.5 2.0 1.5 2.0
LowLevel InputVoltage 4.5 VO= 0.1V or
V
IL
5.5 1.5 0.8 0.8
HighLevelOutputVoltage 4.5
V
OH
5.5 I
4.5 I
5.5 I
LowLevel OutputVoltage 4.5
V
OL
5.5 I
4.5 I
5.5 I
InputLeakage Current 5.5 VI=VCCor GND ±0.1 ±1 µA
I
I
MaxICC/Input 5.5 VI=VCC-2.1V 0.6 1.5 mA
I
CCT
Quiescent SupplyCurrent 5.5 VI=VCCor GND 4 40
I
CC
Dynamic OutputCurrent
I
OLD
OHD
(note 1, 2)
I
1) Maximum test duration 2ms,oneoutput loaded attime
2)Incident waveswitchingisguaranteed ontransmissionlines withimpedancesaslowas 50 Ω.
(*)Alloutputs loaded.
5.5 V
V
-0.1 V
CC
V
-0.1 V
CC
IO=-50 µA 4.4 4.49 4.4
(*)
=
V
I
V
IH
V
IL
(*)
V
I
V
IH
V
IL
OLD
V
OHD
=-50 µA 5.4 5.49 5.4
O
or
=-24 mA 3.86 3.76
O
=-24 mA 4.86 4.76
O
IO=50µA 0.001 0.1 0.1
=
=50 mA 0.001 0.1 0.1
O
or
=24 mA 0.36 0.44
O
=24 mA 0.36 0.44
O
= 1.65 V max 75 mA
= 3.85 V min -75 mA
T
A
Min. Typ. Max. Min. Max.
2.0 1.5 2.0
1.5 0.8 0.8
µ
V
V
V
V
A
4/11
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