![](/html/f2/f2e0/f2e00c47d0e4c2be01d2cc3885b2568b455147554704fa463c2063b792a59405/bg1.png)
74ACT138
3 TO 8 LINE DECODER (INVERTING)
■ HIGH SPEED: t
■ LOWPOWERDISSIPATION:
=8µA (MAX.)at TA=25oC
I
CC
■ COMPATIBLEWITH TTL OUTPUTS
V
=2V(MIN),VIL= 0.8V (MAX)
IH
■ 50Ω TRANSMISSIONLINE DRIVING
=5 ns (TYP.) atVCC=5V
PD
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=24 mA (MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
PHL
■ OPERATINGVOLTAGERANGE:
V
(OPR)= 4.5V to 5.5V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
74SERIES138
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT138 is an advanced high-speed CMOS 3
TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2Aor G2G is held high, the decodingfunctionis
inhibitedand all the 8 outputs go to high.
B
(Plastic Package)
(Micro Package)
M
ORDERCODES:
74ACT138B
Three enable inputs are provided to ease
cascade connection and application of address
decodersfor memory systems.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
SchottkyTTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOSoutput voltage levels.
All inputs and outputs are equipped with
protectioncircuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PINCONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/8
![](/html/f2/f2e0/f2e00c47d0e4c2be01d2cc3885b2568b455147554704fa463c2063b792a59405/bg2.png)
74ACT138
INPUTAND OUTPUTEQUIVALENTCIRCUIT
PIN DESCRIPTION
PI N No SYM B O L NAME A ND FUNCT I ON
1, 2, 3 A, B, C Address Inputs
4, 5 G2A, G2B Enable Inputs
6 G1 Enable Input
15, 14, 13,
12, 11, 10,
9, 7
8 GND Ground (0V)
16 V
Y0 to Y7 Outputs
CC
Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUTS
ENABLE SELEC T
G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXLXXXHHHHHHHH
XHXXXXHHHHHHHH
HXXXXXHHHHHHHH
LLHLL LLHHHHHHH
LLHLLHHLHHHHHH
LLHLHLHHLHHHHH
LLHLHHHHHLHHHH
LLHHL LHHHHLHHH
LLHHLHHHHHHLHH
LLHHHLHHHHHHLH
LLHHHHHHHHHHHL
X:Don’t Care
LOGICDIAGRAMS
This logic diagram has not be used to estimate propagation delays
2/8
![](/html/f2/f2e0/f2e00c47d0e4c2be01d2cc3885b2568b455147554704fa463c2063b792a59405/bg3.png)
74ACT138
ABSOLUTE MAXIMUMRATINGS
Symb o l Parame t er Val u e Uni t
V
V
V
I
I
OK
I
orI
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATINGCONDITIONS
Symbol Parameter Valu e Unit
V
V
V
T
dt/dv Input Rise and Fall Time V
1) VINfrom0.8V to2.0 V
Supply Voltage -0.5 to +7 V
CC
DC Input Voltage -0.5 to VCC+ 0.5 V
I
DC Output Voltage -0.5 to VCC+ 0.5 V
O
DC Input Diode Current ± 20 mA
IK
DC Output Diode Current ± 20 mA
DC Output Current ± 50 mA
O
DC VCCor Ground Current ± 400 mA
GND
Storage Temperature -65 to +150
stg
Lead Temperature (10 sec) 300
L
Supply Voltage 4.5 to 5.5 V
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature: -40to +85
op
= 4.5 to 5.5V (note 1) 8 ns/V
CC
CC
CC
o
C
o
C
V
V
o
C
3/8