The 74ACT02 is an advanced high-speed CMOS
QUAD 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output , which enables high noise
immunity and stable output.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIP74ACT02B
SOP74ACT02M74ACT02MTR
TSSOP74ACT02TTR
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped w ith protection circuits a gainst static discharge, giving them
2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/8April 2001
74ACT02
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
2, 5, 8, 111A to 4AData Inputs
3, 6, 9, 121B to 4BData Inputs
1, 4, 10, 131Y to 4YData Outputs
7GNDGround (0V)
14
TRUTH TABLE
ABY
LLH
LHL
HLL
HHL
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage-0.5 to VCC + 0.5
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
V
CC
Positive Supply Voltage
-0.5 to +7V
±
20mA
±
20mA
±
50mA
±
200mA
-65 to +150°C
300°C
V
V
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VIN from 0.8V to 2.0V
2/8
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time V
= 4.5 to 5.5V (note 1)
CC
4.5 to 5.5V
CC
CC
-55 to 125°C
8ns/V
V
V
DC SPECIFICATIONS
Test ConditionValue
= 25°C
SymbolParameter
V
CC
(V)
V
V
V
V
I
CCT
I
I
OLD
I
OHD
1) Maxim um test duration 2 m s, one output loaded at time
2) Incid ent wave switc hi ng is guaranteed on transmis sion lines with i m pedances as low as 50Ω
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.0
5.04pF
= 10MHz
f
IN
T
A
Min.Typ. Max.Min. Max. Min.Max.
47pF
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/4 (per gate)
CC(opr)
Unit
3/8
74ACT02
TEST CIRCUIT
CL = 50pF or equivalent (includ es jig and probe capacitance)
R
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