SGS Thomson Microelectronics 74AC74TTR, 74AC74MTR, 74AC74M, 74AC74B Datasheet
74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
■ HIGH SPEED:
f
= 300MHz (TYP.) at VCC = 5V
MAX
■ LOW POWER DISSIPATION:
I
= 2µA(MAX.) at TA=25°C
CC
■ HIGH NOISE IMMUNITY:
V
= V
NIH
■ 50Ω TRANSMISSION LINE DRIVING
= 28 % VCC (MIN.)
NIL
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 24mA (MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
■ OPERATING VOL TAGE RANGE:
V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
PHL
(OPR) = 2V to 6V
74 SERIES 74
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q
OUTPUTS during the positive going
TSSOPDIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP 74AC74B
SOP 74AC74M 74AC74MTR
TSSOP 74AC74TTR
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12April 2001
74AC74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1, 13 1CLR
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input
4, 10 1PR
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q
7 GND Ground (0V)
14 V
TRUTH TABLE
, 2CLR
, 2PR Asynchronous Set - Direct
, 2Q Complement Flip-Flop
CC
Asynchronous Reset Direct Input
(LOW to HIGH, Edge
Triggered)
Input
Outputs
Positive Supply Voltage
INPUTS OUTPUTS
CLR
PR DCKQ Q
L H X X L H CLEAR
H L X X H L PRESET
LLXXHH
HHL LH
HHH HL
HHX
X : Don’t Care
Q
n
Q
n
LOGIC DIAGRAM
FUNCTION
NO CHANGE
This log i c diagram has not be used to est i m at e propagation delays
2/12
74AC74
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
V
T
dt/dv
1) VIN from 30 % to 70% of V
Supply Voltage
CC
DC Input Voltage -0.5 to VCC + 0.5
I
DC Output Voltage -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature
op
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
CC
-0.5 to +7 V
± 20 mA
± 20 mA
± 50 mA
± 200 mA
-65 to +150 °C
300 °C
2 to 6 V
CC
CC
-55 to 125 °C
8 ns/V
V
V
V
V
3/12
74AC74
DC SPECIFICATIONS
Test Condition Value
= 25°C
Symbol Parameter
V
CC
(V)
V
V
V
V
I
I
OLD
I
OHD
1) Maxim um test duration 2ms, one output loaded at time
2) Incid ent wave swi tc hi ng is guara nt eed on transmi ssion line s wi t h i mpedance s as low as 50Ω
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Dynamic Output
Current (note 1, 2)
3.0
5.5 3.85 2.75 3.85 3.85
3.0
5.5 2.75 1.65 1.65 1.65
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
5.5
5.5
= 0.1 V or
V
O
V
-0.1V
CC
= 0.1 V or
V
O
V
-0.1V
CC
=-50 µA
I
O
I
=-50 µA
O
I
=-50 µA
O
I
=-12 mA
O
I
=-24 mA
O
I
=-24 mA
O
IO=50 µA
I
=50 µA
O
I
=50 µA
O
I
=12 mA
O
I
=24 mA
O
I
=24 mA
O
= VCC or GND
V
I
= VCC or GND
V
I
= 1.65 V max
V
OLD
V
= 3.85 V min
OHD
T
A
Min. Typ. Max. Min. Max. Min. Max.
2.1 1.5 2.1 2.1
1.5 0.9 0.9 0.9
2.9 2.99 2.9 2.9
4.4 4.49 4.4 4.4
5.4 5.49 5.4 5.4
2.56 2.46 2.4
3.86 3.76 3.7
4.86 4.76 4.7
0.002 0.1 0.1 0.1
0.001 0.1 0.1 0.1
0.001 0.1 0.1 0.1
0.36 0.44 0.5
0.36 0.44 0.5
0.36 0.44 0.5
± 0.1 ± 1 ± 1 µA
22040µA
-40 to 85°C -55 to 125°C
75 50 mA
-75 -50 mA
Unit
V4.5 3.15 2.25 3.15 3.15
V4.5 2.25 1.35 1.35 1.35
V
V
4/12
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