SGS Thomson Microelectronics 74AC74 Datasheet
74AC74
DUAL D-TYPE FLIP FLOP WITH PRESETAND CLEAR
■ HIGH SPEED:
=300MHz (TYP.) at VCC=5V
f
MAX
■ LOWPOWERDISSIPATION:
=4µA (MAX.) at TA=25oC
I
CC
■ HIGH NOISE IMMUNITY:
V
NIH=VNIL
■ 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL=24mA (MIN)
OH
■ BALANCEDPROPAGATIONDELAY S:
≅ t
t
PLH
■ OPERATINGVOLTAGERAN GE:
V
CC
■ PIN AND FUNCTION COMPATIBLE WITH
74SERIES74
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC74 is an advanced high-speed CMOS
OCTALD-TYPE FLIP FLOP WITH PRESET AND
CLEAR NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
=28%VCC(MIN.)
PHL
(OPR) = 2V to 6V
2
MOS technology.
B
(Plastic Package)
(Micro Package)
M
ORDERCODES:
74AC74B 74AC74M
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriateinput.
It is ideal for low power applications mantaining
high speed operationsimilar to equivalent Bipolar
SchottkyTTL.
All inputs and outputs are equipped with
protectioncircuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PINCONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/11
74AC74
INPUTAND OUTPUTEQUIVALENT CIRCUIT
PIN DESCRIPTION
PI N N o SYM B O L N AM E AND FUNCT I ON
1, 13 1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10 1PR, 2PR Asyncronous Set - Direct
Input
5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q, 2Q Complement Flip-Flop
Outputs
7 GND Ground (0V)
14 V
CC
Positive Supply Voltage
TRUTH TABLE
INP UT S OUT P UTS FUNCT ION
CLRPRDCKQ Q
L H X X L H CLEAR
H L X X H L PRESET
LLXXHH
HHL LH
HHH HL
HHX Q
X:Don’t Care
n
Q
n
NO CHANGE
LOGICDIAGRAMS
This logic diagram has not be used to estimate propagation delays
2/11
74AC74
ABSOLUTE MAXIMUM RATINGS
Symb o l Parame t er Val u e Uni t
V
V
V
I
I
OK
I
orI
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATINGCONDITIONS
Symb o l Parame t er Value Un i t
V
V
V
T
dt/dv Input Rise and Fall Time V
1) VINfrom30%to 70% of V
Supply Voltage -0.5 to +7 V
CC
DC Input Voltage -0.5 to VCC+ 0.5 V
I
DC Output Voltage -0.5 to VCC+ 0.5 V
O
DC Input Diode Current ± 20 mA
IK
DC Output Diode Current ± 20 mA
DC Output Current ± 50 mA
O
DC VCCor Ground Current ± 200 mA
GND
Storage Temperature -65 to +150
stg
Lead Temperature (10 sec) 300
L
Supply Voltage 2 to 6 V
CC
Input Voltage 0 to V
I
Output Voltage 0 to V
O
Operating Temperature: -40 to +85
op
= 3.0, 4.5 or 5.5 V(note 1) 8 ns/V
CC
CC
CC
CC
o
C
o
C
V
V
o
C
3/11
74AC74
DC SPECIFICATIONS
Symbol Parameter Test Condition s Value Unit
V
CC
(V)
High Level Input Voltage 3.0 VO= 0.1 V or
V
IH
4.5 3.15 2.25 3.15
V
CC
- 0.1 V
T
=25oC-40to85
A
Min. Typ. Max. Min . Max.
2.1 1.5 2.1
o
C
5.5 3.85 2.75 3.85
Low Level Input Voltage 3.0 VO= 0.1 V or
V
IL
4.5 2.25 1.35 1.35
V
CC
- 0.1 V
1.5 0.9 0.9
5.5 2.75 1.65 1.65
High Level Output
V
OH
Voltage
Low Level Output
V
OL
Voltage
Input Leakage Current
I
I
Quiescent Supply
I
CC
3.0
4.5 I
5.5 I
V
V
3.0 I
4.5 I
5.5 I
3.0
4.5 I
5.5 I
V
V
3.0 I
4.5 I
5.5 I
5.5
IO=-50 µA 2.9 2.99 2.9
(*)
I
IH
V
IL
=-50 µA 4.4 4.49 4.4
O
=
=-50 µA 5.4 5.49 5.4
or
O
=-12 mA 2.56 2.46
O
=-24 mA 3.86 3.76
O
=-24 mA 4.86 4.76
O
IO=50 µA 0.002 0.1 0.1
(*)
I
IH
V
IL
=50 µA 0.001 0.1 0.1
O
=
=50 µA 0.001 0.1 0.1
or
O
=12 mA 0.36 0.44
O
=24 mA 0.36 0.44
O
=24 mA 0.36 0.44
O
VI=VCCor GND ±0.1 ±1 µA
5.5 VI=VCCor GND 4 40 µA
Current
Dynamic Output Current
I
OLD
OHD
(note 1, 2)
I
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as lowas 50 Ω.
(*)All outputs loaded.
5.5 V
= 1.65 V max 75 mA
OLD
V
= 3.85 V min -75 mA
OHD
V
V
V
V
4/11
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