SGS-THOMSON VIPer31SP Technical data

			VIPer31SP
			BATTERY CHARGER PRIMARY I.C.
			ADVANCE DATA
T YPE	VDSS	In	RDS(on)
VIPer31SP	600 V	1 A	6.5 Ω
			10

FEATURE

■RECTANGULAR CHARACTERISTIC, WITHOUT OPTOCOUPLER

■INTERNALLY TRIMMED CURRENT REFERENCE

■FIXED SWITCHING FREQUENCY, ADJUSTABLE UP TO 150 KHZ

■AUXILIARY VOLTAGE REGULATOR

■SOFT START AND SHUT DOWN CONTROL

■AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET ºBLUE ANGELº NORM (<1W TOTAL POWER CONSUMPTION)

■UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS

■INTEGRATED START UP SUPPLY

■AVALANCHE RUGGED

■OVERVOLTAGE PROTECTION

■OVERTEMPERATURE PROTECTION

■CYCLE BY CYCLE CURRENT LIMITATION

■DEMAGNETISATION CONTROL

BLOCK DIAGRAM

Power SO-10

DESCRIPTION

VIPer31SP combines on the same silicon chip a PWM control dedicated to output current regulation together with an optimised high voltage avalanche rugged vertical power MOSFET (600V/1A). Typical applications cover battery chargers with constant current and constant voltage output characteristics, without any optocoupler between primary and secondary sections. Typical output power capability is 15 W in wide range condition and 30 W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the possibility to operate in no load condition with an input power as low as 1W. This feature insures the compliance towards ºBlue Angelº norm and other similar ones.

	FB		COMP	OSC				DRAIN
VCC
	ON/OFF	-
		-
		+		OSCILLATOR
	2.6 V	+
	UVLO		-	+
	UVLO
	LOGIC
				R1
	+			FF		Q
29 V	-			R2 R3	R4	PWM
29 V	-					LATCH
						LATCH
	OVERTEMP.						+
	DETECTOR					200 ns	+
	DETECTOR					200 ns
						BLANKING	-	1.5 A
							-	1.5 A
	10 V			- +
	10 V
	REGULATOR				CURRENT
					REGULATION
	VDD	GND	CREF	CSENSE		DSENSE		SOURCE
								SC12000

January 1998

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VIPer31SP

ABSOLUTE MAXIMUM RATING

Symb ol

VDS

IDREV

VCC

IDSENSE

Vesd

ID(AV)

ED(AV)

Ptot

Ts tg

Parameter	Value	Uni t
Continuous Drain-Source Voltage (Tj = 25 to 125oC)	600	V
Maximum DC Drain Current	Internally Limited	A
Reverse DC Drain Current	-2.5	A
Supply Voltage	0 to 35	V
Voltage Range Input (CSENSE, COMP, FB, OSC, CREF)	-03 to VDD	V
Current Input (CSENSE, COMP, FB, OSC, CREF	10	mA
Current Range Input (DSENSE)	-10 to +10	mA
Electrostatic Discharge (R = 1.5 KΩ C = 100pF)	2000	V
Avalanche Drain-Source Current, Repetitive or Not-Repetitive	TBD	A
(TC = 100 oC, Pulse Width Limited by TJ max)
Avalanche Drain-Source Energy, Repetitive or Not-Repetitive	TBD	mJ
(TC = 25 oC, Pulse Width Limited by TJ max)
Power Dissipation at TC = 25oC	62	W
Junction Operating Temperature	-40 to 150	oC
Storage Temperature	-65 to 150	oC

THERMAL DATA

Rt hj-ca se	Thermal	Resistance	Junction-case	Max	2.0	oC/W
Rth j-a mb.	Thermal	Resistance	Junction-ambient (Note1)	Max	50	oC/W

Note 1 : This thermal resistance corresponds to the standard mounting on a FR4 type printed circuit board.

CURRENT AND VOLTAGE CONVENTIONS

ICOMP

IDSENSE

IFB

IDRAIN

ICC

VCC

COMP

DSENSE

DRAIN

IDD

VDD

CURRENT

2.6V

CONTROL

IOSC

VOLTAGE CONTROL

OSC

GND

CREF

CSENSE

SOURCE

ICREF

ICSENSE

VIPer31

ISOURCE

VCOMP

VFB

VCC

VDD VOSC

VCREF

VCSENSE

VSOURCE

VDRAIN VDSENSE

SC12020

2/16

CONNECTION DIAGRAMS (top View)

PINS FUNCTIONAL DESCRIPTION

DRAIN PIN:

Integrated power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power.

SOURCE PIN:

Integrated power MOSFET source pin. To be connected to an external current sense resistance which defines the output current value.

GND

Used as the signal reference for all low level signals. To be connected to the cold point of the current sense resistance.

VDD PIN:

It corresponds to the low voltage supply of the control part of the circuit. If Vdd goes below 6V, the circuit is shut down and the start-up current source is activated. The circuit resumes normal operation when the VDD voltage reaches 8V. An internal low drop linear regulator generates the VDD voltage from the VCC one, thus limiting its value at 10V.

VCC PIN:

This pin receives the auxiliary unregulated voltage from the main transformer, which can range from 7V up to 27V during normal operation. It delivers a start up current of 1.5mA during the shut down phase. The VCC pin is also connected to an internal 10V low drop regulator which provides the VDD voltage.

VIPer31SP

CSENSE PIN:

Receives the voltage of the current sense resistor, representative from the power MOSFET drain current.

CREF PIN:

Serves as a reference for the peak power MOSFET drain current. It is also the output of the curent regulation function, which adjusts this reference voltage to keep the average output current constant. To be connected to an external filtering capacitor.

DSENSE PIN:

Detects the full demagnetisation of the main transformer, in order to drive the current regulation function. Refer to the application part for further details. It is also used to prevent any new turn on of the power MOSFET during the demagnetisation phase.

FB PIN:

This is the inverting input of the voltage mode error amplifier. This error amplifier is in charge of the limitation of the VCC voltage when the output current is lower than the nominal regulated one.

COMP PIN:

This is the output of the voltage mode error amplifier. An external R-C network connected between this pin and the FB pin defines the bandwidth of the voltage regulation loop, and insures the stability of the converter.

OSC PIN:

An RT-CT network must be connected on that pin to define the switching frequency. Note that despite the connection of RT to VDD, no significant frequency change occurs for VDD varying from 7V to 10V. It provides also a synchronisation capability, when connected to an external frequency source.

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VIPer31SP

ELECTRICAL CHARACTERISTICS (TJ = 25 oC, VCC = 12 V, unless otherwise specified) POWER SECTION

Symb ol	Parameter
BVDSS	Drain-Source Voltage
IDSS	Off-State Drain Current
RDS( on)	Static Drain Source on
	Resistance
tf	Fall Time

Test Cond ition s		Mi n.	Typ . Max.	Un it
ID = 1 mA	VCOMP = 0 V	600		V
VDS = 500 V	VCOMP = 0 V		1	mA
ID = 0.3 A	VSENSE = 0 V
TJ = 25 oC			6.5	Ω
TJ = 100 oC			10	Ω
ID = 0.3 A	Vin = 300 V (1)		250	ns
(see fig. 1)

tr	Rise Time	ID = 0.3 A	Vin = 300 V (1)	TBD	ns
		(see fig. 1)
COSS	Output Capacitance	VDS = 25 V		TBD	pF

(1) On Inductive Load, Clamped.

SUPPLY SECTION

Symb ol	Parameter	Test Cond ition s		Mi n.	Typ . Max.	Un it
ICCch	Start-up Charging	VDD = 0 to VDDon	VDS = 250 V		-1.5	mA
	Current	(see fig. 2)
ICC0	Operating Supply	FSW = 0 KHz			10	mA
	Current	(see fig. 2)
ICC1	Operating Supply	FSW = 100 KHz			TBD	mA
	Current
ICC2	Operating Supply	FSW = 200 KHz			TBD	mA
	Current
VDDo ff	Undervoltage	(see fig. 2)			6	V
	Shutdown
VDDo n	Undervoltage Reset	(see fig. 2)			8	V
VDDhyst	Hysteresis Start-up	(see fig. 2)		TBD	2	V
VDDreg	Output Voltage	(see fig. 2)		TBD	TBD	V
VDO	Drop Out Voltage	VCC = 9 V	IDD = TBD mA		TBD	mV
		(see fig. 2)
IDDsc	Short Circuit Current	VDD = 0 V			TBD	mA

OSCILLATOR SECTION

Symb ol	Parameter	Test Cond ition s			Mi n. Typ . Max. Un it
FSW1	Oscillator Frequency	RT = 8.2 KΩ	CT = 3300	pF	TBD	50	TBD	KHz
	Initial Accuracy	TJ = 25 oC	(see fig.3)
FSW2	Oscillator Frequency	RT = 8.2 KΩ	CT = 3300	pF	TBD	50	TBD	KHz
	Total Variation	VDD = 7 to10 V
VOSC HI	Oscillator Peak Voltage	(1)				6.2		V
VOSC LO	Oscillator Valley	(1)				2.5		V
	Voltage

(1) The peak and valley voltages are used internally by the voltage mode PWM. The sawtooth generated by the oscillator is compared to the COMP pin voltage to limit the duty cycle of the power mosfet switch. See block diagram on page 1.

4/16

VIPer31SP

ELECTRICAL CHARACTERISTICS (continued)

ERROR AMPLIFIER SECTION

Symb ol	Parameter
VREF	Reference Voltage
VREF	Temperaure Variation
GBW	Unity Gain Bandwidth
AVOL	Open Loop Voltage
	Gain
IFB	Input Bias Current
VCOMP LO	Output Low Level
VCOMP HI	Output High Level
ICOMP LO	Output Low Current
	Capability
ICOMP HI	Output High Current
	Capability

Test Cond ition s		Mi n. Typ . Max.			Un it
ICOMP = 0 mA	TJ = 25 oC	TBD	2.6	TBD	V
			TBD	TBD	%
(see fig. 4)			400		KHz
(see fig. 4)		TBD	50		dB
VFB = 5 V			2.5	5	μA
ICOMP = -100 μA	VFB = 5 V		1		V
ICOMP = 100 μA	VF B = 0 V		9		V
VCOMP = 5 V	VFB = 5 V		3.5		mA
VCOMP = 5 V	VFB = 0 V		-3.5		mA

CURRENT REGULATION SECTION

Symb ol	Parameter	Test Cond ition s		Mi n.	Typ .	Max.	Un it
VREG	Reference Voltage	(see fig. 5)		320	350	380	mV
td	Current Sense Delay	(See fig 1)				350	ns
	to Turn-off
VDSENSEth	Demagnetization	(see fig. 6)			2.6		V
	Detector Threshold
	Voltage
VDSENSEcl	Demagnetization	IDSENSE = 10 mA	(see fig. 6)		6		V
	Detector Clamping
	Voltage

PROTECTION SECTION

Symb ol	Parameter	Test Cond ition s		Mi n.	Typ .	Max.	Un it
IDl im	Peak Drain Current	RS = 0	(see fig. 9)	1		2.5	A
	Limitation
tb	Current Limitation	RS = 0	(see fig. 9)		1.2		μs
	Blanking Time
VCClim	VCC Overvoltage	VFB = 0 V	(see fig. 7)	26		35	V
	Threshold
VCChyst	VCC Overvoltage	VFB = 0 V	(see fig. 7)		2		V
	Hysteresis
TSD	Thermal Shutdown	(see fig. 8)		150			oC
	Temperature
TSDhyst	Thermal Shutdown	(see fig. 8)			TBD		oC
	Hysteresis

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