SGS-THOMSON TS68HC901 Technical data

TS68HC901

HCMOS MULTI-FUNCTION PERIPHERAL

The TS68HC901 CMFP (CMOS Multi-Function Peripheral) is a combination of many of the necessary peripheral functions in a microprocessor system.

.Included are :

8INPUT/OUTPUT PINS

•Individually programmable direction

•Individual interrupt source capability

	-	Programmable edge selection
.16 SOURCE INTERRUPT CONTROLLER
•	8 Internal sources
•	8 External sources
•	Individual source enable
•	Individual source masking
• Programmable interrupt service modes
	-	Polling
.•	-	Vector generation
	-	Optional In-service status
	Daisy chaining capability

FOUR TIMERS WITH INDIVIDUALLY PROGRAMMABLE PRESCALING

•Two multimode timers

-Delay mode

-Pulse width measurement mode

-Event counter mode

•Two delay mode timers

•Independent clock input

.• Time out output option SINGLE CHANNEL USART

•Full Duplex

•Asynchronous to 65 kbps

•Byte synchronous to 1 Mbps

•Internal/External baud rate generation

•DMA handshake signals

•Modem control

.• Loop back mode 68000 BUS COMPATIBLE

DESCRIPTION

The use of the CMFP in a system can significantly reduce chip count, thereby reducing system cost. The CMFP is completely 68000 bus compatible, and 24 directly addressable internal registers provide the necessary control and status interface to the programmer.

The CMFP is a derivative of the MK3801 STI, a Z80 family peripheral.

September 1992

PDIP48

PLCC52

(Ordering Information at the end of the Datasheet

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TS68HC901

INTRODUCTION

The TS68HC901 multi-function peripheral (CMFP) is a member of the 68000 peripherals. The CMFP directly interfaces to the 68000 processor via an a- synchronous bus structure. Both vectored and polled interrupt schemes are supported, with the CMFP providing unique vector number generation for each of its 16 interrupt sources. Additionally, handshake lines areprovided to facilitate DMAC interfacing. Refer to block diagram of the TS68HC901.

The TS68HC901 performs many of the functions common to most microprocessor-based systems.

.The resources available to the user include:

Eight Individually Programmable I/O Pins with In-

.terrupt Capability

16-Source Interrupt Controller with Individual

.Source Enabling and Masking

Four Timers, Two of which are Multi-Mode Timers

Figure 1: TS68HC901 Block Diagram

.Timers may be used as Baud Rate Generators

.for the Serial Channel

Single-Channel Full-Duplex Universal Synchronous / Asynchronous Receiver-Transmitter (U- SART) that Supports Asynchronous and with the Addition of a Polynomial Generator Checker Supports Byte Synchronous Formats

By incorporating multiple functions within the CMFP, the system designer retains flexibility while minimizing device count.

From a programmer's point of view, the versatility of the CMFP may be attributed to its register set. The registers are well organized and allow the CMFP to be easily tailored to a variety of applications. All of the 24 registers are also directly addressable which simplifies programming. The register map is shown in Figure 2.

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TS68HC901

Figure 2 : CMFP Register Map.

Address

Hex			Binary			Abbreviation	Register Name
Hex
	RS5	RS4	RS3	RS2	RS1
01	0	0	0	0	0	GPIP	General Purpose I/O Register
03	0	0	0	0	1	AER	Active Edge Register
05	0	0	0	1	0	DDR	Data Direction Register
07	0	0	0	1	1	IERA	Interrupt Enable Register A
09	0	0	1	0	0	IERB	Interrupt Enable Register B
0B	0	0	1	0	1	IPRA	Interrupt Pending Register A
0D	0	0	1	1	0	IPRB	Interrupt Pending Register B
0F	0	0	1	1	1	ISRA	Interrupt In-service Register A
11	0	1	0	0	0	ISRB	Interrupt In-service Register B
13	0	1	0	0	1	IMRA	Interrupt Mask Register A
15	0	1	0	1	0	IMRB	Interrupt Mask Register B
17	0	1	0	1	1	VR	Vector Register
19	0	1	1	0	0	TACR	Timer A Control Register
1B	0	1	1	0	1	TBCR	Timer B Control Register
1D	0	1	1	1	0	TCDCR	Timers C and D Control Register
1F	0	1	1	1	1	TADR	Timer A Data Register
21	1	0	0	0	0	TBDR	Timer B Data Register
23	1	0	0	0	1	TCDR	Timer C Data Register
25	1	0	0	1	0	TDDR	Timer D Data Register
27	1	0	0	1	1	SCR	Synchronous Character Register
29	1	0	1	0	0	UCR	USART Control Register
2B	1	0	1	0	1	RSR	Receiver Status Register
2D	1	0	1	1	0	TSR	Transmitter Status Register
2F	1	0	1	1	1	UDR	USART Data Register

Not e : Hex addresses assume that RS1 connects with A1, RS2connects wi th A2, etc... and that DS is connected to LDS on the 68000 or DS is connect to DS on the 68008.

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TS68HC901

Figure 3 : PDIP Pin connection

Figure 4 : PLCC Pin connection

Pin	MOTOROLA	MOTOROLA	INTEL
	6800 Type	Multiplexed
48	CS	CS	CS
47	E	DS	RD
1	R/W	R/W	WR
35	VSS	AS	ALE

PIN DESCRIPTION

GND : Ground

VCC : +5 volts (± 5%)

R/W : Read/Write (input). This input defines a data transfert as a Read (High) or Write (Low) cycle. This signal is used as WR with an Intel processor type.

DTACK : This output signals the completion of the operation phase of a bus cycle to the processor. If the bus cycle is a processor read, the CMFP asserts DTACK to indicate that the information on the Data bus is valid. If the bus cycle is a processor to the CMFP, DTACK acknowledges the acceptance of the data by the CMFP. DTACK will be asserted only by an CMFP that has CS or IAK (and IEI) asserted. This signal is not used with a 6800 processor type.

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CS : Chip Select (input, active low). CS is u- sed to select the TS68HC901 CMFP for accesses to the internal registers. CS and IACK must not be asserted at the same time.

DS : Data Stobe (input, active low).This Input is part of the internal chip select and interrupt acknowledge functions.

The CMFP must be located on the lower portion of the 16-bit data-bus so that the vector number passed to the processor during an interrupt acknowledge cycle will be located in the low byte of the data word. As a result, DS must be connected to the processor's lower data strobe if vectored interrupt are to be used. Note that this forces all registers to be located at odd addresses and latches data on the rising edge for writes. This signal is used as RD with an Intel processor type.

RS1-RS5: Register Address Bus (inputs). The ad- (A1-A5) dress bus is used to address one of the internal registers during a read or write

cycle.

D0-D7 : Data Bus (bi-directional, tri-stateable). This bus is used to receive data from or transmit data to the MFP's internal registers during a processor read or write cycle. During an interrupt acknowledge cycle, the data bus is used to pass a vector number to the processor. Since the MFP is an 8-bit peripheral, the MFP could be located on either the upper or lower portion of the 16-bit data bus (even or odd address). However, during an interrupt acknowledge cycle, the vector number passed to the processor must be located in the low byte of the data word. As a result, D0-D7 of the MFP must be connected to the low eight bits of the processor data bus, placing MFP registers at odd addresses if vectored interrupt are to be used.

CLK : The clock input is a single-phase TTL compatible signal used for internal timing . This input should not be gated off at any time and must conform to minimum and maximum pulse width times. The clock is not necessarily the system clock in frequency nor phase. When the bus is multiplexed (MPX=1), an address strobe signal is connected to this pin. In the non multiplexed mode (MPX=0), this input is connected to the system clock when used with a 68000 processor type or to VSS (0VDC) when used with a 6800 processor type.

RESET : Device reset. (input, active low). Reset disables the USART receiver and transmitter, stops all timers and forces the timer outputs low, disables all interrupt channels and clears any pending interrupts. The General Purpose Interrupt/I/O lines will be placed in the tri-state input mode. All internal registers (except the timer, USART data registers, and transmit status register) will be cleared.

MPX : This input selects the data bus mode:

MPX = 0 : non multiplexed mode

MPX = 1 : multiplexed mode. The register select lines RS1-RS5 and the data bus D0-D7 are multiplexed. An address strobe must be connected to the CLK pin.

TS68HC901

IRQ : Interrupt Request (output, active low, o- pen drain). This output signals the processor that an interrupt is pending from the CMFP. These are 16 interrupt channels that can generate an interrupt request. Clearing the interrupt pending registers (IPRA and IPRB) or clearing the interrupt mask registers (IMRA and IMRB) will cause IRQ to be negated. IRQ will also be negated as the result of an interrupt acknowledge cycle, unless additional interrupts are pending in the CMFP. Ref er to paragraph INTERRUPTS for further information.

IACK : Interrupt Acknowledge (input, active low). IACK is us ed t o s ignal t he TS68HC901 that the CPU is acknowledging an interrupt. CS and IACk must not be asserted at the same time.

IEI : Interrupt Enable In (input, active low). IEI is used to signal the TS68HC901 that no higher priority device is requesting interrupt service.

IEO : Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals that neither the TS68HC901 nor another higher priority peripheral is requesting interrupt service.

I0-I7 : General Purpose Interrupt I/O lines. These lines may be used as interrupt inputs and/or I/O lines. When used asinterrupt inputs, their active edge is programmable. A data direction register is used to define which lines are to be Hi-Z inputs and which lines are to be push-pull TTL compatible outputs.

SO : Serial Output. This is the output of the U- SART transmitter.

SI : Serial Input. This is the input to the U- SART receiver.

RC : Receiver Clock. This input controls the serial bit rate of the USART receiver.

TC : Transmitter Clock. This input controls the serial bit rate of the USART transmitter.

RR: Receiver Ready. (output, active low) DMA output for receiver, which reflects the status of Buffer Full in port number 15.

TR : Transmitter Ready. (output, active low) DMA output for transmitter, which reflects the status of Buffer Empty in port number 16.

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TS68HC901

TAO,TBO,Timer Outputs. Each of the four timers		TAI,TBI :
TCO,TDO:has an output which can produce a
	square wave. The output will change
	states each timer cycle ; thus one full pe-
	riod of the timer out signal is equal to two
	timer cycles. TAO or TBO can be reset
	(logic ºOº) by a write to TACR, or TBCR
	respectively.
XTAL1,	Timer Clock inputs. A crystal can be
XTAL2 :	connected between XTAL1 and XTAL2,
	or XTAL1 can be driven with a TTL level
	clock. When driving XTAL1 with a TTL le-

vel clock, XTAL2 must be allowed tofloat. When using a crystal, external capacitors are required. See figure 35. All chip accesses are independent of the timer clock.

Signal Name	Mnemonic
Power Input	VCC
Ground	GND
Clock	CLK
Chip Select	CS
Data Strobe	DS
Read/Write	R/W
Data tranfer Acknowledge	DTACK
Register Select Bus	RS1-RS5
Data Bus	D0-D7
Reset	RESET
Interrupt Request	IRQ
Interrupt Acknowledge	IACK
Interrupt Enable In	IEI
Interrupt Enable Out	IEO
General Purpose I/O - Interrupt Lines	I0-I7
Timer Clock	XTAL1, XTAL2
Timer Inputs	TAI, TBI
Timer Outputs	TAO, TBO, TCO, TDO
Serial Input	SI
Serial Output	SO
Receiver Clock	RC
Transmitter Clock	TC
Receiver Ready	RR
Transmitter Ready	TR
MPX	MPX

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Timer A, B inputs. These inputs are control signals for timers A and B in the pulse width measurement mode and e- vent count mode. These signals generate interrupts at the same priority level as the general purpose I/O interrupt lines I4 and I3, respectively. I4 and I3 do not have interrupt capability when the timers are operated in the pulse width measurement mode or the event count mode - under these conditions I4 and I3 may only be used for I/O. Refer to paragraph TIMERS for further information.

	SIGNAL SUMMARY.
I/O	Active
Input	High
Input	Low
Input	N/A
Input	Low
Input	Low
Input	Read-High / Write-Low
Output	Low
Input	N/A
I/O	N/A
Input	Low
Output	Low
Input	Low
Input	Low
Output	Low
I/O	N/A
Input	High
Input	N/A
Output	N/A
Input	N/A
Output	N/A
Input	N/A
Input	N/A
Output	Low
Output	Low
Input	N/A

BUS OPERATION

The following paragraphs explain the control signals and bus operation during data transfer operations and reset.

DATA TRANSFER OPERATIONS.

Transfer of data between devices involves the following pins: Register Select Bus - RS5 through RS1 Data Bus - D0 through D7 Control Signals The address and data buses are separate parallel buses u- sed to transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. Additionally, the bus master is responsible for deskewing the acknowledge and data signals from the peripheral devices.

Read Cycle. To read a CMFP register, CS and DS must be asserted, and R/W must be high. The CMFP will place the content of the register which is selected by the register select bus (RS1 through RS5) on the data bus (D1 through D7) and then assert DTACK. The register addresses are shown on Figure 2. After the processor has latched the data, DS is negated. The negation of either CS or DS will terminate the read operation. The CMFP will drive DTACK High and place it in the high-impedance state. The timing for a read cycle is shown in figure 21.

Write Cycle. To write a register CS and DS must be asserted, and R/W must be low. The CMFP will decode the address bus to determine which register is selected. Then the register will be loaded with the contents of the data bus and DTACK will be asserted. When the processor recognizes DTACK, DS will be negated. The write cycle is terminated when either CS or DS is negated. The CMFP will drive DTACK high and place it in the high-impedance state. The timing for a write cycle is shown in figure 22.

TS68HC901

INTERRUPT ACKNOWLEDGE OPERATION.

The CMFP has 16 interrupt sources, eight internal and eight external. When an interrupt request is pending, the CMFP will assert IRQ. In a vectored interrupt scheme, the processor will acknowledge the interrupt request by performing an interrupt acknowledge cycle. IACK and DS will be asserted. The CMFP responds to the IACK signal by placing a vector number on the lower eight bits of the data bus. This vector number corresponds to the IRQ handler for the particular interrupt requesting service. The format of this vector number is given in figure 6.

When the CMFP asserts DTACK to indicate that valid data is on the bus, the processor will latch the data and terminate the bus cycle by negating DS. When either DS or IACK are negated, the CMFP will terminate the interrupt acknowledge operation by driving DTACK high and placing it in the high-impe- dance state. Also, the data bus will be placed in the high-impedance state. IRQ will be negated as a result of the IACK cycle unless additional interrupts are pending.

The CMFP can be part of a daisy-chain interrupt structure which allows multiple CMFPs to be placed at the same interrupt level by sharing a common IACK signal. A daisy-chain priority scheme is implemented with IEI and IEO signals. IEI indicates that no higher priority device is requesting interrupt service. IEO signals lower priority devices that neither this device nor any higher priority devices is requesting service. To daisy-chain CMFPs, the highest priority CMFP has its IEI tied low and successive CMFPs have their IEI connected to the next higher priority device's IEO. Note that when the daisy-chain

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TS68HC901

interrupt structure is not implemented, the IEI of all CMFPs must be tied low.

When the processor initiates an interrupt acknowledge cycle by driving IACK and DS, the CMFP whose IEI is low may respond with a vector number if interrupt is pending. If this device does not have a pending interrupt, IEO is asserted which allows the next lower priority device to respond to the interrupt acknowledge. When an CMFP propagates IEO, it will not drive the data bus nor DTACK during the interrupt acknowledge cycle. The timing for an IACK cycle is shown in figure 23 and 24.

RESET OPERATION

The reset operation will initialize the CMFP to a known state. The reset operation requires that the RESET input be asserted for a minimum of two microseconds. During a device reset condition, all internal CMFP registers are cleared except for the timer data registers (TADR, TBDR, TCDR and TDDR), the USART data register (UDR), the transmitter status register (TSR) and the interrupt vector register. All timers are stopped and the USART receiver and transmitter are disabled. The interrupt channels are also disabled and any pending inter-

rupts are cleared. In addition, the general purpose interrupt I/O lines are placed in the highimpedance input mode and the timer outputs are driven low. External CMFP signals are negated. The interrupt vector register is initialized to a 0Fh.

NON MULTIPLEXED MODE

In this mode, the MPX input must be set to zero, and the TS68HC901 can be used with a 68000 processor type or a 6800 processor type. Refer to figure 21 to 24 for the electrical characteristics.

With a 6800 processor type the DS pin is connected to the E signal of the processor, the DTACK signal is not used and the CLK must be zeroed.

MULTIPLEXED MODE

The CMFP can be used either on a MOTOROLA or INTEL bus type. In this case the MPX pin is connected to Vcc. The table page 4 gives the signification of the different signals used. A dummy access to the TS68HC901 has to be done before any valid access in order to set up the internal logic of sampling.

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TS68HC901

INTERRUPT STRUCTURE

In a 68000 system, the CMFP will be assigned to one of the seven possible interrupt levels. All interrupt service requests from the CMFP's 16 interrupt channels will be presented at this level. Although, as an interrupt controller, the CMFP will internally prioritize its 16 interrupt sources. Additional interrupt sources may be placed at the same interrupt level by daisy-chaining multiple CMFPs. The CMFPs will be prioritized by their position in the chain.

INTERRUPT PROCESSING

begin execution of the interrupt handler for the interrupt source, decreasing interrupt latency time.

INTERRUPT CHANNEL PRIORITIZATION

The 16 interrupt channels are prioritized as shown in figure 5. General purpose interrupt 7 (I7) is the highest priority interrupt channel and I0 is the lowest priority channel. Pending interrupts are presented to the CPU in order of priority unless they have been masked off. By selectively masking interrupts, the channel are in effect re-prioritized.

Each CMFP provides individual interrupt capability for its various functions. When an interrupt is received on one of the external interrupt channels or from one of the eight internal sources, the CMFP will request interrupt service. The 16 interrupt channels are assigned a fixed priority so that multiple pending interrupts are serviced according to their relative importance. Since the CMFP can internally generate 16 vector numbers, the unique vector number which corresponds to the highest priority channel that as a pending interrupt is presented to the processor during an interrupt acknowledge cycle. This unique vector number allows the processor to immediately

INTERRUPT VECTOR NUMBER FORMAT

During an interrupt acknowledge cycle, a unique 8- bit vector number is presented to the system which corresponds to the specific interrupt source which is requesting service. The format of the vector is shown in figure 6. The most significant four bits of the interrupt vector number are user programmable. These bits are set by writing the upper four bits of the vector register which is shown in figure 7. The low order bits are generated internally by the TS68HC901. Note that the binary channel number shown in figure 5 corresponds to the low order bits of the vector number associated with each channel.

Figure 5 : Interrupt Channel Prioritization

Figure 9 : Interrupt Channel Prioritization

Priority	Channel	Description
HIGHEST	1111	General Purpose Interrupt 7(I7)
	1110	General Purpose Interrupt 6(I6)
	1101	Timer A
	1100	Receive Buffer Full
	1011	Receive Error
	1010	Transmit Buffer Empty
	1001	Transmit Error
	1000	Timer B
	0111	General Purpose Interrupt 5(I5)
	0110	General Purpose Interrupt 4(I4)
	0101	Timer C
	0100	Timer D
	0011	General Purpose Interrupt 3(I3)
	0010	General Purpose Interrupt 2(I2)
	0001	General Purpose Interrupt 1(I1)
LOWEST	0000	General Purpose Interrupt 0(I0)

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TS68HC901

								Figure 6 :
	V7	V6	V5	V4	IV3	IV2	IV1	IV0
V7-V4	The four most significant bits are copied from the register
IV3-IV0	These bits are supplied by the CMFP. They are the binary channel number of the highest
	priority channel that is requesting interrupt service.

Figure 7 :

	7			VECTOR REGISTER				0
VR	V7	V6	V5	V4	S	0*	0*	0*
(17h)

Writing 0 : CLEARED

Writing 1 : SET

CLEARED on RESET

V7-V4 The upper four bits of the vector register are written by the user. These bits become the most significant four bits of the interrupt vector number.

SIn-Service Register Enable. When the S bit is zero, the CMFP is in the automatic end-of-in- terrupt mode and the In-Service register bits are forced low. When the S bit is a one, the CMFP is in the software end-of-interrupt mode and the In-Service register bits are enabled.

*	Unused bits, read as zero.

Figure 8 : Daisy Chaining

TS68HC901

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DAISY-CHAINING CMFPs

As an interrupt controller, the TS68HC901 CMFP will support eight external interrupt sources in addition to its eight internal interrupt sources. When a system requires more than eight external interrupt sources to be placed at the same interrupt level, sources may be added to the prioritized structure by daisy-chaining CMFPs. Interrupt sources are prioritized internally within each CMFP and the CMFPs are prioritized by their position in the chain. Unique vector numbers are provided for each interrupt sources.

The IEI and IEO signals implement the daisy-chai- ned interrupt structure. The IEI of the highest priority CMFP is tied low and the IEO output of this device is tied to the next highest priority CMFP's IEI. The

TS68HC901

IEI and IEO signals are daisy-chained in this manner for all CMFPs in the chain, with the lowest priority CMFP's IEO left unconnected. A diagram of an interrupt daisy-chain is shown in figure 8.

Daisy-chaining requires that all parts in the chain have a common IACK. When the common IACK is asserted during an interrupt acknowledge cycle, all parts will prioritize interrupts in parallel. When the IEI signal to a CMFP is asserted, the part may respond to the IACK cycle if it requires interrupt service. Otherwise, the part will assert IEO to the next lower priority device. Thus, priority is passed down the chain via IEI and IEO until a part which has appending interrupt is reached. The part with the pending interrupt passes a vector number to the processor and does not propagate IEO.

Figure 9a :

Figure 9b :

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TS68HC901

INTERRUPT CONTROL REGISTERS

CMPF interrupt processing is managed by the interrupt enable registers A and B, interrupt pending registers A and B, and interrupt mask registers A and B. These registers allow the programmer to enable or disable individual interrupt channels, mask individual interrupt channels, and access pending interrupt status information. In-service registers A and B allow interrupts to be nested as described hereafter. The interrupt control registers are shown in figure 10.

INTERRUPT ENABLE REGISTERS

The interrupt channels are individually enabled or disabled by writing a one or zero, respectively, to the appropriate bit of interrupt enable register A (IERA) or interrupt enable register B (IERB). The processor may read these registers at any time.

When a channel is enabled, interrupts received on the channel will be recognized by the CMFP and IRQ will be asserted to the processor, indicating that interrupt service is required. On the other hand, a disabled channel is completely inactive; interrupts received on the channel are ignored by the CMFP.

Writing a zero to a bit of interrupt enable register A or B will cause the corresponding bit of interrupt pending register A or B to be cleared. This will terminate all interrupt service requests for the channel and also negate IRQ, unless interrupts are pending from other sources. Disabling a channel, however, does not affect the corresponding bit in interrupt in-ser- vice registers A or B. So, if the CMFP is in the software end-of-interrupt mode and an interrupt is in service when a channel will remain set until cleared by software.

INTERRUPT PENDING REGISTERS

When an interrupt is received on an enabled channel, the corresponding interrupt pending bit is set in interrupt pending register A or B (IPRA or IPRB). In a vectored interrupt scheme, this bit will be cleared when the processor acknowledges the interrupting channel and the CMFP responds with a vector number. In a polled interrupt system, the interrupt pending registers must be read to determine the interrupting channel and then the interrupting pending bit is cleared by the interrupt handling routine without performing an interrupt acknowledge sequence.

A single bit of the interrupt pending registers is cleared in software by writing ones to all bit positions except the bit to be cleared. Note that writing ones to IPRA and IPRB has no effect on the contents of the register. A single bit of the interrupt pending registers is also cleared when the corresponding channel is disabled by writing a zero to the appropriate bit of IERA or IERB.

INTERRUPT MASK REGISTERS

Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register A or B (IMRA or IMRB). Even though an enabled channel is masked, the channel will recognize subsequent interrupts and set its interrupt pending bit. However, the channel is prevented from requesting interrupt service (IRQ to the processor) as long as the mask bit for that channel is cleared.

If a channel is requesting interrupt service at the time that its corresponding bit in IMRA or IMRB is cleared, the request will cease and IRQ will be negated, unless another channel is requesting interrupt service. Later, when the mask bit is set, any pending interrupt on the channel will be processed according to the channel's assigned priority. IMRA and IMRB may be read at any time.

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								TS68HC901
								Figure 10 :
	7		INTERRUPT ENABLE REGISTERS					0
IERA	GPIP7	GPIP6	TIMER A	RCV	RCV	XMIT	XMIT	TIMER B
(07h)				Buffer full	Error	Buffer Empty	Error

IERB	GPIP5	GPIP4	TIMER C	TIMER D	GPIP3	GPIP2	GPIP1	GPIP0
(09h)

	7		INTERRUPT PENDING REGISTERS					0
IPRA	GPIP7	GPIP6	TIMER A	RCV	RCV	XMIT	XMIT	TIMER B
(0Bh)				Buffer full	Error	Buffer Empty	Error

IPRB	GPIP5	GPIP4	TIMER C	TIMER D	GPIP3	GPIP2	GPIP1	GPIP0
(0Dh)

			Wri ti ng 0 : CLEAR
			Wri ti ng 1 : UNCHANGED
	7		INTERRUPT IN-SERVICE REGISTERS					0
ISRA	GPIP7	GPIP6	TIMER A	RCV	RCV	XMIT	XMIT	TIMER B
(0Fh)				Buffer full	Error	Buffer Empty	Error

ISRB	GPIP5	GPIP4	TIMER C	TIMER D	GPIP3	GPIP2	GPIP1	GPIP0
(11h)

	7		INTERRUPT MASK REGISTERS					0
IMRA	GPIP7	GPIP6	TIMER A	RCV	RCV	XMIT	XMIT	TIMER B
(13h)				Buffer full	Error	Buffer Empty	Error

IMRB	GPIP5	GPIP4	TIMER C	TIMER D	GPIP3	GPIP2	GPIP1	GPIP0
(15h)

Writing 0 : MASKED

Writing 1 : UNMASKED

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