SGS-THOMSON TDA9105A Technical data

TDA9105A

TDA9105A

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

.HORIZONTAL

.DUAL PLL CONCEPT

.150kHz MAXIMUM FREQUENCY

.SELF-ADAPTATIVE

.X-RAY PROTECTION INPUT

.DC ADJUSTABLE DUTY-CYCLE

.1st PLL LOCK /UNLOCK INFORMATION

WIDE RANGE DC CONTROLLED H-POSI-

.TION

ON/OFF SWITCH (FOR PWR MANAGE-

.MENT)TWO H-DRIVE POLARITIES

.VERTICAL

.VERTICAL RAMP GENERATOR

.50 TO 185Hz AGC LOOP

.DCCONTROLLEDV-AMP,V-POS,S-AMP& C-COR ON/OFF SWITCH

.EWPCC

VERTICAL PARABOLA GENERATOR WITH

.DC CONTROLLED KEYSTONE& AMPLITUDE

.AUTO TRACKING WITH V-POS & V-AMP CORNER CORRECTION WITH DC CONTROLLED AMPLITUDE

.GEOMETRY

WAVE FORM GENERATOR FOR PARALEL-

.LOGRAM & SIDE PIN BALANCE CONTROL AUTO TRACKING WITH V-POS & V-AMP

.DYNAMIC FOCUS

VERTICAL PARABOLA OUTPUT FOR VERTI-

.CAL DYNAMIC FOCUS

AUTO TRACKING WITH V-POS & V-AMP

.GENERAL

ACCEPT POSITIVE OR NEGATIVE HORI-

.ZONTAL & VERTICAL SYNC POLARITIES

.SEPARATE H & V TTL INPUT COMPOSITE BLANKING OUTPUT

DESCRIPTION

The TDA9105A is a monolithic integrated circuit assembled in a 42 pins shrink dual in line plastic package.

July 1997

PRODUCT PREVIEW

This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors.

This IC, combined with TDA9205 (RGB preamp), STV942x(OSD processor), ST727x(micro controller) and TDA817x (vertical booster), allows to realize very simple and high quality multimodes or multisync monitors.

SHRINK42

(Plastic Package)

ORDER CODE : TDA9105A

PIN CONNECTIONS

V-FOCUS	1	42	SPINBAL
H-LOCKOUT	2	41	KEYBAL
PLL2C	3	40	GEOMOUT
H-DUTY	4	39	EWAMP
H-FLY	5	38	KEYST
H-GND	6	37	EWOUT
H-REF	7	36	V-FLY
FC2	8	35	VDCIN
FC1	9	34	V-SYNC
C0	10	33	V-POS
R0	11	32	VDCOUT
PLL1F	12	31	V-AMP
H-LOCKCAP	13	30	V-OUT
PLL1INHIB	14	29	C-CORR
H-POS	15	28	VS-AMP
XRAY-IN	16	27	V-CAP
H-SYNC	17	26	V-REF
VCC	18	25	V-AGCCAP
GND	19	24	V-GND	01.EPS-
H-OUTEM	20	23	CORNER
H-OUTCOL	21	22	BLK-OUT	9105A

1/31

This is advance information on a new product now in developmentor undergoingevaluation . Details are subject to change without notice.

TDA9105A

PIN DESCRIPTION

Pin	Name	Function
1	V-FOCUS	Vertical Dynamic Focus Output
2	H-LOCKOUT	First PLL Lock/Unlock Output
3	PLL2C	Second PLL Loop Filter
4	H-DUTY	DC Control of Horizontal Drive Output Pulse Duty-cycle. If this Pin is grounded, the Horizontal
		and Vertical Outputs are inhibited. By connecting a Capacitor on this Pin a Soft-start function
		may be realized on H-drive Output.
5	H-FLY	Horizontal Flyback Input (positive polarity)
6	H-GND	Horizontal Section Ground
7	H-REF	Horizontal Section Reference Voltage, must be filtered
8	FC2	VCO Low Threshold Filtering Capacitor
9	FC1	VCO High Threshold Filtering Capacitor
10	C0	Horizontal Oscillator Capacitor
11	R0	Horizontal Oscillator Resistor
12	PLL1F	First PLL Loop Filter
13	H-LOCKCAP	First PLL Lock/Unlock Time Constant Capacitor. When Frequency is changing, a Blanking
		Pulse is generated on Pin 23, the duration of this Pulse is proportionnal to the Capacitor on
		Pin 13.
14	PLL1INHIB	TTL-Compatible Input for PLL1 Output Current Inhibition
15	H-POS	DC Control for Horizontal Centering
16	XRAY-IN	X-RAY protection Input (with internal latch function)
17	H-SYNC	TTL compatible Horizontal Sync Input
18	VCC	Supply Voltage (12V Typ.)
19	GND	Ground
20	H-OUTEM	Horizontal Drive Output (emiter of internal transistor)
21	H-OUTCOL	Horizontal Drive Output (open collector of internal transistor)
22	BLK OUT	Blanking Output, activated during frequency changes, when X-RAY Input is triggered, when
		VS is too low, or when Device is in stand-by mode (through H-DUTY Pin 2) and during H-FLY,
		V-FLY, V-SYNC, VSawth retrace.
23	CORNER	DC Control of Corner Correction Amplitude
24	V-GND	Vertical Section Signal Ground
25	V-AGCCAP	Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26	V-REF	Vertical Section Reference Voltage
27	V-CAP	Vertical Sawtooth Generator Capacitor
28	VS-AMP	DC Control of Vertical S-Shape Amplitude
29	C-CORR	DC Control of Vertical C-Correction
30	V-OUT	Vertical Ramp Output (with frequency independant amplitude and S-Correction)
31	V-AMP	DC Control of Vertical Amplitude Adjustment
32	VDCOUT	Vertical Position Reference Voltage Output
33	V-POS	DC Control of Vertical Position Adjustment
34	V-SYNC	TTL-Compatible Vertical Sync Input
35	VDCIN	Geometric Correction Reference Voltage Input
36	V-FLY	Vertical Flyback Input (positive polarity)
37	EWOUT	East /West Pincushion Correction Parabola Output
38	KEYST	DC Control of Keystone Correction
39	EWAMP	DC Control East/West Pincushion Correction Amplitude
40	GEOMOUT	Side Pin Balance & Parallelogram Correction Parabola Output
41	KEYBAL	DC Control of Parallelogram Correction
42	SPINBAL	DC Control of Side Pin Correction Amplitude

9105A-01.TBL

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TDA9105A

BLOCK DIAGRAM

GND	V	CORNER	-VFOCUS	KEYST	EWOUT	EWAMP	KEYBAL	GEOMOUT	SPINBAL
	CC
19	18	23	1	38	37	39	41	40	42

		H OUTPUT BUFFER		X2
H-OUTEM	20					X2
H-OUTCOL	4 21		SAFETY PROCESSOR
H-DUTY		PULSE SHAPER					BLK	GEN
H-LOCKOUT	216		VS					FLY-H	SYNC-
XRAY-IN
		PHASE SHIFTER							V
PLL2C	3	PHASE COMP	UNLOCKVIDEO			MID-V
H-FLY	985
FC1
FC2
R0	1215 10 11	PHASE FREQUENCYVCO COMP					OSCVERT	RAMP	GENERATOR
C0			LOCK UNLOCK IDENT
PLL1F						V-REF	S CORR
H-POS
		V-REF	PULSE SHAPER POL DETECT	PLL1 INHIB			PULSE SHAPER POL DETECT
	7	6	17	14	13	26	24	34
	H-REF	H-GND	H-SYNC	PLL1INHIB	-LOCKCAP	V-REF	V-GND	V-SYNC
					H

35	VDCIN

22	BLK-OUT
36	V-FLY

32	VDCOUT
33	V-POS
30	V-OUT
31	V-AMP
25	VAGCCAP
27	VCAP
29	C-CORR
28	VS-AMP

TDA9105A

9105A-02.EPS

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TDA9105A

QUICK REFERENCE DATA

Parameter	Value	Unit
Horizontal Frequency	15 to 150	kHz
Autosynch Frequency (for Given R0, C0)	1 to 3.7	FH
± Hor Sync Polarity Input	YES
Compatibility with Composite Sync on H-SYNC Input	YES (see note 1)
Lock/Unlock Identification on 1st PLL	YES
DC Control for H-Position	YES
X-RAY Protection	YES
Hor DUTY Adjust	YES
Stand-by Function	YES
Two Polarities H-Drive Outputs	YES
Supply Voltage Monitoring	YES
PLL1 Inhibition Input	YES
Composite Blanking Output	YES
Horizontal Moire Output	NO
Vertical Frequency	35 to 200	Hz
Vertical Autosync (for 150nF)	50 to 185	Hz
Vertical S-Correction	YES
Vertical C-Correction	YES
Vertical Amplitude Adjustment	YES
Vertical Position Adjustment	YES
East/West Parabola Output	YES
PCC (Pin Cushion Correction) Amplitude Adjustment	YES
Keystone Adjustment	YES
Corner Correction Adjustment	YES
Dynamic Horizontal Phase Control Output	YES
Side Pin Balance Amplitude Adjustment	YES
Parallelogram Adjustment	YES
Tracking of Geometric Corrections with V-AMP and V-POS	YES
Reference Voltage	YES (see note 2)
Mode Detection	NO
Vertical Dynamic Focus	YES

Notes : 1. Provided PLL inhibition input is used, see application diagram on page 27. 2. One for Horizontal section and one for Vertical section.

9105A-02.TBL

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TDA9105A

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value
VCC	Supply Voltage (Pin 18)	13.5
VIN	Max Voltage on Pins 4, 15, 28, 29, 31, 33, 38, 39, 41, 42	8
	Pin 5	1.8
	Pins 17, 34	6
	Pin 16, 2, 22	12
	Pin 14	5
VESD	ESD Succeptibility
	Human Body Model, 100pF Discharge through 1.5kΩ	2
	EIAJ Norm, 200pF Discharge through 0Ω	300
Tstg	Storage Temperature	-40, +150
Tj	Max Operating Junction Temperature	150
Toper	Operating Temperature	0, +70

THERMAL DATA

Symbol	Parameter		Value
Rth (j-a)	Junction-Ambient Thermal Resistance	Max.	65

Unit

V

V

V

V

V

V

kV V

°C °C °C

Unit

°C/W

9105A-04.TBL 9105A-03.TBL

HORIZONTAL SECTION

Operating Conditions

Symbol	Parameter	Test Conditions	Min.	Typ. Max.	Unit
VCO
R0min	Oscillator Resistor Min Value (Pin 11)		6		kΩ
C0min	Oscillator Capacitor Min Value (Pin 10)		390		pF
Fmax	Maximum Oscillator Frequency			150	kHz
HsVR	Horizontal Sync Input Voltage (Pin 17)		0	5.5	V
INPUT SECTION
MinD	Minimum Input Pulses Duration (Pin 17)		0.7		μS
Mduty	Maximum Input Signal Duty Cycle (Pin 17)			25	%
OUTPUT SECTION
I5m	Maximum Input Peak Current (Pin 5)			5	mA
HOI1	Horizontal Drive Output Max Current
	Pin 20	Sourced current		20	mA
HOI2	Pin 21	Sink current		20	mA
DC CONTROL VOLTAGES
DCadj	DC Voltage on DC Controls (Pins 4-15)	VREF-H = 8V	2	6	V

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TDA9105A

HORIZONTAL SECTION (continued)

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol	Parameter		Test Conditions	Min.	Typ.	Max.	Unit
SUPPLY AND REFERENCE VOLTAGES
VCC	Supply Voltage (Pin 18)			10.8	12	13.2	V
ICC	Supply Current (Pin 18)		See Figure 1		45	65	mA
VREF-H	Reference Voltage for Horizontal Section (Pin 7)		I = 2mA	7.4	8	8.6	V
IREF-H	Max Sourced Current on VREF-H (Pin 7)					5	mA
VREF-V	Reference Voltage for Vertical Section (Pin 26)		I = 2mA	7.4	8	8.6	V
IREF-V	Max Sourced Current on VREF-V (Pin 26)					5	mA
INPUT SECTION/PLL1
VINTH	Horizontal Input Threshold Voltage (Pin 17)		Low level voltage	2		0.8	V
			High level voltage
VVCO	VCO Control Voltage (Pin 12)		VREF-H = 8V		1.6 to 6.2		V
VCOG	VCO Gain, dF/dV (Pin 12)		R0 = 6.49kΩ, C0 = 680pF		17		kHz/V
Hph	Horizontal Phase Adjust (Pin 15)		% of Horizontal period		±12.5		%
f0	Free Running Frequency (adjustable by changing R0)		R0 = 6.49kΩ, C0 = 680pF	25	27	29	kHz
CR	PLL1 Capture Range		R0 = 6.49kΩ, C0 = 680pF
		Fh Min	See conditions on Fig. 1		f0		kHz
		Fh Max			3.7 x f0		kHz
PLLinh	PLL 1 Inhibition (Pin 14)	PLL ON	V14			0.8	V
	(Typ. Threshold = 1.6V)	PLL OFF	V14	2			V
IHLock0	Max Output Current on HLock Output		I2			10	mA
VHLock0	Low Level Voltage on HLock Output		V2 with I2 = 10mA		0.25	0.5	V
SECOND PLL AND HORIZONTAL OUTPUT SECTION

FBth	Flyback Input Threshold Voltage (Pin 5)		See Figure 14	0.60	0.70
Hjit	Horizontal Jitter		See Application Diagram		80
			(Pins 8-9)
	Horizontal Drive Output Duty-cycle
HDmin	(Pin 20 or 21) (see Note)		V4 = 2V	31	33.2	35.5
	Minimum
			V4 = 6V	54.5	57	59.5
HDmax	Maximum		V4 = VREF - 500mV		61.5
HDvd	Horizontal Drive Low Level Output Voltage		Pin 20 to GND,		1.1	1.7
			V21-V20, IOUT = 20mA
HDem	Horizontal Drive High Level Output Voltage		Pin 21 to VCC,	9.5	10
	(output on Pin 20)		IOUT = 20mA
XRAYth	X-RAY Protection Input Threshold Voltage (Pin 16)			TBD	8	TBD
ISblkO	Maximum Output Current on Composite Blanking		I22			10
	Output
VSblkO	Low-Level Voltage on Composite Blanking Output		V22 with I22 = 10mA		0.25	0.5
	(Blanking ON)
Vphi2	Internal Clamping Voltage on 2nd PLL Loop Filter		Vmin		1.6
	Output (Pin 3)		Vmax		4.0
VOFF	Threshold Voltage to Stop H-out, V-out and to		V4			1
	activate	BLKout (OFF mode when V4 < VOFF)
	(Pin 4)
VSCinh	Supply	Voltage to Stop H-out, V-out when		TBD	7.5

VCC < VSCinh (Pin 18)

Note : If H-drive is taken on Pin 20	(Pin 21 connected to supply), H-D is the ratio of low level duration t o horizontal period.
If H-drive is taken on Pin 21	(Pin 20 grounded), H-D is the ratio of high level duration to horizontal period.

In both cases, H-D period driving horizontal scanning transistor off.

V ppm

%

%

%

V

V

V mA

V

V

V

V

	V	06.TBL
		9105A-

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TDA9105A

VERTICAL SECTION

Operating Conditions

Symbol	Parameter	Min.	Typ. Max.	Unit
VSVR	Vertical Sync Input Voltage (Pin 34)	0	5.5	V
VEWM	Maximum EW Output Voltage (Pin 37)		6.5	V
VDHPCM	Maximum Dynamic Horizontal Phase Control Output Voltage (Pin 40)		6.5	V
VDHPCm	Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40)	0.9		V
VDFm	Minimum Vertical Dynamic Focus Output Voltage (Pin 1)	0.9		V
Rload	Minimum Load for less than 1% Vertical Amplitude Drift (Pin 25)	65		MΩ

9105A-07.TBL

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
IBIASP	BiasCurrent (currentsourced by PNPBase)(Pin28)	For V28 = 2V		2		μA
IBIASN	Bias Current (Pins 29-31) (sinked by NPN base)	For V31 = 6V, V29 = 6V		0.5		μA
VSth	Vertical Sync Input Threshold Voltage (Pin 34)	High-level	2			V
		Low-level			0.8	V
VSBI	Vertical Sync Input Bias Current	V34 = 0.8V		1		μA
	(Current Sourced by PNP Base)
VRB	Voltage at Ramp Bottom Point (Pin 27)			2/8		VREF-V
VRT	Voltage at Ramp Top Point (with Sync) (Pin 27)			5/8		VREF-V
VRTF	Voltage at Ramp Top Point (without Sync)			VRT-0.1		V
	(Pin 27)
VSW	Minimum Vertical Sync Pulse Width (Pin 34)		5			μS
VSmDut	Vertical Sync Input Maximum Duty-cycle				15	%
	(Pin 34)
VSTD	Vertical Sawtooth Discharge Time Duration	With 150nF cap		70		μS
	(Pin 27)
VFRF	Vertical Free Running Frequency	V28 = 2V, V29 grounded,		100		Hz
		Measured on Pin 27
		Cosc (Pin27) = 150nF
ASFR	AUTO-SYNC Frequency (see Note 1)	With C27 = 150nF	50		185	Hz
RAFD	Ramp Amplitude Drift Versus Frequency	V31 = 6V, C27 = 150nF		100		ppm/Hz
		50Hz < f < 185Hz
Rlin	Ramp Linearity on Pin 30	V28, V29 grounded		0.5		%
Vpos	Vertical Position Adjustment Voltage (Pin 32)	V33 = 2V		3.2	3.3	V
		V33 = 4V		3.5		V
		V33 = 6V	3.65	3.8		V
IVPOS	Max Current on Vertical Position Control Output			±2		mA
	(Pin 32)
VOR	Vertical Output Voltage (Pin 30)	V31 = 2V		2	2.2	V
	(peak-to-peak voltage on Pin 30)	V31 = 4V		3		V
		V31 = 6V	3.75	4		V
VOUTDC	DC Voltage on Vertical Output (Pin30)	See Note 2		7/16		VREF-V
V0I	Vertical Output Maximum Current (Pin 30)			±5		mA
dVS	Max Vertical S-Correction Amplitude	V/V30pp at T/4		-4	TBD	%
	V28 = 2V inhibits S-CORR
	V28 = 6V gives maximum S-CORR	V/V30pp at 3T/4	TBD	+4		%
Ccorr	Max Vertical C-Correction Amplitude	V29 = 2V		-1.6	TBD	%
		V29 = 4V		0		%
		V29 = 6V	TBD	1.6		%
VFly Th	Vertical Flyback Threshold (Pin 36)			1	TBD	V
VFly Inh	Inhibition of Vertical Flyback Input (Pin 36)	See Note 1		VREF- 0.5		V
IBIAS DCIN	Bias Current (Pin 35) (sourced by PNP base)	For V35 = V32		2		μA

Notes : 1. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude.

2. Typically 3.5V for Vertical reference voltage typical value (8V).

9105A-08.TBL

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TDA9105A

VERTICAL SECTION (continued)

East/West Function

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

EWDC	DC Output Voltage (see Figure 2)	V33 = 4V, V35 = V32,	2.5	V
		V38 = 4V, V23 = 4V
TDEWDC	DC Output Voltage Thermal Drift	See Note 2	100	ppm/°C
EWpara	Parabola Amplitude	V28 = 2V, V29 grounded,
		V31 = 6V, V33 = 4V,
		V35 = V32, V38 = 4V, V23 = 4V	TBD 1.70	V
		V39 = 6V
		V39 = 2V	0	V
EWtrack	Parabola Amplitude versus V-AMP	V28 = 2V, V29 grounded
	Control (tracking between V-AMP	V33 = 4V, V35 = V32
	and E/W)	V38 = 4V, V39 = 6V, V23 = 4V
		V31 = 2V	0.45	V
		V31 = 4V	1.0	V
		V31 = 6V	1.7	V
Keytrack	Keystone versus V-POS control	V23 = 4V, V28 = 2V, V29 grounded,
	(tracking between V-POS and EW)	V31 = 6V, V38 = 4V, V39 = 6V
	A/B Ratio	V33 = 2V, V35 = V32	0.54
	B/A Ratio	V33 = 6V, V35 = V32	0.54
KeyAmp	Keystone Amplitude Adjustment	V23 = 4V, V31 = 6V, V39 = 2V
		V38 = 4V	0	V
		V38 = 2V	1.3	V
		V38 = 6V	1.3	V

Notes : 1. When Pin 36 > VREF - 0.5V, Vfly input is inhibited and vertical blanking on composite blanking output is replaced by vertical sawtooth discharge time.

2.These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.

9105A-09.TBL

Dynamic Horizontal Phase Control Function

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
DHPCDC	DC Ouput Voltage (see Figure 3)	V33 = 4V, V35 = V32, V41 = 4V		4		V
TDDHPCDC	DC Output Voltage Thermal Drift	See Note		100		ppm/°C
SPBpara	Side Pin Balance Parabola Amplitude	V28 = 2V, V29 grounded,
	(see Figure 3)	V31 = 6V, V33 = 4V,
		V35 = V32, V41 = 4V	TBD	+1.45		V
		V42 = 6V
		V42 = 2V		- 1.45	TBD	V
SPBtrack	Side Pin balance Parabola Amplitude	V28 = 2V, V29 grounded,
	versus V-amp Control (tracking	V33 = 4V, V35 = V32,
	between V-amp and SPB )	V41 = 4V, V42 = 6V
		V31 = 2V		0.36		V
		V31 = 4V		0.82		V
		V31 = 6V		1.45		V
ParAdj	Parallelogram Adjustment Capability	V28 = 2V, V29 grounded,
		V31 = 6V, V33 = 4V,
		V35 = V32, V42 = 6V	TBD	0.12
	A/B ratio (see Figure.3)	V41 = 6V
	B/A ratio	V41 = 2V	TBD	0.12
Partrack	Parallelogram versus V-pos Control	V28 = 2V, V29 grounded,
	(tracking between V-pos and DHPC)	V31 = 6V, V41 = 4V, V42 = 6V
	A/B ratio	V33 = 2V, V35 = V32,		0.53
	B/A ratio	V33 = 6V, V35 = V32		0.53

9105A-10.TBL

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TDA9105A

VERTICAL SECTION (continued)

Vertical Dynamic Focus Function

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
VDFDC	DC Output Voltage (see Figure 4)	V33 = 4V, V35 = V32		6		V
TDVDFDC	DC Output Voltage Thermal Drift	See Note		100		ppm/C
VDFAMP	Parabola Amplitude versus V-amp	V28 = 2V, V29 grounded,
	(tracking between V-amp and VDF)	V33 = 4V, V35 = V32,
	(see Figure 4)	V31 = 2V	-0.84	-0.72	-0.6	V
		V31 = 4V	-1.78	-1.57	-1.36	V
		V31 = 6V	-3.14	-2.85	-2.56	V
VDFKEY	Parabola Assymetry versus V-pos	V28 = 2V, V29 grounded,
	Control (tracking between V-pos	V31 = 6V,
	and VDF)	V33 = 2V, V35 = V32,	0.42	0.54	0.64
	A/B ratio
	B/A ratio	V33 = 6V, V35 = V32	0.42	0.54	0.64
Corner	Corner Amplitude Adjustment	V31 = 4V, V38 = 4V, V39 = 2V
Amplitude		V23 = 2V		0.55		VPP
		V23 = 4V		0		VPP
		V23 = 6V		0.55		VPP
	Tracking Corner with V-amp	V23 = 6V
		V31 = 2V		0.2		VPP
		V31 = 4V		0.55		VPP
		V31 = 6V		1.7		VPP

Note : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.

9105A-11.TBL

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10/31

F1μ

10nF

4.7μF

680pF1%

0.1%6.49kΩ

47nF

47nF

22nF

10kΩ

1kΩ

1.8k Ω

VCC

VCC

15

12

10

11

8

9

5

3

2

16

4

21

20

7

2.2μF

V-REF

PHASE

PHASE

PHASE

PULSE

H

6

FREQUENCY

VCO

OUTPUT

COMP

SHIFTER

SHAPER

COMP

BUFFER

PULSE

LOCK

VIDEO UNLOCK

SAFETY

SHAPER

17

UNLOCK

VS

PROCESSOR

POL

IDENT

DETECT

X2

14

PLL1

INHIB

13

X2

220nF

26

2.2μF

V-REF

V-MID

24

PULSE

VERT OSC

BLK

S

SHAPER

34

RAMP

H-FLY

GEN

POL

CORR

DETECT

GENERATOR

V-SYNC

TDA9105A

28

29

27

25

31

30

33

32

36

22

35

18

150nF

470nF

2.2μF

1%

1%

10kΩ

12V

VCC

VCC

Testing : 1 Figure	TDA9105A
Circuit

23 CORNER

19

1

10kΩ

38

37

10kΩ

39

41

40

10kΩ

42

100nF

9105A-03.EPS