SGS-THOMSON TDA1771 Technical data

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						TDA1771
.RAMP GENERATOR		VERTICAL DEFLECTION CIRCUIT
.INDEPENDENT AMPLITUDE ADJUSTEMENT
.BUFFER STAGE
.POWER AMPLIFIER
.FLYBACK GENERATOR
.INTERNAL REFERENCE VOLTAGE
.THERMAL PROTECTION					SIP10
					(Plastic Package)
					ORDER CODE : TDA1771
			PIN CONNECTIONS (top view)
					10	FLYBACK GENERATOR
					9	VS
					8	INVERTING INPUT
DESCRIPTION					7	BUFFER OUTPUT
The TDA1771 is a monolithic integrated circuit in					6	RAMP GENERATOR
					5	GROUND
SIP10 package.					4	HEIGHT ADJUSTMENT
It is a full performance and very efficient vertical					3	TRIGGER INPUT
deflection circuit intended for direct drive of a TV					2	OUTPUT STAGE V S	01.EPS
picture tube in Color and B & W television as well					1	POWER OUTPUT
							1771-
as in Monitor and Data displays.
BLOCK DIAGRAM
		9			2
		VOLTAGE			FLYBACK	10
		REGULATOR			GENERATOR
				R3
TRIGGER IN	3	RAMP		CLOCK	POWER	1
		GENERATOR		PULSE	AMP.
		BUFFER			THERMAL
		STAGE			PROTECTION
	4	6	7	8	5		02.EPS-1771
September 1993						1/4

TDA1771

ABSOLUTE MAXIMUM RATINGS

	Symbol	Parameter	Value	Unit
	VS	Supply Voltage	30	V
	V1 , V2	Flyback Peak Voltage	65	V
	V3	Trigger Input Voltage	20	V
	V8	Amplifier Input Voltage	GND to VS	V
	I0	Output Peak to Peak Current (non repetitive t = 2ms)	6	A
	I0	Output Peak to Peak Current t > 10μs	4	A
	I10	Pin 10 DC Current at V1 < V9	100	mA
	I10	Pin 10 Peak to Peak Current @ tfly < 1.5ms	3	A	01.TBL-
	Ptot	Total Power Dissipation @ Ttab = 60°C	9	W
	TS, TJ	Storage and Junction Temperature	– 40, + 150	°C	1771

THERMAL DATA

	Symbol	Parameter		Value	Unit
						02.TBL-
	Rth (j-tab)	Thermal Resistance Junction-tab	Max.	10	°C/W
	Rth (j-a)	Thermal Resistance Junction-ambient	Max.	70	°C/W	1771

ELECTRICAL CHARACTERISTICS (Tamb = 25°C unless otherwise specified)

Symbol				Parameter	Test Conditions	Min.	Typ.	Max.	Unit
DC (VS = 30V)
I2		Pin 2 Quiescent Current			I1 = 0, I10 = 0		16	36	mA
I9		Pin 9 Quiescent Current			I1 = 0, I10 = 0		15	30	mA
– I6		Ramp Generator Bias Current			V6 = 0			0.5	μA
– I6		Ramp Generator Current			V6 = 0, – I4 = 20μA	18.5	20	21.5	μA
dI6/I6		Ramp Gener. Linearity			V6 = 0 to 15V, – I4 = 20μA		0.2	1	%
V1		Quiescent Output Voltage			Ra = 30kΩ, Rb = 10kΩ, VS = 30V	17.0	17.8	18.6	V
					Ra = 6.8kΩ, Rb = 10kΩ, VS = 15V	7.2	7.5	7.8	V
V1L		Out Saturation Voltage to GND			I1 = 0.5A		0.5	1	V
					I1 = 1.2A		1	1.4	V
V1H		Out Saturation Voltage to VS			– I1 = 0.5A		1.1	1.6	V
					– I1 = 1.2A		1.6	2.2	V
V4		Reference Voltage			– I4 = 20μA	6.3	6.6	6.9	V
dV4/VS		Reference Voltage Drift Versus VS			VS = 10V to 30V		1	2	mV/V
dV4/dI 4		Reference Voltage Drift Versus I4			I4 = 10μA to 30μA		1.5	2	mV/μA
Vr		Internal Ref. Voltage				4.26	4.40	4.54	V
Gv		Ouput Stage Open Loop Gain			f = 100Hz		60		dB
Vfs		V9 – 10 Saturation Voltage			– I10 = 1.2A		1.5	2.5	V
V10		Pin 10 Scanning Voltage			I10 = 20mA		1.7	3	V
V3		Trigger Input Threshold			(see note 1)	2.6	3.0	3.4	V	1171-03.TBL
I3		Trigger Input Bias Current			VIN = V3 – 0.2V			30	μA
t3		Trigger Input Width			(see note 2)	20	60	th	μS
Notes : 1. The trigger input circuit can accept, with a metal option, positive and negative going input pulses.
2.	th =		1.2 × tS	where tS is the vertical period and VPP is ramp amplitude at Pin 6
			VPP

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