SGS-THOMSON M494 Technical data

查询M494供应商

SINGLE-CHIPVOLTAGE TUNING SYSTEM WITH

4 ANALOGCONTROLS AND µP INTERFACE

.

NON-VOLATILE MEMORY FOR 20 PRO­GRAMWORDS (17 BIT x 20)

- TUNINGVOLTAGE12BITS

- BAND2 BITS

- MULTI STANDARD 2 BITS

- PROGRAMSKIP BIT 1 BIT

- 10,000MODIFY CYCLESPER WORD

- MIN.10 YEARSDATARETENTION

.

13 BITVOLTAGESYNTHESIZER(BRM + PWM)

.

NV MEMORY FOR 4 ANALOG CONTROLS
(6 BITx 4)

.

4 BANDSWITCH OUTPUTS
(VHF I & III, UHF, CATV)

.

5 x 7 KEYBOARD

.

2 AUDIOVISUAL OUTPUTS (VCR& PC)

.

2 CODED MULTI STANDARD OUTPUTS
(e.g. PAL, SECAM, NTSC etc.)

.

DIRECT 11/2 DIGIT 7 SEGMENT COMMON
ANODE LED DISPLAYDRIVING

.

PCMREMOTE CONTROL RECEIVER
(M708 transmitter)

.

5-BIT DATA INPUT + CONTROL LINE FOR
P INTERFACE

.

LINEARAFC DEFEATOUTPUT

.

FLYBACK/SYNC.COINCIDENCE INPUTFOR
SEMI-AUTOMATICSEARCH

.

STANDBY OUTPUT

.

OPTIONSELECT : 16 OR 20 PROGRAMS

.

POWERUP MODE

.

PROGRAMSKIP DEFEAT

.

AVOPTIONS

.

1 * OR DECADE MODE OPTION IN 20 PRO­GRAM OPTION

.

TEMPORARY ANALOG UP/DOWN INDICA­TOR ON LED DISPLAY

.

BANDSKIP OPTION

.

455 TO 510kHz CHEAP CERAMIC RESONATOR

.

VDD=5V ±5%. VPP= 25V ± 1V

M494

pable of including a floatinggate NV memorycell
(EEPROM).

The i.c. has been designed as a complete digital
TV tuning system based on the voltage synthesis
principleand as a replacementfor all the conven­tional potentiometers and band switches particu­larly in low cost TV sets. It also provides some
functionsnormallyonlyassociatedwithhighercost
sets.NV memoryis integratedonthe chip together
withallthenecessarycontrolcircuitrytoprovidethe
program memory. Separate NV memory is also
integrated to provide the memory for four analog
controls. A seven segment LED display can be
directly driven by the chip to display the program
selected, and the direction of movement of the
analog controls. Provision is made for a remote
control receiver both on and off chip, the latter is
interfacedvia a data input and single controlline.
(Thisenablescontrol by a microprocessor).Alocal
keyboardcan be used with the device in avariety
of configurations.An optionselect pinprovides for
different program number options, power up op­tionsand skip associated functions. This device is
anothersignificantstep towards the completeinte­gration of TV control circuitry.

The device is packaged in a 40 pin DIL plastic
package.

DIP40

(Plastic Package)

DESCRIPTION

The M494 is a monolithic LSI integrated circuit
fabricatedinSGS-THOMSON’sEPM2process; an
N-channel, Planox, doublepoly MOS process ca-

June 1991

ORDER CODE : M494B1

1/22

M494

PINCONNECTIONS

OPTION SELECT

DISPLAY DRIVE

h+i

V

AV0
AV1

V

MEMORYTIMING

1

D4

2

D3

3

D2

4

D1

5

D0

6
7
8
9

g

10

f

11

e

12

SS

13

d

14

c

15

b

16

a

17
18
19

PP

20

DATA HANDSHAKE

40

V

39

DD

STANDBY

38

AFC DEFEAT

37

FB/SYNC COINCIDENCE

36

REMOTECONTROL

35

VOLUME

34

SATURATION

33

TEST 1

32

BRIGHTNESS

31

MS0

30

MS1

29

CONTRAST

28

TUNING

27

OSC. OUT

26

OSC. IN

25

VHF 1

24

VHF 3

23

CATV

22

UHF

21

ABSOLUTEMAXIMUM RATINGS

Symbol Parameter Value Unit

V

DD

V

PP

V

V

O(off)

I

OL

t

PD

P

tot

T

stg

T

op

C

os

R

os

C

dk

R

k

C

rts

Stresses above those under ”Absolute Maximum Ratings” may causes permanent damage to the device. This is a stress rating only and
functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periodsmay affect device reliability.

Supply Voltage – 0.3 to 7 V
Memory Supply Voltage – 0.3 to 26 V
Input Voltage – 0.3 to 15 V

I

Off State Input Voltage 15 V
Output Low Current

LED Driver Outputs : pin a-g

pin h + i

All other Outputs

20
35

5
Max. Delaybetween Memory Timing & Memory Supply Pulses 5 µs
Total Package Power Dissipation 1 W
Storage Temperature – 25 to + 125 °C
Operating Temperature 0 to + 70 °C
Capacitance on OptionSelect Pin 100 pF
Resistance on Option Select Pin 1 kΩ
Capacitance on data outputs & keyboard inputs when lines are

150 pF

connected by a keyboard switch closure
Series Resistance of Single Keyboard Switch 10 kΩ
Capacitance on Data Handshake Pin 50 pF

mA
mA
mA

494-01.EPS

494-01.TBL

2/22

M494

STATICELECTRICAL CHARACTERISTICS (T

Pins Symbol Parameter Test Conditions Min. Typ. Max. Unit

Memory Supply I

Memory Timing V

I

O(off)

Tuning V
V

DD

I
RC V
FB/sync. Coin. Input V

V

Vol. Brigh. Sat.
Contr. DACs

V

I

O(off)

h+i V

V

V

D0, D1
D2, D3
D4

V

V

V

I

O(off)

MS0, MS1 AFC
def. AV0, AV1

V

I

O(off)

Option Select V

V

Standby V

a, b, c, d, e, f, g V

V

V

Display Drive V

I

O(off)

UHF, III, I, CATV V

V

V

V

I

O(off)

Data
Handshake

V
V

V

V

I

O(off)

Memory Supply

PP

Current

R Pull Down 25 kΩ

OL

Leakage VDD= 4.75V, VO= 26V 100 µA

OL

Supply Current VDD= 5.25V 100 mA

DD

pk to pk 0.5 13.2 V

I
IL
IH

I

IL

R Pull up 30 kΩ

OL

IL
IH

I

IL

R Pull up 200 kΩ

OH

IL
IH

I

IL
OL

R Pull up 30 KΩ

OL

IL
IH

I

IL

R Pull up 30 kΩ

OL

I

O

IL
IH

I

IL

R Pull up 200 kΩ

OL
OL

OL
OH

IL
IH

OL
OH

IL
IH

I

IL

R Pull up 30 kΩ

=0to70°C, VDD= 5V unless otherwisespecified)

amb

VPP= 25V Write Peak

Write Average
Erase Peak
Erase Average
Read Peak
Read Average

VDD= 4.75V, IOL= 2.5mA 8 V

VDD= 4.75V, IOL= 5mA 1 V

2.0 V

VDD= 5.25V, VIL= 0.8V – 0.4 mA

VDD= 4.75V, IOL= 4mA 1 V
VDD= 5.25V, VO= 13.2V 50 µA

3.5 V

VDD= 5.25V, VIL= 1.5V – 50 µA

VDD= 4.75V, IOL= 30mA 1.5 V

3.5 V
VDD= 5.25V, VIL= 1.5V – 0.4 mA
VDD= 4.75V, IOL= 1mA 0.4 V
V

= 5.5V 25 µA

O(off)

VDD= 4.75V, IOL= 1mA 0.4 V
VDD= 5.25V, VO13.2V 50 µA

3.5 V
VDD= 5.25V, VIL= 1.5V – 0.4 mA

VDD= 4.75V, IOL= 100µA 0.4 V
VDD= 4.75V, VO= 0.7V 1.6 mA

3.5 V
VDD= 5.25V, VIL= 1.5V – 50 µA

VDD= 4.75V, IOL= 15mA 1.5 V
VDD= 4.75V, IOL= 5mA 0.4 V
VDD= 5.25V, VO= 13.2V 50 µA
VDD= 4.75V, IOL= 1mA 3 V
VDD= 4.75V, IOH= – 150µA 2.4 V

3.5 V
VDD= 5.25V, VO= 13.2V 50 µA
VDD= 4.75V, IOL= 1mA 3 V
VDD= 4.75V, IOH= 150µA 2.4 V

3.5 V
VDD= 5.25V, VIL= 1.5V – 0.4 mA

VDD= 5.25V, VO= 13.2V 50 µA

35

mA

10

mA

9

mA

5

mA

8

mA

2.5

mA

0.8 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

494-02.TBL

3/22

M494

DEFINITIONOF TERMS

The M494 has four conditions or statesthat it can
be in which are defined below. Logic LO 0V and
logic HI = 5V.

PoweredDown

V

=0V.VPP=0V

DD

On

=5V.VPP=25V.

V

DD

Devicedriving display normally.
Data Handshake pinconfigured as RTSi/p.
Standby o/p = HI. All other functions operating
normally.

Standby

=5V.VPP=0V.

V

DD

Device driving display to show a singlestatic bar
(g segment).

FUNCTIONAL DESCRIPTION (clock frequency = 500kHz)
V

DD&VSS

VDD=+5V± 5%.Whenapplied,an internalpower
onresetof110msisgenerated.Thevoltagethresh­old for the reset is in the range 3 to 3.5V but is in
fact the point at which the internal clock phases
start.

V

=0V.This pin is connectedto the substrate of

SS

the i.c. and is the reference for all parameters of
the device.

Oscillator I/O

The frequencyof the oscillator should be between
445 and 510kHz using a cheap ceramicresonator.
The reference frequency of the remote control
transmitter must also be in the same range i.e. if
the oscillator frequency is 455kHz then the trans­mitter frequencycouldbe 510kHzor viceversa.

Test

Thispinis normallyusedforpost fabricationtesting
purposesonly andshould betied to V

. However

SS

this pin can be used by SGS-THOMSON or the
OEM to enable external loading of the memory.
Details of how to achieve this can be furnishedby
SGS-THOMSON.

DataHandshakepinconfiguredasRTS i/p.Stanby
o/p =LO.
All keyboard commands are disabled except any
programcommand On/Off, On/Stanby.
Memory sequence up or down, 1 * and ±10 (dec­ade) commands.
Analog controls. Tuning, AV, MS and AFC defeat
o/p’s = LO. Band o/p’s= HI (externallypulled up).
See Standby section for more detail.

Off

V

DD

Data Handshakepin configuredas OFF o/p.
Standby o/p = LO. Display disabled and Display
driveo/p = HI (externallypulled up).
All keyboard commandsdisabled except ON/OFF.
Remoteand data command sources disabled.
Analog controls, Tuning, AV, MS and AFC defeat
o/p’s = HI (externallypulled up).

The signal from the preamplifier (TDA8160) is
broughtto the RC signal input via an AC coupling
network(seeFigure 1).

Figure1

The input is self biased to approx. 1.5V. When a
largesignal is applied to the input a levelshift will
take place predominantlydue to the coupling net­work.

Howeveranother time constantis alsovisible due
to the coupling C and the internal resistorR
Figures. 2 & 3).

Figure2

=5V.VPP= 0V. Device not driving display.

VDD(TDA8160) R C

5V 2.2kΩ 4.7nF

12V 10kΩ 4.7nF

TDA8160

RC

M494

. (see

i

V

DD

494-02.EPS

Remote ControlInput

The integratedRCreceiver decodessignalstrans­mitted by the M708 (address 10). The minimum
signal amplitude should be 0.5V peak to peak at
the input pin. The minimum pulse width should be
8µs.

4/22

1.5V

Ri

to Cct

Remote
ControlI/P

494-03.EPS

FUNCTIONAL DESCRIPTION (continued)
Figure 3

τ

=RC

1

τ

=Ri.C

2

1.5V

Severaltests are performedon the signal :
a) Measurement of the pulse distance T (time

base synchronization).

b) Check of the bit positions relative to the time

basewindows.
c) Checkof theparity bit.
d) Check oftheabsenceof pulsesbetweenparity

and stop pulses.
e) Check of the noise level. The receiver checks

the noise level for a time T after each pulse

detected.
If all these tests are successful the received word

is stored and decoded. If not it is rejected. The
transmissionis terminatedon receptionof the end
of transmission (EOT) code or if the internal timer
measuresatransmission interruptionof morethan
550ms. For more detail concerning the operation
of theRC receiver refer toSGS-THOMSON Tech­nical Note No. 155 pp11-12.

The RC receiverand the local keyboardhave the
same command source priority i.e. a local com­mand is not accepted until a previously accepted
RC commandhas been completelyexecuted and
the EOTcode transmitted. Similarly if alocalcom­mand isunder executionthenan RCcommandwill
not be accepted. The RC truth table and com­mandsare shownon the next page.

Analog Control Outputs

Four analog control outputs are implemented to
provide for Volume, Brightness, Saturation and
Contrast from four 6 bit D/A’s. TheseD/A’suse the
Pulse Width Modulation technique to synthesize a
pulse trainof constantfrequencybut variablepulse
width (PWM). Each output delivers a 7.8kHz
square wave whose duty cycle is variable in 63
steps. External RC filtering and level shifting is
required to realise a static DC voltage from the
pulse train. If the analog outputs are continuously
varied by command from the keyboard or data
commandsourcesthe outputswill change approx.
every 112ms (fck = 500kHz) or approx. every
102ms if the command is issued from the RC
command source. One analog control is specifi-

callydesignedasa volumecontrolas mutecircuitry
isbuilt in.

On start up resetthe analogcontrol outputs except
volume are enabled after a period of approx.

1.1 seconds. In the Standbyand Off statesall the
analogcontrol outputs arepulled to logicLO.

The normalise command reads the contents of
each analog memory sequentially to its corre-

494-04.EPS

spondingcounter and D/Aoutput.

Tuning Output

The tuning voltage is generated from a 13 bit
counter.Theprogrammemorystoresthe 12MSB’s
of the tuning word. The range of the AFC circuitry
is at least 3 bits so the LSB of the tuning counter
doesnot affectthe resolutionof tuning.

Thecontents of the counterare convertedusing a
PWM and a Bit Rate Multiplier (BRM) technique.
13 bits gives 8192 steps which yields a resolution
ofapproximately3.9mVwith a max. tuning voltage
of 32V. This corresponds to a resolution of about
75kHzin the UHF band. The 5 MSB’sof thetuning
word areconverted using PWM and the remaining
8 bits using BRM. Thus as the tuning word in­creasesfromall zeroesthenumberof pulsesinone
period increases to 256 with all the pulses being
the same length (t

=2µs). Forvalues larger then

o

256 PWM conversiontakes placewhere the num­ber of pulses in one period stays constant at 256
but the width changes.

Whenthepulsewidth reaches15t

twosuccessive

o

pulses ”link” together and the number of pulses
decreases(see Figure 4).

Thepulse trainis fed toan externallow pass filter
to realise a DC voltage. The temperaturedepend­ence of thissystem is predominantlythe switching
times of the output pulses and asthere are only a
maximumof256 pulsesin oneperiodthetempera­turestability is very good.

InStandbyand Offstatesthetuningoutputispulled
to logic LO.

Figure4

No OF PULSES

256

TUNING

1V 31V

VOLTAGE

M494

494-05.EPS

5/22

M494

FUNCTIONAL DESCRIPTION (continued)
Table1 : RemoteControl Commands(address 10, code =1010)

Command

Number

0
1
2
3
4
5
6

7
8

9
10
11
12

13
14
15
16
17
18

19
20
21
22
23
24

25
26
27
29
28
30

The above table showns the differencebetween the 16 and 20 program optionswith respect to the remote control commands. Commands 16,
17, 18 &21 change function between the two options. Commands 22, 23 & 24 should not be used in the 20 program option, as theyhave no
function.
NOP = No operation

16 Programs 20 Programs C1 C2 C3 C4 C5 C6

EOT
Standby
Mute (toggle)
Program 1
Program 2
Program 3
Program 4

Contrast up
Contrast down
Program 5
Program 6
Program 7
Program 8

Memory Seq. up
Memory Seq. down
Program 9
Program 10
Program 11
Program 12

Normalise
On/stby (tog.)
Program 13
Program 14
Program 15
Program 16

Volume up
Volume down
Brightness up
Brightness down
Saturation up
Saturation down

Function Code

EOT
Standby
Mute (toggle)
Program 1
Program 2
Program 3
Program 4

Contrast up
Contrast down
Program 5
Program 6
Program 7
Program 8

Memory Seq. up
Memory Seq. down
Program 9
Program 0
– 10 (decade)
+ 10 (decade)

Normalise
On/stby (tog.)
1*
NOP
NOP
NOP

Volume up
Volume down
Brightness up
Brightness down
Saturation up
Saturation down

0
1
1
0
1
0
1

1
1
0
1
0
1

1
1
0
1
0
1

1
1
0
1
0
1

1
1
0
0
1
1

0
0
1
0
0
1
1

0
1
0
0
1
1

0
1
0
0
1
1

0
1
0
0
1
1

0
1
0
1
0
1

0
0
0
1
1
1
1

0
0
1
1
1
1

0
0
1
1
1
1

0
0
1
1
1
1

0
0
1
1
1
1

0
0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

1
1
1
1
1
1

0
0
0
0
0
0
0

1
1
1
1
1
1

0
0
0
0
0
0

1
1
1
1
1
1

1
1
1
1
1
1

0
0
0
0
0
0
0

0
0
0
0
0
0

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

Program Memory

NV memory(EEPROM)is integratedon thechipto
provide storage for up to20 stations.
Each memorylocationis 17 bits inlengthproviding
12 bits fortuning voltage,2 bits for band, 2 bits for
two coded multi-standard outputs and 1 bit pro­gram skipflag.
Individualprogramwordscanbe readoncommand
from the keyboard, remote or data command
sources but can only be written oncommandfrom
the keyboard.
There are twomethods for storing a program(writ­ing the memory): pre and post tuning selectionof
the programnumber. See Commands, section7.
Readingeach memory locationin sequence(up or
down) can also beachievedfromall thecommand
sources.

All memory timing functionsare provided on chip
and only one external transistor is required to
switch the external memory supply (25V).

6/22

Thereare essentiallytwo operationscarriedouton
the memory: Write/Modifyand Read.
The Write/Modifycycle consistsof 3 steps :

a) All ”1s” are written to thebits of theaddressed

word.
b) All bits of the word are erased.
c) The new contents are written.

Usingthismethodallthebitsof theaddressedword
are aged thesame.Formore detail concerningthe
write, erase and read current waveforms at the
Memory Supplypin seeM491 datasheet.

MemoryFor Analog Controls

The memory for the analog controls is electrically
identicaltothemain programmemory butis organ­ised as four 6-bit words located in two sequentially
addressed words at the memory. Each word cor­responds to the Volume, Brightness, Saturation
and Contrast outputs. At power on reset and nor­malise commandeachmemory word is readout to
its corresponding counterand D/Ain sequence.

FUNCTIONAL DESCRIPTION (continued)
Display,Keyboard and Data Multiplexing

Logic is integrated on the chip to provide the mul­tiplexing between the display, keyboard and data
inputs. In the On state and with the Data Hand­shake pin at logic HI as an input the display and
keyboardare muxed together.See Figure 5. Each
column output goes to logicLO in sequence and
the row inputs are scanned for a key closure. In
chronological order across the total mux. period
there is : initialisation, scan, decision and display
periods.

The Data Handshake pin has a complex logical
function. It hastwo modesof operation: as a hand
shake I/O line to a µP and as an output line to the
P to signalthat theM494is in theOff state.In order
to achieve this function careful signal timing is
required both internally and externallyto the chip.
See Figure6. Whenthe deviceis in the OFFstate
the Data Handshake pin is used to signal this
condition to theµP by being pulled LO.

Figure 6 : Data-input-timing

Figure5

D0

D1

D2

D3

D4

DISPLAY
DRIVE

( 2ms)

INITIALIZE

MUX PERIOD (8ms)

640µs

SCAN

DECISION

M494

DISPLAY

494-06.EPS

A1 B1 C1 D1 A2 B2 C2 D2 A3

DATA
HANDSHAKE

D0 - D4

EOE
(END OF TRANSMISSION)

DATA HANDSHAKE

NOT TO SCALE

PIN CONFIGURATION

N° Symbol Parameter Min. Typ. Max. Unit

1t

RTS

2t

CTS

3t

O/P

4t

HS

5t
6t
7t
8t

Note : Oscillator Clock = 500kHz

S
H

J

CR

t

CR

t

O/P

t

RTS

t

j

t

CTS

DATA DATA

t

t

HS

t

t

S

CTS

H

t

CR

t

O/P

K/B AND RC I/P
DISABLEDTILL
EOT EXECYTION

(EOT = END OF

O/II/OO/II/O

TRANSMISSION)

Request to Send Pulse (RTS) 5 10 µs
Clear to Send (CTS) 512 µs
Pin Output Configuration 8 ms
Handshake Time 12 µs
Data Set up Time 10 128 µs
Data Hold Time 128 256 µs
Synchronization Jitter 8 ms
CTS tonext RTS Pulse 98 ms

494-07.EPS - 494-03.TBL

7/22