TATIVESTANDARDN°13A,”STANDARDSPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
HCC/HCF4034B
INPUT/OUTPUT BUS REGISTER
EY
(Plastic Package)
HCC4034BFHCF4034BEY
PIN CO N NECTIONS
(Ceramic Frit Seal Package)
M1
(MicroPackage)
ORDER CODES :
HCF4034BM1
F
DESCRIPTION
TheHCC4034B(extended temperature range) and
HCF4034B (intermediate temperature range) are
monolithic integrated circuits, available in 24-lead
dual in-line plastic or ceramic package and plastic
micro package. The HCC/HCF4034B is a static
eight-stage parallel-or serial-input parallel-output
register. Itcan be used to : 1) bidirectionally transfer
parallel information between two buses ; 2) convert
serial data to parallel form and direct the parallel
datatoeitheroftwobuses ;3)store(recirculate)paralleldata,or4)acceptparallel datafromeitheroftwo
buses and convert that data to serial form. Inputs
that control the operations include a single-phase
CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS(A/S), A-BUS-TOB-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/
SERIAL (P/S). Data inputs include 16 bidirectional
parallel data lines of whichtheeightAdata linesare
inputs(3-stateoutputs) and the Bdatalinesare outputs (inputs) depending on the signal level on the
A/B input.In addition, an input for SERIAL DATAis
alsoprovided. AllregisterstagesareD-typemasterslaveflip-flops withseparatemasterandslaveclock
June 1989
1/16
HCC/HCF4034B
inputs generated internally toallowsynchronous or
asynchronous data transfer from master to slave.
Isolationfrom externalnoise andthe effectsofloading isprovidedby outputbuffering.
PARALLELOPERATION – A high P/S input signal
allowsdata transfer intothe register via theparallel
data lines synchronously with thepositive transition
of the clockprovided the A/S input islow. If the A/S
inputishigh thetransfer is independent oftheclock.
The direction of data flow is controlled by the A/B
input. When this signal ishigh the A data lines are
inputs (andB data linesare outputs); alowA/Bsignal reverses thedirection ofdata flow.The AE-input
is an additional feature which allowsmanyregisters
tofeeddatatoacommonbus.TheADATAlinesare
FUNCTIONAL DIAGRAM
enabledonly whenthis signal is high. Datastorage
through recirculation of data in each register stage
is accomplished by making theA/B signalhigh and
the AE signallow.
SERIALOPERATION –AlowP/Ssignal allowsserial data to transfer into the register synchronously
withthe positivetransitionoftheclock.TheA/Sinput
isinternally disabledwhenthe register isin theserial
mode (asynchronous serial operation is not
allowed). The serial dataappears asoutputdataon
either the B lines (when A/B is high) or the A lines
(whenA/B islowandtheAEsignal ishigh).Register
expansion can beaccomplished by simply cascading HCC/HCF4034B packages.
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
*Supply Voltage : HCC Types
V
DD
V
Input Voltage– 0.5 to VDD+ 0.5V
i
I
DC Input Current (any one input)± 10mA
I
P
T
T
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device
reliability.
2/16
Total Power Dissipation (per package)
tot
Dissipation per Output Transistor
for T
= Full Package-temperature Range
op
Operating Temperature : HCC Types
op
Storage Temperature– 65 to + 150°C
stg
HCF Types
HCF Types
– 0.5 to + 20
– 0.5 to + 18
200
100
– 55 to + 125
–40to+85
V
V
mW
mW
°C
°C
HCC/HCF4034B
RECOMMENDED OPERATINGCONDITIONS
SymbolParameterValueUnit
V
T
LOGIC DIAGRAMS
STEERING LOGIC
Supply Voltage : HCC Types
DD
HCF Types
V
Input Voltage0 to V
I
Operating Temperature : HCC Types
op
HCF Types
3to18
3to15
DD
– 55 to + 125
–40to+85
V
V
V
°C
°C
3/16
HCC/HCF4034B
LOGIC DIAGRAM AND TRUTH TABLE
REGISTER STAGE (1 of 8 stages)
INPUTSOUT
▲
CL
M
▲ = LEVEL CHANGE
•=INVALID CONDI-
CL
▲
S
DQ
00
00
0•
X0
11
11
1•
FOR REGISTER INPUT-LEVELSAND RESULTING REGISTER OPERATION
”A”
Enable
000XSerial Mode ; Synch. Serial Data Input, ”A” Parallel Data Outputs Disabled
001XSerial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output
0100Parallel Mode ; ”B” Synch. Parallel Data Inputs, ”A” Parallel Data Outputs
0101Parallel Mode ; ”B” Asynch. Parallel Data Inputs, ”A” Parallel Data Outputs
0110Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,
0111Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,
100XSerial Mode ; Synch. Serial Data Input, ”A” Parallel Data Output
101XSerial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output
1100Parallel Mode ; ”B” Synch. Parallel Data Input, ”A” Parallel Data Output
1101Parallel Mode ; ”B” Asynch. Parallel Data Input, ”A” Parallel Data Output
1110Parallel Mode ; ”A” Synch. Parallel Data Input, ”B” Parallel Data Output
1111Parallel Mode ; ”A” Asynch. Parallel Data Input, ”B” Parallel Data Outpu
* Outputs change at positive transition of clock in the serial mode and when the A/S control inputs is ”low” in the parallel
mode.
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
TYPICAL APPLICATIONS
16-BITPARALLEL IN/PARALLEL OUTPARALLEL IN/SERIAL OUT, SERIAL IN/PARALLEL OUT,SERIAL
IN/SERIALOUT REGISTER.
8/16
TYPICAL APPLICATIONS (continued)
16-BITSERIALIN/GATED PARALLEL OUT REGISTER
FREQUENCYAND PHASECOMPARATOR.
HCC/HCF4034B
TIMINGDIAGRAM
9/16
HCC/HCF4034B
TYPICAL APPLICATIONS (continued)
SHIFTRIGHT/SHIFTLEFT WITH PARALLEL INPUTS
A ”High” (”Low”) on the Shift Left/Shift Right input
allowsserial data on the Shift Left Input (Shift Right
Input) to enterthe register onthe positive transition
of the clocksignal. A ”high” onthe ”A” Enable Input
disables the”A” parallel data lines on Reg.1 and 2
and enables the ”A” datalines on registers 3 and4
and allowsparallel dataintoregisters 1and 2. Other
logic schemes may be used in place of registers 3
and 4 forparallel loading. When parallel inputs are
not used Reg. 3 and 4 and associatedlogic arenot
required.
* ShiftLeft input mustbe disabled during parallel
entry.
N-STAGEREGISTER WITH FIXEDSERIAL OUTPUT LINE
10/16
TYPICAL APPLICATIONS (continued)
SAMPLEAND HOLDREGISTER-SERIAL/PARALLEL IN-PARALLEL OUT
SINGLE-AND DOUBLE-BUSSYSTEMS
HCC/HCF4034B
The ”A” enable (AE) and A/B signals control all combinations of transfer between the registers and bus systems.
Information furnished is believed tobe accurate and reliable.However, SGS-THOMSON Microelectronicsassumes no responsability forthe
consequences of useof such information nor for any infringement of patents orother rights of third parties which may results fromits use. No
license isgranted byimplication or otherwiseunder any patentorpatent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to changewithout notice. This publication supersedes andreplaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsinlife support devicesor systems withoutexpress
written approval of SGS-THOMSONMicroelectonics.
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