SGS-THOMSON HCC40192B, HCF40192B, HCC40193B, HCF40193B Technical data

HCC/HCF40192B

HCC/HCF40192B

HCC/HCF40193B

PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) 40192B ± BCD TYPE 40193B ± BINARY TYPE

.INDIVIDUAL CLOCK LINES FOR COUNTING

.UP OR COUNTING DOWN

SYNCHRONOUS HIGH-SPEED CARRY AND BORROW PROPAGATION DELAYS FOR CAS-

.CADING

ASYNCHRONOUS RESET AND PRESET CA-

.PABILITY

MEDIUM-SPEED OPERATION - fCL = 8MHz

.(typ.) @ 10V

STANDARDIZED SYMMETRICAL OUTPUT

.CHARACTERISTICS

.5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C

.FOR HCC DEVICE

.100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDECTENTATIVE STANDARD N°13A, ºSTANDARD SPECIFICATIONS FOR DESCRIPTION OF ºBº SERIES CMOS DEVICESº

EY	F
(Plastic Package)	(Ceramic Frit Seal Package)

M1	C1
(Chip Carrier)	(Plastic Chip Carrier)

ORDER CODES :

HCC401XXBF HCF401XXBM1

HCF401XXBEY HCF401XXBC1

DESCRIPTION	PIN CONNECTIONS
The HCC40192B, HCC40193B, (extended tem-
perature range) and the HCF40192B, HCF40193B
(intermediate temperature range) are monolithic in-
tegrated circuits, available in 16-lead dual in-line
plastic or ceramic package and platic micro pack-
age. The HCC/HCF40192B Presettable BCD
Up/Down Counter and the HCC/HCF40193B Pres-
ettable Binary Up/Down Counter each consist of 4
synchronously clocked, gated ºDº type flip-flops
connected as a counter. The inputs consist of 4 in-
dividual jam lines, a PRESET ENABLE control, in-
dividual CLOCK UP and CLOCK DOWN signals
and a master RESET. Four buffered Q signal out-
puts as well as CARRY and BORROW outputs for
multiple-stage counting schemes are provided. The
counter is cleared so that all outputs are in a low
state by a high on the RESET line. A RESET is ac-
complished asynchronously with the clock. Each
output is individually programmable asynchron-
ously with the clock to the level on the corresponding
jam input when thePRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP line

June 1989

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HCC/HCF40192B/193B

is high. The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the countup mode. The BORROW signal goes low one-half clock cycle after the counter reaches its minimum

FUNCTIONAL DIAGRAM

count in the count-down mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding package.

ABSOLUTE MAXIMUM RATINGS

Symbol

V DD*

Vi

II

Pt o t

T o p

Ts t g

Parameter	Value	Unit
Supply Voltage : HC C Types	± 0.5 to + 20	V
H C F Types	± 0.5 to + 18	V
Input Voltage	± 0.5 to VDD + 0.5	V
DC Input Current (any one input)	± 10	mA
Total Power Dissipation (per package)	200	mW
Dissipation per Output Transistor
for To p = Full Package-temperature Range	100	mW
Operating Temperature : HCC Types	± 55 to + 125	°C
H CF Types	± 40 to + 85	°C
Storage Temperature	± 65 to + 150	°C

Stresses above those listed under ºAbsolute Maximum Ratingsº may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltages are with respect to VSS (GND).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter	Value	Unit
VDD	Supply Voltage : H CC Types	3 to 18	V
	H C F Types	3 to 15	V
VI	Input Voltage	0 to VDD	V
T o p	Operating Temperature : HCC Types	± 55 to + 125	°C
	H CF Types	± 40 to + 85	°C

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HCC/HCF40192B/193B

LOGIC DIAGRAMS

40192B (BCD).

40193B (Binary).

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HCC/HCF40192B/193B

TIMING DIAGRAMS

40192B (BCD).

40193B (Binary).

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HCC/HCF40192B/193B

Internal Logic of Flip-flop.

TRUTH TABLE

Clock		Clock	Preset	Reset	Action
Up		Down	Enable
±/±		1	1	0	Count Up
±\±		1	1	0	No Count
1		±/±	1	0	Count Down
1		±\±	1	0	No Count
X		X	0	0	Preset
X		X	X	1	Reset
1 = High Level	0 = Low Level	X = Don't Care.

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