SERVICE MANUAL AV100 SERVICE MANUAL

SyncMOS Technologies Inc. SM8958A

September 2002

Product List

SM8958AL25, 25MHz 32KB internal flash MCU SM8958AC25, 25MHz 32KB internal flash MCU SM8958AC40, 40MHz 32KB internal flash MCU

Description

The SM8958A series product is an 8 - bit single chip micro controller with 32KB on-chip flash and 1K byte RAM embedded. It is a derivative of the 8052 micro controller family. It has 5-channel SPWM build-in. User can access on-chip expanded RAM with easier and faster way by its ‘bank mapping direct addressing mode’ scheme. With its hardware features and powerful instruction set, it’s straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 I/ O pins for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 32K byte flash memory for program data. To program the on-chip flash memory, a commercial writer is available to do it in parallel programming method.

Ordering Information

yywwv SM8958Aihhk

yy: year, ww:week v: version identifier {, A, B,...} i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table} v: version identifier

T,C

O

AF

Postfix Package P 40L PDIP page 2 page 21 J 44L PLCC page 2 page 22 Q 44L QFP page 2 page 23

Pin/Pad Configuration Dimension

DR

O

D

Preliminary

8 - Bit Micro-controller

with 32KB flash & 1KB RAM embedded

Features

Working voltage: 3.0V ~ 3.6V For L Version

4.5V ~ 5.5V For C Version

General 8052 family compatible 12 clocks per machine cycle 32K byte on chip program flash 1024 byte on-chip data RAM Three 16 bit Timers/Counters One Watch Dog Timer Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package Full duplex serial channel Bit operation instruction Page free jumps 8-bit Unsigned Division 8-bit Unsigned Multiply BCD arithmetic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt

NFIDENT

A serial I/O port Power save modes: Idle mode and Power down mode Code protection function Low EMI (inhibit ALE) Bank mapping direct addressing mode for access on-chip RAM 5 channel SPWM function with P1.3 ~ P1.7

C

T

O

AL

I

PY

NO

Ta iw a n 4F, No. 1 Creation Road 1, Science-based Industrial Park, Hsinchu, Taiwan 30077

TEL: 886-3-578-3344 886-3-579-2988 FAX: 886-3-579-2960

886-3-578-0493

Web site: http://www.syncmos.com.tw

Specifications subject to change without notice,contact your sales representatives for the most recent information.

1/25 Preliminary Ver 0.2 PID 8958A 09/02

Pin Configurations

SPWM2/P1.5 SPWM3/P1.6 SPWM4/P1.7

RES

RXD/P3.0

P4.3

TXD/P3.1 #INT0/P3.2 #INT1/P3.3

T0/P3.4

T1/P3.5

SyncMOS Technologies Inc. SM8958A

Preliminary

September 2002

P0.0/AD0

181716151413

VDD

19

P0.1/AD1

P0.2/AD2

P0.3/AD3

33

P0.4/AD4

32

P0.5/AD5

31

P0.6/AD6

30

P0.7/AD7

29

#EA

28

P4.1

27

ALE

26

#PSEN

25

P2.7/A15

24

P2.6/A14

23

22

2120

P2.5/A13

P1.2

P1.3/SPWM0

P1.4/SPWM1

6

7

8

9

10

11

12

13

14 15 16 17

19

18

P1.1/T2EX

3

5

4

SM8958A

ihhJ

44L PLCC (Top View)

22

20

21

VDD

P0.0/AD0

P4.2

P1.0/T2

144434241 40

2

26

25

23

24

P0.1/AD1

P0.2/AD2

2827

P0.3/AD3

39

38

37

36

35

34

33

32 31

30

29

P0.4/AD4

P0.5/AD5 P0.6/AD6

P0.7/AD7

#EA P4.1

ALE #PSEN

P2.7/A15

P2.6/A14 P2.5/A13

SPWM2/P1.5

SPWM3/P1.6

SPWM4/P1.7

RES

RXD/P3.0

P4.3

TXD/P3.1 #INT0/P3.2 #INT1/P3.3

T0/P3.4 T1/P3.5

P1.3/SPWM0

P1.4/SPWM1

P1.2

44 43 42 41 38 37 36 35 3440 39

1 2

3

4

5

6

7 8

9

10

11

SM8958A ihhQ

44L QFP

(Top View)

12

P4.2

P1.1/T2EX

P1.0/T2

AL

I

T2/P1.0

T2EX/P1.1

P1.2

SPWM0/P1.3

SPWM1/P1.4

SPWM2/P1.5

SPWM3/P1.6

SPWM4/P1.7

RES

RXD/P3.0

TXD/P3.1

#INT0/P3.2

#INT1/P3.3

T0/P3.4

T1/P3.5

#WR/P3.6

#RD/P3.7

XTAL2

XTAL1

VSS

XTAL1

XTAL2

#RD/P3.7

#WR/P3.6

1

2

3

4

5

6

7

8

9

10

11

12

DR

13

14

15

16

17

18

19

20

P4.0

(Top View)

40L PDIP

AF

P2.1/A9

P2.0/A8

P2.3/A11

P2.4/A12

P2.2/A10

VDD

40

P0.0/AD0

39

P0.1/AD1

38

P0.2/AD2

37

P0.3/AD3

36

T,C

P0.4/AD4

35

SM8958A ihhP

34

P0.5/AD5

P0.6/AD6

33

32

P0.7/AD7

#EA

31

30

ALE

D

#PSEN

29

P2.7/A15

28

P2.6/A14

27

P2.5/A13

26

P2.4/A12

25

P2.3/A11

24

P2.2/A10

23

P2.1/A9

22

21

P2.0/A8

NFIDENT

O

NO

O

C

T

PY

O

XTAL2

#RD/P3.7

#WR/P3.6

VSS

P4.0

XTAL1

P2.0/A8

P2.1/A9

P2.3/A11

P2.2/A10

P2.4/A12

Specifications subject to change without notice,contact your sales representatives for the most recent information.

2/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Block Diagram

Stack Pointer

Buffer2

RES

Vdd

Vss

Timer 2

WDT

Reset Circuit

Power

Circuit

Timer 1

Timer 0

to pertinent blocks

to whole chip

Preliminary

Decoder & Register

Acc

Buffer1

1024 bytes

RAM

AL

I

Incrementer

Buffer

DPTR

PC

XTAL2

XTAL1 #EA

ALE

#PSEN

SPWM

Interrupt

Circuit

Timing

Generator

Instruction

Register

AF

Port 0

Latch

DR

5

Port 0

Driver & Mux

to pertinent blocks

to whole system

T,C

Port 1

Latch

D

Port 1

Driver & Mux

ALU

NFIDENT

PSW

O

NO

O

Port 2

Latch

Port 2

Driver & Mux

T

Port 3 Latch

Port 3

Driver & Mux

O

C

Port 4 Latch

Port 4

Driver & Mux

PY

2

Program

Counter

Register

Memory

32K

bytes

Flash

7FFFH

0000H

8

Specifications subject to change without notice,contact your sales representatives for the most recent information.

3/25 Preliminary Ver 0.2 PID 8958A 09/02

8

4

SyncMOS Technologies Inc. SM8958A

September 2002

Pin Descriptions

40L

44L

PDIP

QFP

PLCC

Pin#

1 40 2 T2/P1.0 i/o timer 2 clock out & bit 0 of port 1 2 41 3 T2EX/P1.1 i/o timer 2 control & bit 1 of port 1 3 42 4 P1.2 i/o bit 2 of port 1 4 43 5 SPWM0/P1.3 i/o SPWM channel 0, bit 3 of port 1 5 44 6 SPWM1/P1.4 i/o SPWM channel 1, bit 4 of port 1 6 1 7 SPWM2/P1.5 i/o SPWM channel 2, bit 5 of port 1 7 2 8 SPWM3/P1.6 i/o SPWM channel 3, bit 6 of port 1 8 3 9 SPWM4/P1.7 i/o SPWM channel 4, bit 7 of port 1 9 4 10 RES H i Reset 10 5 11 RXD/P3.0 i/o Receive data & bit 0 of port 3 11 7 13 TXD/P3.1 i/o Transmit data & bit 1 of port 3 12 8 14 #INT0/P3.2 L/ - i/o low true interrupt 0 & bit 2 of port 3 13 9 15 #INT1/P3.3 L/ - i/o low true interrupt 1 & bit 3 of port 3 14 10 16 T0/P3.4 i/o Timer 0 & bit 4 of port 3 15 11 17 T1/P3.5 i/o Timer 1 & bit 5 of port 3 16 12 18 #WR/P3.6 i/o ext. memory write & bit 6 of port 3 17 13 19 #RD/P3.7 i/o ext. mem. read & bit 7 of port 3 18 14 20 XTAL2 o Crystal out 19 15 21 XTAL1 i Crystal in 20 16 22 VSS Sink Voltage, Ground 21 18 24 P2.0/A8 i/o bit 0 of port 2 & bit 8 of ext. memory address 22 19 25 P2.1/A9 i/o bit 1 of port 2 & bit 9 of ext. memory address 23 20 26 P2.2/A10 i/o bit 2 of port 2 & bit 10 of ext. memory address 24 21 27 P2.3/A11 i/o bit 3 of port 2 & bit 11 of ext. memory address 25 22 28 P2.4/A12 i/o bit 4 of port 2 & bit 12 of ext. memory address 26 23 29 P2.5/A13 i/o bit 5 of port 2 & bit 13 of ext. memory address 27 24 30 P2.6/A14 i/o bit 6 of port 2 & bit 14 of ext. memory address 28 25 31 P2.7/A15 i/o bit 7 of port 2 & bit 15 of ext. memory address 29 26 32 #PSEN o program storage enable 30 27 33 ALE o address latch enable 31 29 35 #EA L i external access & VPP 32 30 36 P0.7/AD7 i/o bit 7 of port 0 & data/address bit 7 of ext. memory 33 31 37 P0.6/AD6 i/o bit 6 of port 0 & data/address bit 6 of ext. memory 34 32 38 P0.5/AD5 i/o bit 5 of port 0 & data/address bit 5 of ext. memory 35 33 39 P0.4/AD4 i/o bit 4 of port 0 & data/address bit 4 of ext. memory 36 34 40 P0.3/AD3 i/o bit 3 of port 0 & data/address bit 3 of ext. memory 37 35 41 P0.2/AD2 i/o bit 2 of port 0 & data/address bit 2 of ext. memory 38 36 42 P0.1/AD1 i/o bit 1 of port 0 & data/address bit 1 of ext. memory 39 37 43 P0.0/AD0 i/o bit 0 of port 0 & data/address bit 0 of ext. memory 40 38 44 VDD Drive Voltage, +5 Vcc

17 23 P4.0 i/o bit 0 of Port 4 28 34 P4.1 i/o bit 1 of Port 4 39 1 P4.2 i/o bit 2 of Port 4 6 12 P4.3 i/o bit 3 of Port 4

Symbol Active I/O Names

NFIDENT

O

T,C

NO

AF

O

D

DR

Preliminary

AL

I

PY

O

C

T

Specifications subject to change without notice,contact your sales representatives for the most recent information.

4/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Special Function Register (SFR)

The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general 8052, as well as SM8958A Extension SFRs.

Special Function Register (SFR) Memory Map

$F8

$F0

$E8

$E0 $D8 $D0 $C8 $C0

$B8

$B0

$A8

$A0

$98

$90 $88 $80

Note: The text of SFRs with bold type characters are Extension Special Function Registers for

Addr SFR Reset 7 6 5 4 3 2 1 0

85H RCON ******00 RAMS1 RAMS0 86H DBANK 0***0001 BSE BS3 BS2 BS1 BS0 97H WDTKEY ******** WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0 9BH P1CON 00000*** SPWME4 SPWME3 SPWME2 SPWME1 SPWME0 9FH WDTC 0*0**000 WDTE CLEAR PS2 PS1 PS0 A3H SPWMC ******00 SPFS1 SPFS0 A4H SPWMD0 00H SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00 A5H SPWMD1 00H SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10 BRM12 BRM11 BRM10 A6H SPWMD2 00H SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20 BRM22 BRM21 BRM20 A7H SPWMD3 00H SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30 BRM32 BRM31 BRM30

ACH SPWMD4 00H SPWMD44 SPWMD43 SPWMD42 SPWMD41 SPWMD40 BRM42 BRM41 BRM40

BFH SCONF 0*****00 WDR OME ALEI C8H T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 C9H T2MOD ******00 T2OE DCEN D8H P4 ****1111 P4.3 P4.2 P4.1 P4.0

B

ACC

P4

PSW

T2CON T2MOD RCAP2L RCAP2H TL2 TH2

IP SCONF

P3

IE SPWMD4

P2 SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3

SCON SBUF P1CON WDTC

P1 WDTKEY

TCON TMOD TL0 TL1 TH0 TH1

P0 SP DPL DPH (Reserved) RCON DBANK PCON

NFIDENT

O

T,C

NO

AF

O

D

DR

Preliminary

AL

I

PY

O

C

T

SM8958A

$FF

$F7

$EF $E7 $DF $D7

$CF $C7

$BF

$B7

$AF $A7 $9F $97

$8F $87

Specifications subject to change without notice,contact your sales representatives for the most recent information.

5/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Extension Function Description

1. Memory Structure

The SM8958A is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general 8052 structure.

1.1 Program Memory

The SM8958A has 32K byte on-chip flash memory which used as general program memory. The address range for the 32K byte is $0000 to $7FFF.

32K Program

memory space

7FFF

Preliminary

AL

I

PY

0000

Note: The single flash block address structure for doing as well as program ROM flash.

1.2 Data Memory

NFIDENT

O

C

O

T

The SM8958A has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by ‘Bank mapping direct addressing mode’ as described in next page.

T,C

02FF

NO

AF

O

Expanded 768 bytes RAM (Accessed by direct external addressing mode, by instruction MOVX, or by Bank mapping direct addressing mode)

FF

( OME = 1 )

80

0000

DR

FF

Higher 128 bytes (Access by indirect addressing mode only)

80 7F

Lower 128 bytes (Accessed by

direct & indirect

00

addressing mode)

D

SFR (Accessed by direct

addressing mode only)

On-chip expanded RAM address structure.

Specifications subject to change without notice,contact your sales representatives for the most recent information.

6/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)

Data Memory $00 to $FF is the same as 8052.

The address $00 to $7F can be accessed by direct and indirect addressing modes.

Address $00 to $1F is register area.

Address $20 to $2F is memory bit area.

Address $30 to $7F is for general memory area.

1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)

The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode.

Address $80 to $FF is data area.

1.2.3 Data Memory - Expanded 768bytes ($0000 to $02FF, Bank 4 ~ Bank 15)

From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described below:

Preliminary

AL

I

1.3 Bank mapping direct addressing mode

We provide RAM bank address ‘40H~7FH’ as mapping window which allow user access all the 1KB on-chip RAM through this RAM bank address.

:

PY

O

NFIDENT

That means using direct addressing mode can access all the 1KB on-chip RAM. Please see next page for the mapping mode table.

O

C

T

T,C

NO

AF

O

D

DR

Specifications subject to change without notice,contact your sales representatives for the most recent information.

7/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

BS3 BS2 BS1 BS0 040h~07fh map-

ping address

0 0 0 0 000h~03fh lower 128 byte RAM

0 0 0 1 040h~07fh lower 128 byte RAM

0 0 1 0 080h~0bfh higher 128 byte RAM

0 0 1 1 0c0h~0ffh higher 128 byte RAM

0 1 0 0 0000h~003fh on-chip expanded 768 byte RAM

0 1 0 1 0040h~007fh “

0 1 1 0 0080h~00bfh “

0 1 1 1 00c0h~00ffh “

1 0 0 0 0100h~013fh “

1 0 0 1 0140h~017fh “

1 0 1 0 0180h~01bfh “

1 0 1 1 01c0h~01ffh “

1 1 0 0 0200h~023fh “

1 1 0 1 0240h~027fh “

1 1 1 0 0280h~02bfh “

1 1 1 1 02c0h~02ffh “

NFIDENT

O

With this bank mapping scheme, user can access entire 1K byte on-chip RAM with direct addressing method. That means using the window area ($040~$07F), user can access any bank (64 byte) data of 1K byte on-chip RAM space which is selected by BS[3:0] of data bank control register (DBANK, $86).

Preliminary

Note

AL

I

PY

O

C

T

T,C

For example, user write #30h to $101 address: MOV DBANK, #88H ; set bank mapping $040~$07f to $0100~$013f MOV A, # 30H ; store #30H to A MOV 41H, A ; write #30H to $0101 address

AF

NO

O

D

DR

Specifications subject to change without notice,contact your sales representatives for the most recent information.

8/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Data Bank Control Register (DBANK, $86)

bit-7 bit-0

Read :

Write :

Reset value :0 * ** 0001

Data bank select enable bit BSE = 1 enables the data bank select function Data bank select enable bit BSE = 0 disables the data bank select function

BS[3:0] setting will map $040~$07F RAM space to entire 1K byte on-chip RAM space.

BSE Unused Unused Unused BS3 BS2 BS1 BS0

Preliminary

AL

I

Internal RAM Control Register (RCON, $85)

bit-7 bit-0

Read :

Write :

Reset value :******00

SM8958A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1,

RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).

Unused Unused Unused Unused Unused Unused RAMS1 RAMS0

PY

O

NFIDENT

RAMS1 RAMS0 MOVX @Ri i=0,1 mapping to expended RAM address

0 0 $0000 ~ $00FF

0 1 $0100 ~ $01FF

1 0 $0200 ~ $02FF

O

C

T

T,C

The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.

NO

AF

System Control Register (SCONF, $BF)

bit-7 bit-0

Read :

Write :

Reset value :0*****00

DR

WDR Unused Unused UnusedUnusedUnused OME ALEI

O

D

WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow. WDR will be set to 1, The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.

Specifications subject to change without notice,contact your sales representatives for the most recent information.

9/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

OME : 768 bytes on-chip RAM enable bit. The bit 0 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 0 (disable).

ALEI : ALE output inhibit bit, to reduce EMI. Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.

1.4 I/O Pin Configuration

The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a ‘1’ which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input. The port 4 used as GPIO will has the same function as port 1, 2 and 3.

output data

input

data

port 0

standard 8051

NFIDENT

O

2. Port 4 for PLCC or QFP package :

Preliminary

output data

input

data

C

T

PY

O

AL

I

port 1, 2 and 3 standard 8051

The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.

Port4 (P4, $D8)

AF

bit-7 bit-0

Read :

Write :

Reset value :****1111

Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0

DR

T,C

NO

O

D

The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.

Specifications subject to change without notice,contact your sales representatives for the most recent information.

10/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

3.Watch Dog Timer

The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened

The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.

There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is independent to the system frequency.

To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8958A been reset, either hardware reset or WDT reset.

To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.

Preliminary

AL

I

3.1 Watch Dog Timer Registers:

Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)

NFIDENT

bit-7 bit-0

Read :

Write :

Reset value : 0 * 0 * * 0 0 0

WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit

PS[2:0] : Overflow period select bits

WDTE Unused CLEAR Unused Unused PS2 PS1 PS0

T,C

AF

O

NO

C

T

O

PS [2:0] Overflow Period (ms)

000 2.048

D

DR

001 4.096

010 8.192

011 16.384

100 32.768

PY

O

101 65.536

110 131.072

111 262.144

Specifications subject to change without notice,contact your sales representatives for the most recent information.

11/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Watch Dog Key Register - (WDTKEY, $97H)

bit-7 bit-0

Read :

Write :

Reset value : * * * * * * * *

By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to enable the WDTC write attribute, That is MOV WDTKEY, # 1EH MOV WDTKEY, # E1H

When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # E1H MOV WDTKEY, # 1EH

Watch Dog Timer Register - System Control Register (SCONF, $BF)

WDT

KEY7

WDT

KEY6

WDT

KEY5

WDT

KEY4

Preliminary

WDT

KEY3

WDT

KEY2

WDT

KEY1

AL

I

WDT

KEY0

bit-7 bit-0

Read :

Write :

Reset value :0*****00

The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened

4. Reduce EMI Function

The SM8958A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.

WDR Unused Unused Unused Unused Unused OME ALEI

NFIDENT

O

C

T

T,C

NO

PY

O

AF

5. Specific Pulse Width Modulation (SPWM)

The Specific Pulse Width Modulation (SPWM) module contain 1 kind of PWM sub module: SPWM (Specific PWM). SPWM has five 8-bit channels.

5.1 SPWM Function Description:

The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(SPFS[1:0]+1)]/32.

DR

O

D

Specifications subject to change without notice,contact your sales representatives for the most recent information.

12/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

5.2 SPWM Registers - P1CON, SPWMC, SPWMD[4:0]

SPWM Registers - Port1 Configuration Register (P1CON, $9B

bit-7 bit-0

Read:

Write:

Reset value: 0 0 0 0 0 * * *

SPWME[4:0] : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.

SPWM Registers - SPWM Control Register (SPWMC, $A3

Read:

Write:

Reset value:******00

SPFS[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.

SPWME4 SPWME3 SPWME2 SPWME1 SPWME0 Unused Unused Unused

bit-7 bit-0

Unused Unused Unused Unused Unused Unused SPFS1 SPFS0

Preliminary

)

AL

I

)

PY

SPFS1 SPFS0 Divider SPWM clock, Fosc=20MHz SPWM clock, Fosc=24MHz

002 10MHz 12MHz

0 1 4 5MHz 6MHz

1 0 8 2.5MHz 3MHz

1 1 16 1.25MHz 1.5MHz

SPWM Registers - SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4

bit-7 bit-0

Read:

Write:

Reset value:00000000

SPWMD[4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform.

BRM[2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame

DR

AF

SPWMD

[4:0]4

T,C

SPWMD

[4:0]3

SPWMD

O

[4:0]2

D

NFIDENT

O

C

T

NO

SPWMD

[4:0]1

SPWMD

[4:0]0

O

BRM

[2:0]2

)

BRM

[2:0]1

BRM

[2:0]0

Specifications subject to change without notice,contact your sales representatives for the most recent information.

13/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

N = BRM[2:0] Number of SPWM cycles inserted in an 8-cycle frame

000 0

001 1

010 2

011 3

100 4

101 5

110 6

111 7

Example of SPWM timing diagram:

MOV SPWMC , #03H ; Set output frequency (Divider = 16) MOV SPWMD0 , #83H ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3 MOV P1CON , #08H ; Enable P1.3 as SPWM output pin

Preliminary

I

PY

1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame 6th cycle frame 7th cycle frame 8th cycle frame

O

32T 32T

32T

NFIDENT

32T

AL

32T 32T

16T

If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz

16T

1T 1T 1T

(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)

SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1)

The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32

AF

16T

T,C

D

16T

O

NO

O

DR

16T

C

T

16T

Specifications subject to change without notice,contact your sales representatives for the most recent information.

14/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Operating Conditions

Symbol Description Min. Typ. Max. Unit. Remarks

TA Operating temperature 0 25 70

TS Storage temperature -55 25 155

VCC5 Supply voltage 4.5 5.0 5.5 V For C Version

VCC3 Supply voltage 3 3.3 3.6 V For L Version

Fosc 16 Oscillator Frequency 3.0 16 16 MHz For 5V, 3.3V application

Fosc 25 Oscillator Frequency 3.0 25 25 MHz For 5V, 3.3V application

Fosc 40 Oscillator Frequency 3.0 40 40 MHz For 5V application

DC Characteristics

(16/25/40MHz, typical operating conditions, valid for SM8958A version series)

Symbol Parameter Valid

VIL1 Input Low Voltage port 0,1,2,3,4,#EA VIL2 Input Low Voltage RES, XTAL1 VIH1 Input High Voltage port 0,1,2,3,4,#EA VIH2 Input High Voltage RES, XTAL1 VOL1 Output Low Voltage port 0, ALE, #PSEN VOL2 Output Low Voltage port 1,2,3,4 VOH1 Output High Voltage port 0

VOH2 Output High Voltage port 1,2,3,4,ALE,#PSEN

IIL Logical 0 Input Current port 1,2,3,4 ITL Logical Transition Current port 1,2,3,4 ILI Input Leakage Current port 0, #EA R RES Reset Pull-down Resistance RES C IO Pin Capacitance I CC Power Supply Current Vdd

AF

T,C

NFIDENT

O

NO

O

D

DR

Preliminary

Min.

-0.5 0

Vcc+0.5

2.0

70%Vcc

2.4

90%Vcc

2.4

T

90%Vcc

50

o

C

o

C

Max.

0.8

Vcc+0.5

0.45

O

C

-75

-650 +

10

300

10 15 10 7

10

7

4.5

10

Ambient temperature under bias

AL

I

Unit

V V

V

V V

V

uA uA uA

Kohm

pF

mA

uA

Test Conditions

PY

IOL=3.2mA IOL=1.6mA

IOH=-800uA (only for VCC =5V) IOH=-80uA IOH=-60uA (only for VCC =5 V)

IOH=-10uA

Vin=0.45V Vin=2.0V

0.45V<Vin<Vcc

Freq=1MHz, Ta=25 C

Active mode, 40MHz

Active mode, 25MHz Active mode, 16MHz Idle mode, 40MHz Idle mode, 25MHz Idle mode, 16MHz

Power down mode

Specifications subject to change without notice,contact your sales representatives for the most recent information.

15/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

AC Characteristics

(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF)

Symbol Parameter T LHLL ALE pulse width RD/WRT 115 2xT - 10 nS T AVLL Address Valid to ALE low RD/WRT 43 T - 20 nS T LLAX Address Hold after ALE low RD/WRT 53 T - 10 nS T LLIV ALE low to Valid Instruction In RD 240 4xT - 10 nS T LLPL ALE low to #PSEN low RD 53 T - 10 nS T PLPH #PSEN pulse width RD 173 3xT - 15 nS T PLIV #PSEN low to Valid Instruction In RD 177 3xT - 10 nS T PXIX Instruction Hold after #PSEN RD 0 0 nS T PXIZ Instruction Float after #PSEN RD 87 T + 25 nS T AVIV Address to Valid Instruction In RD 292 5xT - 20 nS T PLAZ #PSEN low to Address Float RD 10 10 nS T RLRH #RD pulse width RD 365 6xT - 10 nS T WLWH #WR pulse width WRT 365 6xT - 10 nS T RLDV #RD low to Valid Data In RD 302 5xT - 10 nS T RHDX Data Hold after #RD RD 0 0 nS T RHDZ Data Float after #RD RD 145 2xT + 20 nS T LLDV ALE low to Valid Data In RD 590 8xT - 10 nS T AVDV Address to Valid Data In RD 542 9xT - 20 nS T LLYL ALE low to #WR High or #RD low RD/WRT 178 197 3xT - 10 3xT + 10 nS T AVYL Address Valid to #WR or #RD low RD/WRT 230 4xT - 20 nS T QVWH Data Valid to #WR High WRT 403 7xT - 35 nS T QVWX Data Valid to #WR transition WRT 38 T - 25 nS T WHQX Data hold after #WR WRT 73 T + 10 nS T RLAZ #RD low to Address Float RD 5 nS T YALH #WR or #RD high to ALE high RD/WRT 53 72 T -10 T + 10 nS T CHCL clock fall time nS T CLCX clock low time nS T CLCH clock rise time nS T CHCX clock high time nS T, TCLCL clock period 63 1/fosc nS

AF

T,C

Valid Cycle

O

fosc=16MHz Min. Typ. Max

NFIDENT

NO

Preliminary

Variable fosc Min. Typ. Max

O

C

T

Unit Remarks

AL

I

PY

D

ICC Active mode test circuit

DR

Vcc

RST

SM8958A

VCC

PO EA

ICC

Vcc

8

ICC Idle mode test circuit

RST

SM8958A

VCC

PO EA

ICC

Vcc

8

(NC)

Clock Signal

Specifications subject to change without notice,contact your sales representatives for the most recent information.

16/25 Preliminary Ver 0.2 PID 8958A 09/02

XTAL2 XTAL1 VSS

Clock Signal

(NC)

XTAL2 XTAL1 VSS

SyncMOS Technologies Inc. SM8958A

September 2002

Application Reference

Valid for SM8958A

X'tal 3MHz 6MHz 9MHz 12MHz C1 30 pF 30 pF 30 pF 30 pF C2 30 pF 30 pF 30 pF 30 pF R open open open open

X'tal 16MHz 25MHz 33MHz 40MHz C1 30 pF 15 pF 5 pF 2 pF C2 30 pF 15 pF 5 pF 2 pF

R open 62KΩ 6.8KΩ 4.7KΩ

NOTE: Oscillation circuit may differs with different crystal or ceramic

resonator in higher oscillation frequency which was due to each

crystal or ceramic resonator has its own characteristics.

User should check with the crystal or ceramic resonator manufacturer

for appropriate value of external components.

C1

Preliminary

X'tal

R

C2

XI

SM8958A

X2

AL

I

PY

Data Memory Read Cycle Timing

OSC

ALE

T12

T1

1

T2

T3

T,C

#PSEN

AF

#RD

DR

PORT2

PORT0

INST in Float A7 - A0

T4

2

3

T5

O

D

4

Float

O

NFIDENT

T6

O

T7

T8

T9

C

T10

T11

T12

T

NO

5

ADDRESS A15 - A8

6

DATA in

7

T1 T2

8

Float

T3

ADDRESS

or Float

Specifications subject to change without notice,contact your sales representatives for the most recent information.

17/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Program Memory Read Cycle Timing

T12 T1

OSC

ALE

#PSEN

#RD,#WR

PORT2

T2 T3 T4

1

2

3

T6

T5

5

ADDRESS A15 - A8

T7

Preliminary

T11 T12

T10

T9

T8

7

T1

T2

AL

I

ADDRESS A15 - A8

PORT0

Data Memory Write Cycle Timing

T12

OSC

ALE

#PSEN

#WR

DR

Float

T2 T3

T1

1

AF

A7 - A0

PORT2

3

4

Float

T4 T5

T,C

O

D

2

68

INST in

Float

A7 - A0

Float

PY

INST in

O

NFIDENT

T6

O

T7

T8

T10 T11 T1 T2

T9

C

T12

T

NO

5

ADDRESS A15 - A8

Float

T3

6

2

PORT0

Specifications subject to change without notice,contact your sales representatives for the most recent information.

18/25 Preliminary Ver 0.2 PID 8958A 09/02

INST Float

A7 - A0

3

DATA OUT

4

ADDRESS

or Float

SyncMOS Technologies Inc. SM8958A

September 2002

I/O Ports Timing

X1

inputs P0,P1

inputs P2,P3

Output by

Mov Px,Src

RxD at Serial Port

Shift Clock

(Mode 0)

T6

T7

current data

T8

T9

sampled

T10

sampled

T11

sampled

T12

Preliminary

T1

T2

next data

T3

T4

T6 T7

T5

AL

I

T8

Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)

NFIDENT

Vdd-0.5V

0.45V

Tm.I External Program Memory Read Cycle

#PSEN

AF

70%Vdd

20%Vdd-0.1V

T,C

O

TCHCL

TPLPH

NO

C

T

TCLCX

O

TCLCL

TCLCH

O

ALE

PORT 0

TLHLL

TAVL L

DR

A0 - A7

TLLPL

TLLAX

TPLAZ

D

TPLIV

TPXIZ

TPXIX

Instruction. IN

TAVI V

A8 - A15

PORT 2

PY

TCHCX

A0 - A7

A8 - A15

Specifications subject to change without notice,contact your sales representatives for the most recent information.

19/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Tm.II External Data Memory Read Cycle

#PSEN

ALE

TLLDV

P2.0 - P2.7 or A8 - A15 from DPH

#RD

PORT 0

PORT 2

TAVL L

TLLYL

TLLAX

A0 - A7

from Ri or DPL

TAVYL

TAVD V

TRLAZ

TRLRH

TRLDV

Preliminary

TYHLH

TRHDZ

TRHDX

DATA IN

AL

I

A0 - A7

from PCL

PY

A8 - A15 from PCH

INSTRL

IN

Tm.III External Data Memory Write Cycle

#PSEN

TLHLL

ALE

T,C

TLLYL

AF

#WR

TAVL L

TLLAX

O

TQVWX

D

DR

PORT 0

A0-A7

from Ri or DPL

TAVY L

PORT 2

P2.0-P2.7 or A8-A15 from DPH

O

NFIDENT

O

TWLWH

NO

TQVWH

DATA OUT

C

T

TYHLH

TWHQX

A0-A7

From PCL

A8-A15 from PCH

INSTRL

IN

Specifications subject to change without notice,contact your sales representatives for the most recent information.

20/25 Preliminary Ver 0.2 PID 8958A 09/02

A1

SyncMOS Technologies Inc. SM8958A

September 2002

40L 600mil PDIP Information

D

S

Preliminary

E

E1

AL

I

C

eA

e1

A2

A

L

B1

B

Note:

1. Dimension D Max & include mold flash or tie bar burrs.

2. Dimension E1 does not include inter lead flash.

3. Dimension D & E1 include mold mismatch and are

determined at the mold parting line.

4. Dimension B1 does not include dam bar protrusion/

infusion.

5. Controlling dimension is inch.

6. General appearance spec. should base on final visual

inspection spec.

AF

T,C

O

D

DR

PY

O

NFIDENT

O

Symbol A - / 0.210 - / 5.33 A1 0.010 / - 0.25 / A2 0.150 / 0.160 3.81 / 4.06 B 0.016 / 0.022 0.41 / 0.56 B1 0.048 / 0.054 1.22 / 1.37 C 0.008 / 0.014 0.20 / 0.36

NO

D - / 2.070 - / 52.58 E 0.590 / 0.610 14.99 / 15.49 E1 0.540 / 0.552 13.72 / 14.02 e1 0.090 / 0.110 2.29 / 2.79 L 0.120 / 0.140 3.05 / 3.56 a 0 / 15 0 / 15 eA 0.630 / 0.670 16.00 / 17.02 S - / 0.090 - / 2.29

Dimension in inch

C

minimal/maximal

T

a

Dimension in mm minimal/maximal

Specifications subject to change without notice,contact your sales representatives for the most recent information.

21/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

44L Plastic Chip Carrier (PLCC)

6

7

Preliminary

EHE

L

AL

I

GE

y

D

HD

T,C

θ

e

GD

AF

b1

O

Note:

1. Dimension D & E does not include inter lead flash.

2. Dimension b1 does not include dam bar protrusion/ intrusion.

3. Controlling dimension: Inch

4. General appearance spec. should base on final visual inspection spec.

DR

D

PY

O

NFIDENT

O

b

NO

C

T

C

Dimension in inch

Symbol A - / 0.185 - / 4.70 A1 0.020 / - 0.51 / A2 0.145 / 0.155 3.68 / 3.94 b1 0.026 / 0.032 0.66 / 0.81 b 0.016 / 0.022 0.41 / 0.56 C 0.008 / 0.014 0.20 / 0.36 D 0.648 / 0.658 16.46 / 16.71 E 0.648 / 0.658 16.46 / 16.71 e 0.050 BSC 1.27 BSC GD 0.590 / 0.630 14.99 / 16.00 GE 0.590 / 0.630 14.99 / 16.00 HD 0.680 / 0.700 17.27 / 17.78 HE 0.680 / 0.700 17.27 / 17.78 L 0.090 / 0.110 2.29 / 2.79

- / 0.004 - / 0.10 / /

minimal/maximal

θ

y

A2

A1

A

Dimension in mm minimal/maximal

Specifications subject to change without notice,contact your sales representatives for the most recent information.

22/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

44L Plastic Quad Flat Package

D2

D1

Preliminary

C

L

S

D

A2

L1

2

e

θ

R1

AL

I

b

3

θ

Gage Plane

0.25 mm

R2

E2

E1 E

e1

Note:

Dimension D1 and E1 do not include mold protrusion.

Allowance protrusion is 0.25mm per side.

Dimension D1 and E1 do include mold mismatch

and are determined datum plane.

Dimension b does not include dam bar protrusion.

Allowance dam bar protrusion shall be 0.08 mm total

in excess of the b dimension at maximum material

condition. Dam bar cannot be located on the lower

radius or the lead foot.

DR

AF

T,C

seating plane

D

NFIDENT

O

e

NO

O

A1

PY

A

O

C

Symbol A - / 0.100 - / 2.55

T

A1 0.006 / 0.014 0.15 / 0.35 A2 0.071 / 0.087 1.80 / 2.20 b 0.012 / 0.018 0.30 / 0.45 c 0.004 / 0.009 0.09 / 0.20 D 0.520 BSC 13.20 BSC D1 0.394 BSC 10.00 BSC D2 0.315 8.00 E 0.520 BSC 13.20 BSC E1 0.394 BSC 10.00 BSC E2 0.315 8.00 e 0.031 BSC 0.80 BSC L 0.029 / 0.041 0.73 / 1.03 L1 0.063 1.60 R1 0.005 / - 0.13 / R2 0.005 / 0.012 0.13 / 0.30 S 0.008 / - 0.20 / 0 / 7 as left 1 0 / - as left 2 10 REF as left 3 7 REF as left C 0.004 0.10

Dimension in Inch

C

minimal/maximal

θ

θ θ

θ

Dimension in mm minimal/maximal

°

Specifications subject to change without notice,contact your sales representatives for the most recent information.

23/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Company Contact info Programmer Model Number Advantech

7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw

Caprilion P.O. Box 461 KaoHsiung, Taiwan, ROC Web site: http://www.market.net.tw/ ~ cap/

Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw

eMCU writer list

Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw

Tel:07-3865061 Fax:07-3865421 E-mail: cap@market.net.tw

Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw

Preliminary

LabTool - 48 (1 * 1) LabTool - 848 (1*8)

UNIV2000

AL

I

All - 11 (1*1) Gang - 08 (1*8)

PY

Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw

GECN

NO.3 Heguang Road ,Tangxia The Fist Industry Area,Zhongshan Avenue ,Guangzhou Web site: http://www.Greatecn.com

T,C

Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw

NFIDENT

O

Tel:+86-20-85664031,85664610 E-mail: xuexiang@21cn.com

ankxuexiang@hotmail.com

T

C

ChipStation (1*1) SU - 2000 (1*8)

O

Superpro/2000 (1*1) Superpro/680 (1*1) Superpro/280 (1*1) Superpro/L+(1*1)

NO

AF

O

D

DR

Specifications subject to change without notice,contact your sales representatives for the most recent information.

24/25 Preliminary Ver 0.2 PID 8958A 09/02

SyncMOS Technologies Inc. SM8958A

September 2002

Feedback / Inquiry:

To Attn

Fax

Tel

: Request customer logo as below :

:SyncMOS Technologies, Inc. :MKT / Customer Service Dept. : 86-20-8564525

: :86-20-85664031 :86-20-85664610

Preliminary

From

Company :

Dept, Section :

Position Title :

Inquiry Date :

Ref No :

:

AL

I

AF

DR

T,C

O

D

NFIDENT

O

C

T

NO

PY

O

Specifications subject to change without notice,contact your sales representatives for the most recent information.

25/25 Preliminary Ver 0.2 PID 8958A 09/02