Sequans Communications VZM20Q Operators Guide

Sequans Module VZM20Q

SEQUANS Communications

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Module
Integration
Guide

Legal Notices

Copyright© 2016, SEQUANS Communications

All information contained herein and disclosed by this document is
confidential and the proprietary property of SEQUANS Communications,
and all rights therein are expressly reserved. Acceptance of this material
signifies agreement by the recipient that the information contained in this
document is confidential and that it will be used solely for the purposes set
forth herein. Acceptance of this material signifies agreement by the recipient
that it will not be used, reproduced in whole or in part, disclosed, distributed,
or conveyed to others in any manner or by any means – graphic, electronic, or
mechanical, including photocopying, recording, taping, or information
storage and retrieval systems – without the express written permission of
SEQUANS Communications.

Preface

All Sequans’ logos and trademarks are the property of SEQUANS
Communications. Unauthorized usage is strictly prohibited without the
express written permission of SEQUANS Communications. All other
company and product names may be trademarks or registered trademarks of
their respective owners. Products and services of SEQUANS
Communications, and those of its licensees may be protected by one or more
pending or issued U.S. or foreign patents.

Because of continuing developments and improvements in design,
manufacturing, and deployment, material in this document is subject to
change without notification and does not represent any commitment or
obligation on the part of SEQUANS Communications. SEQUANS
Communications shall have no liability for any error or damages resulting
from the use of this document.

MODULE INTEGRATION GUIDE PROPRIETARY i

SEQUANS Communications

Document Revision History

Revision Date Product Application

01 November 2016 First edition of the VZM20Q Module Integration Guide.

ii PROPRIETARY MODULE INTEGRATION GUIDE

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Purpose and Scope

This Application note is intended to help customers who want to deviate from
the Sequans’ Reference Designs to successfully integrate and test their
product based on module.

It presents Integration Guidelines for:

• All VZM20Q Interface Requirements

• Tips and “how-to”s for troubleshooting

Development of the Hardware should follow a process that ensures the
solution will be optimum and it is the purpose / goal of this document to reach
this. For this to occur it is recommended that these processes are followed in
order. This document is delivered as three sections:

About this Guide

1. System Overview

2. Hardware and software design guidelines

3. Bring-up verification and test

Caution: It is highly recommended that Sequans support teams are

involved during all processes to ensure the very best can be
achieved for the alternative design.

Who Should Read this Document

This Application Note is for hardware designers of user applications based on
Sequans VZM20Q Module.

Important: Reference design source files are based on the application PADS®

from Mentor Graphics® (www.mentor.com). Customers using
the other CAD applications can use schematics translators and
viewers, such as Elgris® (www.elgris.com). Such translators may
save time and prevent mistakes during manual PADs conversion.

MODULE INTEGRATION GUIDE PROPRIETARY iii

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Reference Documentation

1. DV Tool User Guide

2. Sequans Hardware Platform User Guide

3. mTools Reference Manual

4. Nimbelink™ Evaluation Kit User Manual

See http://nimbelink.com/

Changes in this Document

This is the first edition of the document.

iv PROPRIETARY MODULE INTEGRATION GUIDE

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Documentation Conventions

This section illustrates the conventions that are used in this document.

General Conventions

Note Important information requiring the user’s attention.

A condition or circumstance that may cause damage to the equipment or loss of
data.

Caution

A condition or circumstance that may cause personal injury.

War ning

Italics Italic font style denotes

• emphasis of an important word;

• first use of a new term;

• title of a document.

Screen Name Sans serif, bold font denotes

• on-screen name of a window, dialog box or field;

• keys on a keyboard;

• labels printed on the equipment.

Software Conventions

Code Regular Courier font denotes code or text displayed on-screen.

Code Bold Courier font denotes commands and parameters that you enter exactly as

shown. Multiple parameters are grouped in brackets [ ]. If you are to choose only
one among grouped parameters, the choices are separated with a pipe: [parm1 |
parm2 | parm3] If there is no pipe separator, you must enter each parameter:
[parm1 parm2 parm3]

Code Italic Courier font denotes parameters that require you to enter a value or

variable. Multiple parameters are grouped in brackets [ ]. If you are to choose
only one among grouped parameters, the choices are separated with a pipe:
[parm1 | parm2 | parm3] If there is no pipe separator, you must enter a value for
each parameter: [parm1 parm2 parm3]

MODULE INTEGRATION GUIDE PROPRIETARY v

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Table of Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i

Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i

Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ii

About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Purpose and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Who Should Read this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv

Changes in this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv

Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Chapter 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Recommended Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.1 Design Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.2 Schematics Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.3 PCB Placement and Layout Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.4 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.5 Functional Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.6 Manufacturing Recommended Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Chapter 2

Manufacturing Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Manufacturing Process Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Module Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 3

Hardware Integration Recommendations . . . . . . . . . . . . . . . . . . . 6

3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1.1 Synthesis of the Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1.2 Power Supply Circuit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1.3 Module Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 SIM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2.1 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2.2 Other Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2.3 Software-Configurable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Host Communications Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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Table of Contents

3.3.1 Introduction to UART Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3.2 General Notes on UART Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3.3 UART0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.4 UART1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3.5 UART2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4.1 RF Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4.2 Circuit Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.3 Test Points and Measurement Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.4 Antennas and RF Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 Reset and Environmental Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 GPIO Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6.1 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6.2 Software Configurable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4

PCB Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 Trace Characteristic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.1 Digital Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.2 Power Supply Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.3 RF Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.4 Controlled Impedance Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.5 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 5

Bring-Up and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Functional Verification without Assembled Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3.2 RF Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4 Functional Verification with Assembled Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.2 Confirm Module Power-Up Operation (UART1) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4.3 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.4 SIM Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 LTE RF Performance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.1 Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5.2 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.5.3 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Appendix A

Hardware Test Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . 37

A.1 RF Interfaces Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Table of Contents

A.1.1 LTE RF Test Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Appendix B

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

viii Proprietary M

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ODULE INTEGRATION GUIDE

Introduction

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1

1.1 System Architecture

Figure 1-1 provides an overview of the Host to VZM20Q interfacing

relationship. The various interfaces are explained in detail later in this
document.

It provides summary details of:

• Digital interfaces between the VZM20Q and the host platform

• Power supply requirement (V

Note: V

It does not show the VZM20Q local terminations.

range is 3.1 V to 4.5 V.

BAT1

bat

).

MODULE INTEGRATION GUIDE PROPRIETARY 1

Figure 1-1: VZM20Q-Based System Architecture

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INTRODUCTION

SYSTEM ARCHITECTURE

Figure 1-2: VZM20Q Mounted on Skywire™ 4G LTE CAT M1 Embedded

Modem

Figure 1-3: Skywire™ 4G LTE CAT M1 Embedded Modem - Bottom View

2 PROPRIETARY MODULE INTEGRATION GUIDE

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Note: The hardware design package of VZM20Q reference design is

available from your Sequans local contact.

1.2 Recommended Design Flow

To ensure that the customer benefits from the details of this document we
recommend to carefully take the following information into account during
the design process.

1.2.1 Design Modifications

Compared to Nimbelink™ reference design, only the following modifications
to the BOM are allowed to designers:

INTRODUCTION

RECOMMENDED DESIGN FLOW

• SIM connector

•Level shifter on UARTs

• Circuitry on RESETN

Note: Any GNSS/GPS function is out of scope of VZM20Q Reference

Design.

Consultancy with Sequans is highly recommended to verify these alternate
preferences.

1.2.2 Schematics Review

Ensuring that the circuit design by analysis will be compliant with the
Sequans’ chipset. It is recommended that the review of the design includes
Sequans’ technical support team.

1.2.3 PCB Placement and Layout Review

To ensure the PCB layout is compliant, it is recommended that the review of
this CAD activity includes Sequans at several iterative steps such as
component placement, RF and digital routing, final layout levels etc. This
might avoid later rework.

MODULE INTEGRATION GUIDE PROPRIETARY 3

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INTRODUCTION

RECOMMENDED DESIGN FLOW

1.2.4 Optimization

When the design returns from the manufacture, it might occur that
improvements have to be made to the circuits. It is also recommended to
communicate such results to Sequans who can help to verify the
implementation.

1.2.5 Functional Validation

The test of the design performance should be done in thorough detail. This
will ensure the compliance with the test standard as the final design will be
subjected to a formal qualification. It is the designer’s responsibility to meet
this goal. Sharing the results with Sequans will help identify any particular
problem that could be fixed at an early stage to ensure strong confidence of
qualification. This should be done for all the tests that involve Sequans
chipsets.

Hardware Test Preparation on page 37 provides you with the hardware setup

required to proceed with test phases.

1.2.6 Manufacturing Recommended Process

Manufacturing Process on page 5 provides information on the process

required to achieve the manufacturing of your product.

4 PROPRIETARY MODULE INTEGRATION GUIDE

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Manufacturing Process

2

2.1 Manufacturing Process Overview

Note: The contents of this section will be provided in a future revision

of the document.

2.2 Module Upgrade

Note: The contents of this section will be provided in a future revision

of the document.

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Hardware Integration Recommendations

3

This chapter provides the information necessary to understand the various
interface requirements to interconnect with the VZM20Q, associated
software-configurable items for the respective interface and, more generally,
good practices for board design when considering the various interface types.

Table 3-1 describes the requirements for trace characteristics.

Important: Different signals require different special needs. Please consider

carefully the interfacing requirement of each relevant connection.

Table 3-1: Requirements Overview: Trace Characteristics

Trace Characteristics Description

Digital Generic digital trace if reasonable high impedance

Supply Broader trace routing based on the power needs of the load

50 Ohm Conventionally used for RF routing. Track must be retained to this impedance

Quiet Intention is to keep away from digital signals and as short as possible, possibly burying

the signal

Ground Shortest VZM20Q Ground to Host Ground possible, best possible lowest impedance

path

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HARDWARE INTEGRATION RECOMMENDATIONS

3.1 Power Supply

3.1.1 Synthesis of the Power Supplies

Table 3-2 and Table 3- 3 provide a synthesis of the power supplies and their

characteristics. Please see typical voltage values in VZM20Q Datasheet.

Note: Each output reference voltage (pads 3, 9, 11) can be either running

or powered off depending on the internal software configuration.
They should not be used to power external IC or parts that require
permanent supply.

Table 3-2: Power Supply Signals

POWER SUPPLY

Pin

Pin Name

1V8 3 Supply Out Reference voltage. See the note above.

3V0 9,11 Supply Out To be only connected to VCC1_PA and VCC2_PA. These pads

GNSS_VCC1 100 Supply In Reserved. Do not connect.

GNSS_VCC2 101 Supply Out Reserved. Do not connect.

GNSS_VCC3 102 Supply In Reserved. Do not connect.

VBAT1 107, 108 Supply In Voltage used for qualification is 3.8 V, range 3.1 V to 4.5 V

VCC1_PA 97 Supply In To be connected to 3V0

VCC2_PA 98, 99 Supply In To be connected to 3V0

Number

Trace
Style

Direction Notes

should not be used for any other usage. See the note above.

Table 3-3: Power Supply Digital Enable Signals

Typical

Pin

Pin Name

POWER_EN 106 Digital In 1V8

MODULE INTEGRATION GUIDE PROPRIETARY 7

Number

Tra ce
Style

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Direction

Voltage

Ref

Notes