The SC2422A biphase, current mode controller is designed to work with Semtech smart synchronous
drivers, such as the SC1205, SC1305 or the SC1405 to
provide the DC/DC converter solution for the most
demanding Micro-processor applications. Input current
rather than output current sensing is used to guar antee
precision phase to phase current matching using a
single sense resistor on the input power line. Accur ate
current sharing and pulse by pulse current limit are
implemented without the power loss and transient response degradation associated with output current
sense methods. Two phase operation allows significant
reduction in input/output ripple while enhancing transient response.
The DAC step size and range are programmable with
external components thus allowing compliance with
new and emerging VID ranges.
A novel approach implements ac tive droop, minimizing
output capacitor requirements during load transients.
This avoids the pitfalls of the passive droop im plementation. This feature als o allows easy implementation of
N+1 redundancy and current sharing among modules.
Programmable Under Voltage Lockout assures proper
start-up and shutdown by synchronizing the controller
to the driver supply. Wide PWM frequency range allows
use of low profile, surface mount components.
TYPICAL APPLICATION SCHEMATIC
FEATURES
Precision, pulse by pulse phase current match-
•
ing
•
Active drooping allows for best transient response
PARAMETERCONDITIONSMINTYPMAXUNITS
Current Sense Amplifier
= 25°C, R
AMB
= 11.5kΩ.
REF
Amplifier Gain(V
Input Offset Voltage,
(V
OC-
OC-
- V
) < 100mV26dB
OC+
- V
) < 100mV4mV
OC+
Input Referred
CMRRV
PSRRV
= 9 ~ 14V @ DC80dB
ICM
= 9 ~ 14V @ DC80dB
CC
Input Common Mode RangeV
Max Differential Signal/
V
- V
OC-
OC+
Current Limit Threshold
I-Limit DelayCurrent limit activation to OUT 1 & OUT
2 switching off
Protection
UVLO Ramp-up Threshold
UVLO Ramp-down Threshold
R
SOURCE
R
SOURCE
UVLO pin = 20k
UVLO pin = 20k
Ω
Ω
Outputs (OUT 1, OUT 2)
Max Duty CyclePer phase, F
Duty MatchF
Typical Output Voltage Swing
OSC
R
= 500kHz47%
OSC
= 500kHz-.5.5%
= 10k
L
Ω
.82.5V
+/-
CC
0.3
100mV
60ns
1.475V
1.375V
R
= 100k
L
Ω
.23.3V
VID Logic Threshold0.82V
VID Logic Pin Bias CurrentV
= 012µA
IN
Note:
1. If the VID pins are driven high by an external source (in contrast to being left open), then all VIDs input will need
to be externally pulled high. If VIDs are left open, no external pull-up is required.
2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
RREF Frequency setting resistor pin. Also programs the DAC current step size. (see application information for programming the frequency)
Pin 9:
GND Chip ground.
Pin 10:
Out. This pin may be connected to the MOSFET driver
supply through a voltage divider to inhibit the SC2422A
until the drivers are on. The UVLO comparator trip
point is 1.5V.
UVLO Programmable Under Voltage Lock-
sense resistor.
Pin 12:
nal Power MOSFET driver.
Pin 13:
nal Power MOSFET driver.
Pin 14:
pin is connected to MOSFET side of the current sense
resistor.
Pin 15:
ground (GSEN) with a .022µF - 0.1µF capacitor to implement soft start in conjunction with internal 3KΩ resistor. To ensure output voltage accuracy, the maximum current source/sink from this pin should be limited to 0.5 uA.
Pin 16:
OUT2 PWM output for phase 2. Drives exter-
OUT1 PWM output for phase 1. Drives exter-
OC+ Input current sense positive input. This
BGOUT Soft start and reference. Bypass to
VCC Chip positive supply.
Pin 11:
pin is connected to the input supply side of the current
The SC2422A is an Input Current Mode Controller designed for High Current, High performance two phase
DC/DC converters. The Current mode control is implemented by generating the PWM ramp from the Input
Current, rather than the output current. This has the
advantage of eliminating the output current sense resistors, and the power loss associated with output current sensing. Eliminating the output current sense resistors has the added advantage of improving the transient response by reducing the output impedance.
The output voltage is programmed via a 5-bit DAC in
32 steps. A novel technique allows programmable
DAC step size and output offset, allowing the SC2422A
based DC/DC converters to work in VRM9.0, VRM 8.3,
VRM8.4, VRM8.5 or future specified voltage ranges.
Theory of Operation
Pulse by Pulse Current Matching
The operation of the Input Current Mode, ICM, is as
follows:
The SC2422A Oscillator generates the OUT1 and
OUT2 logic output drives. OUT1 and OUT2 are nonoverlapping and sequentially command an external,
power MOSFET driver to turn on the Top MOSFETs.
When the Top MOSFET is enhanced (each phase),
the input voltage is impressed across the MOSFET
and the output Inductor. The AC current in the inductor
is:
IL
−
=
Tx)VV(
ONOUTIN
L
−
=
FxL
Where F is the frequency (per phase) and L is the output inductor. D is the duty cycle and is approximately
equal to V
. The approximation arises from the
O/VIN
fact that the Duty cycle extends slightly to compensate
for losses in the current path. These losses include
RDS_ON of the MOSFET, the Equivalent Series Resistance of the Inductors and the PCB trace resistances.
Dx)VV(
OUTIN
ramp voltage equals the error amplifier output signal.
The current mode control is inherently immune to input
voltage changes because the ramp amplitude reflects
the input voltage changes.
Since the input current sense resistor is the same for
both phases, the inherent inaccuracy due to mismatch
between output current sense resistors is avoided.
Also, since the comparator threshold is the same for
both phases, accurate current matching is achieved
between phases. This implements a pulse by pulse
current matching with a faster response to changes in
output current by monitoring the input current for each
phase.
Programming the SC2422A
Figure 2 below, is the connection schematic for the Internal Error Amplifier.
Bandgap
1.5V
BGOUT (P15)
Vid0
Vid4
DAC
VOUTFB(P7)
Ri
Figure 2: Error amplifier connections
The external components, R
step size, output voltage offset and droop, accordingly.
A resistor from R
REF
frequency as well as the DAC current step size.
Programming the Switching Frequency
The oscillator frequency can be selected first by setting
the value of R
f
OSC
IN
resistor (pin 8) to ground.
REF
=
V12V
=
3K
E/A
Io
+
-
Ccomp
Ros
ERROUT(P6)
Rcomp
Rf
, R
and RF set the DAC
I
OS
(pin 8) to ground programs the
Ω
kHz500*k13
R
REF
The inductor current flows in the input current sense
resistor, generating a PWM ramp, same as in all cur-
The switching frequency per phase is 1/2 of the above
oscillator frequency.
rent mode controllers. The ramp is compared with an
amplified, level shifted and filtered version of the output
voltage at the PWM comparator. The comparator then
outputs a gate drive pulse that terminates when the
The SC2422A allows programming the output voltage
and the DAC step size by selecting external resistors.
The DAC current step size, for one MSB is:
V
BG
I
where R
=
MSB_DAC
R
REF
is the resistor from R
REF
pin to Ground.
REF
The DAC MSB voltage step size is calculated as follows:
V
DAC_MSB
V
= I
=
LSB_DAC
DAC_MSB
V
32
* R
MSB_DAC
I
or
V
V
LSB_DAC
R
Note that changing R
DAC step size. R
R
BG
REF
I
∗=
32
affects both frequency and
REF
must be proportionally adjusted to
I
keep the same step size at different frequencies. The
advantage of this method is that all new VID specifications can be accommodated by modifying external
components while maintaining the required precision
without the need for converter redesign.
Programming the DAC Offset Voltage
Kirchoff’s current law can be applied to the error amplifier’s Inverting node (see figure 2) to calculate R
OS
, the
DAC offset setting resistor. The output Offset at zero
DAC current (VID=00000), is set as follows:
V
R
=
OS
Where V
EO
BG
VV
−
BGO
+
R
I
VV
−
BGEO
R
F
is the error amplifier output voltage and as
a first approximation is equal to 1.75V.
Where V
The value of R
= Precision Reference Voltage = 1.50V.
BG
can be fine trimmed using a poten-
OS
tiometer connected from the FB pin to ground.
Programming the Dynamic (Active) Droop
The SC2422A employs a novel approach to active
drooping for optimum transient response. The output
voltage is regulated as a function of output current. At
zero current the output is regulated to the upper limit of
the output voltage specification. As the load is increased, the output “droops” towards the lower limit.
This makes optimum use of the output voltage error
band, yielding minimum output capacitor size and cost.
Active drooping, does not compromise the converter
response time as does passive droop techniques. The
active droop also allows for an accurate Inter-Module
current sharing scheme, where multiple DC/DC converters are required to share the current required by a
DC bus. As one module supplies more current, that
modules output voltage ”droops”, allowing other modules to provide the balance of the required current.Any
changes in the output voltage is instantaneously reflected to the error amplifier, which has a high Slew
Rate and wide Gain-Bandwidth product to recover the
output voltage to its nominal level with minimal delay.
The droop is adjusted by setting the feedback resistor,
Rf. While the optimum value of R
may be derived ex-
F
perimentally, the following equation can provide the
droop at a given output current:
I*R*R*G
V
DROOP
=
2
OUTSICA
RF
The Gain of the current amplifier is set to 20 (26dB),
while R
is the input sense resistor.
S
The effective inductance of the sense resistor must be
minimized to achieve accurate correlation between the
above equation and actual droop achieved. This is because the inductive spike, which may also be caused
by layout inductance's, will alter the PWM comparator
trip point. The value of R
may have to be adjusted to
F
compensate for such parasitic effects.
Since Rf also sets the DC gain of the system, changing
the value of Rf affects the offset voltage, which is set
via Ros. The value of Ros can be modified to achieve
exact offset after the droop resistor has been chosen.It
must be noted that the Current Amplifier gain is quite
precise, with greater than 80dB of Common Mode Rejection Ratio (CMRR). Thus the droop’s accuracy is
limited primarily by external components tolerances
and the external parasitic effects.
Loop Gain Considerations
The Modulator gain in Input Current Mode control is
equal to:
0.3V is the ramp added for slope compensation when
the output current is near zero.
The DC loop gain is the product of the modulator gain
and the error amplifier gain and is calculated as follows:
R*V
G
LOOP
=
FIN
R*V
IRAMP
Refer to Application note AN00-1 for detailed treatment
of frequency compensation component selection as well
as programming the SC2422A. The application note is
available on the Semtech website or by contacting the
factory.
Programming the Under Voltage Lock out
The SC2422A may be operated from any supply in +5V
to +12V range. A pin has been dedicated to externally
selecting the voltage at which the SC2422A outputs are
active. A good typical turn-on threshold value is 4.5V for
a +5V input supply and 9V for a +12V supply. A voltage
divider connected to the UVLO pin selects this threshold.
The UVLO comparator trip point is approximately
1.475V. Sufficient hysterisis is provided to ensure
proper DC/DC converter shutdown.
Considerations in Input Current Mode DC/DC Converters”. This application note is available by contacting the factory.
Remote Sensing Capability
The SC2422 has a single ground for error amplifier
and DAC reference and for the internal biasing of the
chip. Since the chip uses approximately 10ma of quiescent current, the ground pin may be connected to a
remote location without fear of ground loops. When
used as a microprocessor power supply, connecting
the ground pin directly to the ground plane may result
in undesirable voltage drops in the plane at high output current. This is not entirely predictable since the
error amplifier is correcting for the DC error with reference with the ground plane and not the processor
“feedback ground”. Thus any voltage difference between the two ground will result in a DC error. This
error will obviously consume valuable static error
band tolerance. To avoid this DC error, the SC2422
ground pin (pin 9) can be connected to a copper
“Island”, to which Rref (frequency setting resistor)
and Ros (offset setting resistor) will also be connected. This “Island” in turn will only be connected to
the “Processor Feedback” ground via a trace. While
the trace may be long, it should not be routed through
or near the switching sections or noisy components.
This method of remote sensing will alleviate the need
for a differential amplifier to sense the output voltage/
output return pair and the design effort and costs associated with it.
The UVLO setting should consider external MOSFET
SC2422A Evaluation Board
driver’s UVLO threshold. Ideally, the external MOSFET
driver should turn on before the SC2422 controller and
turn off before the controller. This assures the converter
output will rise and fall slowly using the soft start feature
and that the output voltage will not go negative at turnoff.
The SC2422A based DC/DC converter utilizes the
SC1205 High Speed MOSFET drivers to achieve
VRM 9.0 output Voltage Specifications. SC2422A
Evaluation Board Schematic (Figure 1) shows the
circuit for a 40A, BiPhase DC/DC converter. The
Evaluation board is available by contacting the fac-
PCB layout
tory or Semtech website at WWW.Semtech.com.
Care must be excercised when laying out the PC board
for SC2422 or other input current mode DC/DC converters. SInce the current is delivered and sensed in pulse
packets, the inductance of the current carrying traces
and thus their length must be minimized. Ceramic bypass capacitors must be located near the sense resistor.
For a detailed treatment and circuit parasitic models,
consult application note: