SEMTECH SH3000 Technical data

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SH3000 User Manual

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Using the SH3000 MicroBuddy™

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SH3000 User Manual

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MicroBuddy, mBuddy, and mB are trademarks of Semtech Corporation. Semtech is a registered trademark of Semtech Corporation. All other trademarks are the property of their respective owners.

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Document Revision History

Revision Date Reason for Changes

Rev. 0.95 2002-08-09 Preliminary draft

SH3000 User Manual

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SH3000 User Manual

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Table of Contents

1.

Introduction ............................................................................................................................................ 1

2. CPU Supervisor ..................................................................................................................................... 4

2.1 Low VDD Reset ...............................................................................................................................5

2.2 Watchdog Timer ............................................................................................................................. 7

2.3 CPU Supervisor Registers .............................................................................................................. 8

3. High-Frequency (HF) Oscillator ........................................................................................................... 10

3.1 Auto Clock Detect Mode ............................................................................................................... 12

3.2 Programmable Spread Spectrum ................................................................................................. 13

3.3 High-Frequency (HF) Oscillator Registers .................................................................................... 14

4. Low-Frequency (LF) Oscillator............................................................................................................. 17

4.1 Low-Frequency (LF) Oscillator Registers ..................................................................................... 18

5. Real-Time Clock (RTC) ....................................................................................................................... 21

5.1 Real-Time Clock (RTC) Registers ................................................................................................ 22

6. Periodic Interrupt/Wake-up Timer........................................................................................................ 23

6.1 Periodic Interrupt/Wake-up Timer Registers ................................................................................ 24

7. Serial Interface ..................................................................................................................................... 25

7.1 Serial Communications Interface.................................................................................................. 25

7.2 Interrupt Interface ......................................................................................................................... 28

7.3 Serial Communication/Interrupt Registers .................................................................................... 28

8. Auxiliary Functions ............................................................................................................................... 30

8.1 Scratchpad RAM and ID number .................................................................................................. 30

8.2 Write Protect Logic ....................................................................................................................... 31

8.3 Voltage Regulator ......................................................................................................................... 33

8.4 Backup Power............................................................................................................................... 33

9. Registers .............................................................................................................................................. 34

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List of Tables

Table 1: SH3000 MicroBuddy™ Pin Descriptions.......................................................................................3

Table 2: Programmable VBO Values (Volts)................................................................................................ 5

Table 3: Operating Parameters for FLL ....................................................................................................11

Table 4: EMI reduction with Spectrum Spreading .....................................................................................13

Table 5: Load Capacitance Settings .........................................................................................................18

Table 6: Minimum/Maximum Serial Bit Timing..........................................................................................26

Table 7: SH3000 MicroBuddy™ Registers 0x00 to 0x0F.......................................................................... 34

Table 8: SH3000 MicroBuddy™ Registers 0x10 to 0x17 ..........................................................................35

Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F.......................................................................... 37

List of Figures

Figure 1: SH3000 MicroBuddy™ Block Diagram ........................................................................................2

Figure 2: CPU Supervisor ...........................................................................................................................4

Figure 3: Operation of Low VDD / Brownout Detector .................................................................................6

Figure 4: Noise Filtering ..............................................................................................................................6

Figure 5: High-Frequency (HF) Oscillator .................................................................................................10

Figure 6: Low-Frequency (LF) Oscillator...................................................................................................17

Figure 7: Real-Time Support: Real-Time Clock (RTC), Periodic Interrupt, & W ake-up Timer .................21

Figure 8: Serial Communication Timing Diagram .....................................................................................27

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SH3000 User Manual

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1. Introduction

The programmable SH3000 MicroBuddy™ (µBuddy™) provides all mandatory microcontroller support functions:

· CPU Supervisor

· Clock Management System

· Real-Time Support

· Auxiliary functions

Three components make a complete system: any microcontroller, the SH3000, and a bypass capacitor. This low-cost system would consume very little power and have clock-frequency accuracy of ±0.5%. A fourth component, a 32.768 kHz watch crystal, raises the clock frequency accuracy to ± 0.0256% (± 256 ppm).

The SH3000 can operate completely stand-alone, or under control of the microcontroller. A single-wire interface handles both bi-directional communications and the interrupt / wake-up signal from the SH3000. The SH3000 stores all configuration, calibration, parameters, and status information in a 36-byte bank of control registers. On reset, most of these are reloaded with defaults from the factory-set One-TimeProgrammable (OTP) memory. The microcontroller can change any settings on the fly. If some of the settings must remain fixed, a comprehensive set of write-protect bits is provided for several related groups of registers (with both permanent write-inhibit and lock/unlock capabilities).

A backup power source may also be connected to the SH3000. The IC can directly accommodate 2/3-cell zinc-carbon/alkaline, 2/3-cell mercury, 2/3/4-cell NiCd/NiMH, 1-cell Li/Li+ batteries, or a super cap.

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Microcontroller

DD

V+

V

32KH

Z

XIN X

OUT

R

ESET

I/O

CLK

V

X

R

BA

V

X

OUT

SEL

REF

REG

2 3

V

4

DD

V

CLK32

13

Regulators &

OUT

CLK

Clock Driver &

Start/Stop Logic

Battery Back-up

SS

1

SS

8

IN

5

Voltage

Reference

LF Oscillator

TAL

X

Post-scaler

HF Oscillator

VDD Monitor

Watchdog

Oscillator

6

& FLL

IN

CLK

1516

OTP Memory

Calibration &

Default Settings

RST

Reset Drivers

11

& Logic

N

RST

10

EST

Control Logic

T

12

Real Time Clock

Select

7

Logic

9

RC

Oscillator

Periodic Interrupt / Wake-up Timer

Interrupt

Serial I/O

IO/I

14

NT

SH3000 µBuddy™

Figure 1: SH3000 MicroBuddy™ Block Diagram

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Table 1: SH3000 MicroBuddy™ Pin Descriptions

Pin Name Type Function

1

V

SS

Power

Ground, 0 V. All VSS pins and TEST (VSS) pin must be connected together. Output of internal voltage regulator, 2.2 V nominal. This pin can power external

2

V

REG

Power

loads of <5 mA. If load is “noisy,” it requires a bypass capacitor. May be left unconnected or used as a high logic level signal for CLK

3

V

DD

Power Main power supply, +2.3 to +5.5 V.

Backup power supply for real-time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical).

4

V

BAK

Power

This voltage can be higher or lower than V

DD. Connect a backup battery or backup

capacitor (with external recharge circuit). Connect to V

5

6

X

IN

OUT

Analog In

Analog Out

Oscillator pins for an optional external low-frequency crystal, typically a 32.768 kHz watch crystal with nominal 12.5 pF load capacitance. Keep open or connect to if not used. A logic low level selects the internal 32 kHz RC oscillator (CLK high state on this pin selects the 32 kHz crystal oscillator (CLK

REG). The SH3000 always starts up using the internal 32 kHz RC oscillator. If

V

7

CLK

SEL

Digital In

SEL is high, the internal 32 kHz clock switches to the crystal oscillator once it

CLK

has stabilized, and RC oscillator is disabled for power conservation. Do not connect CLK

SEL to any signals except VSS or VREG. CLKSEL must not be

left open.

8

9

V

R

SS

REF

Power

Analog

Ground, 0 V. All VSS pins and TEST (VSS) pin must be connected together. Optional 1 MOhm external bias resistor for the internal 32 kHz RC oscillator. Can be used to set, trim or modulate the internal RC oscillator. Keep open if not used. Active low system reset output. Asserted with a strong low state when a reset

10

NRST

Digital Out

condition occurs. Weakly pulled to V valid for V

DD as low as 1 V. Keep open if not used.

DD internally when not active. This signal is

Active high system reset output. Asserted with a strong high state when a reset

11

12

RST

T

EST (VSS)

Digital Out

Digital In

condition occurs. Weakly pulled to V valid for V

DD as low as 1 V. Keep open if not used.

Factory test enable. All VSS pins and TEST (VSS) pin must be connected together.

SS internally when not active. This signal is

Buffered internal 32 kHz clock, derived according to the CLK

DD is not present. When driving high, this

13

CLK32

Digital Out

uses backup power for the buffer when V signal is either at V

BAK or VDD (if VDD is higher than the reset threshold). When

enabled, this signal runs continuously independent of CLK external load to reduce power consumption during backup operations. When disabled, this pin is driven to V

SS. Keep open if not used.

Serial communications interface and interrupt output pin. This pin is internally

14

IO/I

NT

I/O

weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to V inactive. Keep open if not used. Clock activity sense input. Used to detect when the target microcontroller enters

15

CLK

IN

Digital In

stop mode (which disables its clock). Connect to the microcontroller’s clock output or oscillator output pin. Connect to V

SS when not used. CLKIN must not be left

open.

16

CLK

OUT

Digital Out

Programmable high-frequency clock output. Connect to the target microcontroller’s clock input or oscillator input pin. Keep open if not used.

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SEL pin (see below).

DD if not used.

VSS

SEL tied to VSS). A SEL is connected to

SEL pin setting. This pin

OUT activity. Minimize the

DD when

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2. CPU Supervisor

The SH3000 has two CPU Supervisor functions that manage the reset of the host microcontroller, a low-

V

DD monitor (brownout detector) and a watchdog timer (see Figure 2).

Both functions are integrated with the Clock Management System to provide a more complete system solution than stand-alone components.

The SH3000 has both active high and active low reset output pins. Both are driven strong in the active state, and weak in the inactive state. This eliminates the need for external pull-ups and allows various reset sources to be connected together in a wire-OR configuration. (this makes it simple to set up a manual rest circuit.)

A set of flags in the ResetEvent register (R0x1B) indicates the source of the reset to the system software.

R

ESET

DD

Watchdog

Reload Control

Alternating Codes

Logic

0x5A / 0xC3

From / To Serial I/O

RST

11

N

RST

10

V

DD

1

Temperaturecompensated

Voltage

Reference

Lock Logic

Noise Filter

4.40 V

HIGH

2.30 V

LOW

V

Threshold

D/A

Hysteresis

TYP

50mV

Write-once

Initialization Logic

32kHz

PWR

OK

Reset Logic

&

V

Minimum

Duration Timer

U

R

CLK

32kHz

ESET

OUT

/256

NDERFLOW

.

Mode6-bit Value

1→0

7-bit Down Counter

/128

Load

7-bit Watchdog

Timeout Value

Figure 2: CPU Supervisor

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2.1 Low VDD Reset

The SH3000 drives the reset pins active whenever VDD is below the value of VBO, the brownout reset threshold. V from 2.30 V to 4.40 V in average increments of 33.33 mV–see Table 2.

BO can be set using bits 0:5 of the VBOValue register (R0x10). VBO can be set to a value

Table 2: Programmable V

BO Values (Volts)

4.400 4.367 4.333 4.300 4.267 4.233 4.200 4.167

4.133 4.100 4.067 4.033 4.000 3.967 3.933 3.900

3.867 3.833 3.800 3.767 3.733 3.700 3.667 3.633

3.600 3.567 3.533 3.500 3.467 3.433 3.400 3.367

3.333 3.300 3.267 3.233 3.200 3.167 3.133 3.100

3.067 3.033 3.000 2.967 2.933 2.900 2.867 2.833

2.800 2.767 2.733 2.700 2.667 2.633 2.600 2.567

2.533 2.500 2.467 2.433 2.400 2.367 2.333 2.300

The default V

BO value is loaded on power-up from the factory-programmed OTP nonvolatile memory. It

can be re-programmed at any time or it can be permanently protected from any changes by setting the

V

BO lock flag or an OTP write-protect flag.

On power up, both the active high and active low reset pins are driven active. These outputs are typically valid for a V

DD level of at least 0.5 V, and guaranteed to be valid for a VDD level of 1.0 V.

The reset output pins remain active until V

HYST is a small fixed amount of hysteresis, nominally 50 mV. This hysteresis is added to prevent false

V

DD rises and stays above the level of VBO + VHYST, where

triggering from noise or small power glitches.

At the threshold level (V

BO + VHYST), the power supply is considered valid. On initial power up, the reset

lines become inactive 3–5 ms after power is valid. In the case of brownout, the reset is released after a delay of 6 ms, but no less than 12 ms from the moment brownout has been detected.

Such a fast reset is possible because the SH3000 provides a fast-starting clock that is free of crystal startup time delays. This gives the SH3000 an advantage over other external reset circuits, which must have a long reset pulse duration to accommodate long and unpredictable crystal start-up times.

The SH3000 guarantees that before the reset signals are inactive a valid and stable clock is available for at least 1 ms on power up, or 2 ms after brownout, so that internal synchronous reset and initialization of the host microcontroller can proceed normally.

With the clock becoming active 1-2 ms before the reset lines become inactive, considerable energy is conserved since the clock is not active during the whole reset period.

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When a brownout event occurs, the SH3000 continues to provide the clock to the host microcontroller, but at a reduced frequency between 500 kHz and 1.0 MHz. After a delay of 2 ms this clock is stopped, automatically lowering the energy consumption of the whole system; see Figure 3.

A noise filter prevents the reset lines from going active due to noise and power glitches on the V

Figure 4 shows typical behavior for the V

DD level just above VBO for negative-going spikes of various

DD line.

duration and amplitude.

12ms minimum

6ms

10

Duration

Amplitude

5

VDD

RST

V

BO

+ V

HYST

V

BO

1V

3-5ms

Guaranteed reset

Duration, µs

N

RST

Undefined

Guaranteed NO reset

Normal

CLK

OUT

F

OUT

Figure 3: Operation of Low V

2ms2ms1ms

Reduced F

0.5-1.0 MHz

DD / Brownout Detector Figure 4: Noise Filtering

OUT

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

Amplitude , V

When V

DD power is removed from the chip, the following sequence of events occurs:

1. When V reset lines are guaranteed to become active within 5 µs after V

DD drops below the programmed reset threshold, NRST and RST are asserted. Both

DD has crossed the VBO threshold.

2. If V

BATT is above 1.5 V to 2.2 V, then the chip switches on to VBATT operation; NRST and RST

remain asserted

3. CLK

OUT continues to run at a reduced rate (500 kHz to 1 MHz), provided that VDD stays above

approximately 2.25 V. If V immediately. If CLK

DD falls below this threshold at any time, then CLKOUT is stopped

OUT was inactive when the reset condition occurred, it is activated at this

time.

4. If enabled, the CLK32 output continues normal operations when V

DD is absent and backup power

is available.

5. 2 ms after V

DD drops below the VBO threshold, CLKOUT switches off.

The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in the ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared individually by writing a “1” to the relevant bit position; they are not cleared automatically. On a power-on reset (bit 0), the brownout flag (bit 3) is invariably set also.

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2.2 Watchdog Timer

The Watchdog Timer is part of the CPU Supervisor function of the SH3000. Whereas the low-VDD Brownout Detector monitors supply voltage, the watchdog timer monitors behavior of the host microcontroller. It is based on a programmable timer that must be restarted periodically by the host. If the host does not send a command to restart the timer (which is likely when the host firmware has hung or failed), the watchdog resets the host.

The watchdog is disabled after reset occurs. It stays disabled until initialized by the host microcontroller. The initialization requires the watchdog clock mode to be selected (see Figure 2) and the 7-bit time-out value to be set. Once the time-out value is written, the watchdog begins operations and cannot be stopped; the time-out value and clock source can no longer be changed.

The two clock sources available for the watchdog are the internal 32 kHz clock and the CLK

The time-out interval can be set with bits 0:6 of the WdogPeriod register (R0x1D). When operating from the 32 kHz source, the time-out interval is programmable from 7.8125 ms to 1000 ms with a resolution of

7.8125 ms. Since the internal 32 kHz clock is running all the time, the time-out period is fixed and predictable.

When operating from the CLK cycles with a resolution of 256 cycles. The actual time-out duration is variable; it depends both on the frequency of CLK the CLK

These two clock modes, together with the programmable time-out value, allow the SH3000 exceptional flexibility previously unattainable by discrete watchdog solutions.

The watchdog timer is kept from timing out by periodic writing of a code to the WdogCode register (R0x1C). As a safety measure, the code values must be alternated between 0x5A and 0xC3. The first code written to the register must be 0x5A; at the next period, the code 0xC3 must be used, and so forth. The timer is reloaded after every write of the correct one of these codes.

If the watchdog code is not written before the time-out period expires, or if the code is incorrect or out of sequence, the SH3000 issues a reset to the microcontroller by asserting both the RST (pin 11) and (pin 10) lines. The reset state is asserted for 6 ms.

OUT signal is also stopped. When the CLKOUT signal is stopped, the watchdog is suspended.

OUT and the amount of time the host microcontroller spends in the STOP mode, when

OUT signal, the time-out period is programmable between 256 and 32768

OUT signal.

NRST

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2.3 CPU Supervisor Registers

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ADDRESS

0x0E

0x10

0x17

Config

ADDRESS

0 VBOValue

0 WP_PostScale

PAGE

NAME

RESET EVENT

PowerOn

WDog

BrownOut

P PW B PW B PW B

PW B PW B PW B

PW B

INIT

EVENT

PowerOn

WDog

P W P W P W P W P W P W

P W P W P W P W P W B P W B P W B P W B

RESET VALUE

DESCRIPTION

HEX

BINARY

1 b7

XTALtune Rewrite-Once Enable (see notes for use) 0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

0x88

1b3CLK 0 b2 W dogClkSelect. 1 = CLK

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

OUT

, 0 = 32 kHz.

0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0. 0 b0 Interrupt Enable. 1 = enable, 0 = disable.

INIT

VALUE

WRITE

PROTECT

DESCRIPTION

Value

BO

BrownOut

HEX

BINARY

IDCode

-0-

? ?

0x??

? ? ?

V V V V V V

?

? b7 ? ? ?

0x??

? A b3 CLK32 enable, 1 = enable, 0 = disable. ? A b2

? A b1 ? A b0

Calibration

Application

Xtal REWRITE-once

V

b7 Reserved, not used b6 Reserved, not used

b5 b4

BO

V

b3

~33.33 mV steps.

b2 b1 b0

IDCode Write Protect, 1 = no writes. Calibration Write Protect, 1 = no writes.

b6

pplication Write Protect, 1 = no writes.

b5

BO

V

b4

DCO Post-Scaler, 8 (eight) setting:

/1, 2, 4, 8, 16, 32, 64, 128.

Threshold Value, 2.3 V to 4.4 V in

Value Write Protect, 1 = no writes.

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Note: The four bit flags 0:3 (Power-on reset, watchdog code violation, watchdog timeout, and brownout) in the ResetEvent register (R0x1B) reflect reset history. This register is readable, and may be cleared individually by writing a “1” to the relevant bit position; they are not cleared automatically. On a power-on reset (bit 0), the brownout flag (bit 3) is invariably set also.

ADDRESS

0x1B

0x1C

0x1D

RESET EVENT

RESET VALUE

NAME

PowerOn

WDog

BrownOut

0x02 0x04

ResetEvent

P B

W W

P

WDogCode P W B

P W B P W B

WDogPeriod

P W B P W B P W B P W B P W B

0x08

or

0x09

0x00

DESCRIPTION

HEX

BINARY

-0-

b7

-0-

b6

-0-

0/1 b3 V 0/1 b2 Watchdog code violation caused the reset. 0/1 b1 Watchdog timeout caused the reset. 0/1 b0 Power-on caused the reset.

-0-

Reserved, not used

b5 b4

DD

dropped below VBO threshold (brown-out).

Alternate writes of code-Bytes 0x5A and 0xC3 are required to prevent timeout. Watchdog is reloaded after every write (only one code has to be written to reload the watchdog, but the value of the code-Byte has to alternate between 0x5A and 0xC3).

b7 Reserved, not used

0b6

Watchdog timeout value. Depending on WdogClkSelect bit

0b5

in the Config register (R0x0E, b2), the watchdog will be decremented by either a 32 kHz clock or the signal on the

0b4

CLK

OUT

0b3

when the HFCLK stops). The Watchdog is disabled after the

0b2

reset and started by writing to WDogPeriod. Once started,

0b1

the clock selection or timeout value cannot be changed.

0b0

pin (in which case the watchdog will be suspended

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3. High-Frequency (HF) Oscillator

The frequency synthesizer in the SH3000 is constructed from the 2:1 digitally-tunable 8.0–16.0 MHz HighFrequency (HF) oscillator followed by a programmable binary post-divider; see Figure 5.

Clock On

Clock Buffer

and Glue

Logic

HF Digitally

Controlled

Oscillator

8-16 MHz

TART/STOP

S

CLKOUT

16

CLKIN

15

Force

DCO On

32.768 kHz

/16

2048 Hz

From / To Serial I/O

Frequency Locked Loop

Logic

13-bit

Frequency

Set value

FLL Enable

Post-scaler

(Divide by 1, 2, 4,

8, 16, 32, 64, 128)

18-bit

DCO Code

Register

8-bit Pseudo

Random Noise

Generator

Clock Source

1

0

Spectrum

Spreading

Controls

Figure 5: High-Frequency (HF) Oscillator

The Clock Source selector and the programmable Post-scaler allow instantaneous switching between the 32 kHz internal clock and the divided-down HF oscillator output. There is no settling or instability when the switch occurs.

The SH3000 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32 kHz reference. This architecture has several advantages over the common PLL (Phase Lock Loop) systems, including the ability to stop and re-start without frequency transients and instability, and with instant settling to a correct frequency. The conventional PLL approach invariably includes a low-pass filter that requires a long settling time on restart.

When the HF oscillator is operating without FLL control, it can set the frequency of the clock on the

OUT pin to ±0.025%, and maintain it to ±0.5% over temperature.

CLK

When the HF oscillator is operating under FLL control, the absolute accuracy and stability of the HF clock depends on the quality of the 32.768 kHz internally generated clock. An external 32.768 kHz watch crystal used as a reference provides excellent accuracy and stability for the SH3000.

The primary purpose of the FLL is the maintenance of the correct frequency while the ambient temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action from the FLL system is also small and gradual, in proportion with the changes in temperature.

To set a new frequency for the FLL, the host microcontroller writes the 13-bit Frequency Set value to the appropriate bits in registers SS_FreqSet (R0x15) and FreqSetLSB (R0x16); it may also update the postscaler setting in the WP_PostScale register (R0x17). The resulting output frequency is calculated using simple formulas [1] and [2] (reference frequency is 32.768 kHz):

OSC = 2048 Hz * (Frequency Set value + 1) [1]

F

OUT = FOSC / (Post-divider setting) [2]

F

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For example, a post-divider setting of /8 and the Frequency Set value of 4000 (0x0FA0) produce an output frequency of 1.024 MHz. Table 3 shows the available frequencies with the corresponding resolution at high and low frequency limits.

Table 3: Operating Parameters for FLL

Post-

divider

Frequency Resolution

Hz

(Guaranteed)

Frequency Range

High

(Guaranteed)

Hz

Low

Hz

Low

(Typical)

Hz

/1 2048 16,777,216 7,999,488 6,144,000 /2 1024 8,388,608 3,999,744 3,072,000 /4 512 4,194,304 1,999,872 1,536,000

/8 256 2,097,152 999,936 768,000 /16 128 1,048,576 499,968 384,000 /32 64 524,288 249,984 192,000 /64 32 262,144 124,992 96,000

/128 16 131,072 62,496 48,000

Frequency Set

value

Resolution

Dec

Hex 0x1FFF

%

ppm

8191 3905 2999

0x0F41 0x0BB7

0.01221 0.02560 0.03333 122 256 333

When the Frequency Set value changes, the FLL synthesizer needs some settling time to lock the new frequency. There are several possible methods for decreasing this time:

1. The host microcontroller may simply wait for the FLL to lock, checking the FLL lock flag (bit 0) in the Status register (R0x1A). This approach is the simplest but also the slowest. Depending on the frequency step it may take up to two seconds to obtain the lock. The frequency change from the old to the new value is slow and gradual.

2. The host may issue a Coarse Lock command by setting the coarse lock bit (bit 1) in the FLLcontrol register (R0x0F). The SH3000 performs a successive approximation algorithm on the 18-bit DCO (digitally controlled oscillator) code value (contained in registers R0x13, R0x14, and R0x18) and finds a locked setting in approximately 25 ms. The clock may experience frequency fluctuations of up to 2:1.

3. If the frequency step is small (less than 256 kHz at the undivided output of the HF oscillator), the host may issue a fine lock command by setting the fine lock bit (bit 2) in the FLLcontrol register. The SH3000 performs a successive approximation algorithm on the 7 least significant bits of the 18-bit DCO code value, and finds a locked setting in approximately 5 ms. The clock may experience the maximum frequency fluctuations of only 3.2%.

4. The host may write the new value into the DCO code registers to directly control the frequency of the HF oscillator. This method is preferable and results in minimum settling time. The 18-bit DCO code value can be obtained from programming the HF oscillator to a correct frequency using method 2 or 3 above (at start-up or at some point in the operation), reading the value from the DCO code registers, and storing the value in the host’s memory. This calibration should be performed for each of the frequencies to be employed. This method allows the locking time to be as small as 1 or 2 ms, independent of the frequency step.

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5. The host may perform a custom or proprietary algorithm for frequency control; the SH3000 provides all of the information, reference, and timing signals needed.

During each of the settling methods described above, the processor clock can be switched to 32 kHz, and would be completely free of any frequency fluctuations or instabilities. Since the SH3000 automatically shuts down the HF oscillator when 32 kHz is selected as the output frequency, the HF oscillator should be forced to an active state by setting the Force DCO On bit (bit 5) in the Config register (R0x0E).

Systems requiring a very stable clock for short periods of time (controlling an integrating D/A converter, for example), may stop the FLL action in the SH3000 by resetting the FLL enable bit (bit 0) in the FLLcontrol register (R0x0F).

3.1 Auto Clock Detect Mode

The SH3000 HF oscillator block has two main modes with which to operate.

1. Mode 1 provides a system clock source. In this mode the CLK

OUT pin supplies a clock at the

frequency configured by the register settings. It can be enabled/disabled by setting/resetting the

CLK

OUT pin enable bit (bit 3) of the Config register (R0x0E).*

2. Mode 2 provides a CPU oscillator source. In this mode, the CLK

OUT pin supplies a clock

frequency configured by the register settings. It can be enabled/disabled by setting/resetting the

CLK

OUT pin enable bit of the Config register.* When the host microcontroller enters stop mode,

the SH3000 CLK shuts down the CLK configures the CLK interrupt signal, the CLK

IN pin detects the absence of transitions from the host oscillator output pin, and

OUT pin within four clock cycles to save power. At this time the SH3000

OUT pin in such a way that as soon as the host exits stop mode via a reset or

IN pin receives a transition. When this occurs, the SH3000 restarts the

clock within 2 ms. This happens much faster than with a standard crystal or a ceramic resonator, faster even than with an LC tank circuit. This is a key feature of low-power operation of the SH3000.

The operating mode is determined by CLK

IN. If the SH3000 detects at least four transitions on the CLKIN

pin, it assumes Mode 2 is in effect and configures itself to auto-clock detect. This also sets the corresponding bit (bit 4) in the Status register (R0x1A).

* As programmatically disabling the CLK

OUT pin causes the clock to be irrecoverable, the periodic timer

must be set and enabled before this is done. The SH3000 does not disable the clock unless the periodic timer is enabled.

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3.2 Programmable Spread Spectrum

The SH3000 offers a technique for reducing electromagnetic interference (EMI). It can be a part of the initial design strategy, or it can be applied in the prototype stage to fix problems identified during compliance testing. This feature of the SH3000 may greatly reduce the requirements for radio frequency (RF) shielding, and permits the use of simple plastic casings in place of expensive RFI-coated or metal casings.

The SH3000 employs programmable spectrum spreading to reduce RF emissions from the processor’s clock. There are five possible settings; see Table 4 for operating and performance figures in the 8–16 MHz range.

Spectrum spreading is implemented by varying the frequency of the HF oscillator with a pseudo-random sequence (with a zero-average DC component). The Maximum-Length Sequence (MLS) 8-bit random number generator, clocked by 32 kHz, is used. Only 4, 5, 6, or 7 bits of the generated 8-bit random number are used, according to the configuration setting.

Maximum fluctuations of the frequency depend on the selected frequency range and the position within the range. Selecting the HF oscillator frequency near the high end of the range limits the peak variations to ±0.1%, ±0.2%, ±0.4%, or ±0.8%.

The spread spectrum values are set in the SS_FreqSet register (R0x15). Bit 5 enables spectrum spreading, and bits 7:6 specify the spreading bandwidth.

Table 4: EMI reduction with Spectrum Spreading

Peak EMI

Reduction

(guaranteed)

db

b6

Spreading

Bandwidth

kHz

Setting

En

CFG1

b5

0 X X Off 0 0

1 0 0 32 -3 -3

1 0 1 64 -6 -7

1 1 0 128 -9 -10

1 1 1 256 -12 -15

CFG0

b7

Peak EMI

Reduction

(measured)

db

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ADDRESS

0x0E

0x0F

Config

FLLcontrol

NAME

RESET EVENT

RESET VALUE

DESCRIPTION

PowerOn

WDog

BrownOut

HEX

BINARY

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B PW B

PW B PW B PW B

PW B

PW B PW B PW B

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

0x88

1b3CLK 0 b2 WdogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

-0-

b7 Reserved, not used

-0-

b6 Reserved, not used

-0-

0x00

or

0x01

b5 Reserved, not used

-0-

b4 Reserved, not used

-0-

b3 Reserved, not used

0 b2 Start FLL fine frequency lock (~5 ms to achieve lock). 0 b1 Start FLL coarse frequency lock (~25 ms to achieve lock).

0/1 b0 Enable FLL. 1 = enabled, 0 = disabled. On Reset =pin CLK

OUT source. 1 = 32 kHz, 0 = HFCLK. OUTEnable. 1 = enable, 0 = disable.

OUT, 0 = 32 kHz.

SEL.

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ADDRESS

0x13

0x14

0x15

0x16

0x17

INIT

EVENT

NAME

PAGE

PowerOn

WDog

BrownOut

P

W

P

W

P

W

P

0 VREF_DCOcode

0 DCOcode1 P W B

0 SS_FreqSet

0 FreqSetLSB P W B

0 WP_PostScale

W

P W B

P W B P W B P W B

P W B P W B P W B P W B P W B

P W P W P W P W P W B P W B P W B P W B

INIT

VALUE

WRITE

PROTECT

DESCRIPTION

Value

BO

HEX

BINARY

IDCode

Calibration

C

?

C

?

C

?

C

?

0x??

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

? b7 ? ? ? ? A b3 CLK32 enable, 1 = enable, 0 = disable. ? A b2 ? A b1 ? A b0

Application

Xtal REWRITE-once

V

b7

Adjustment for internal temperature-

b6

compensated Voltage Reference,

b5

Factory-Only temperature drift trim.

b4

Disconnect Internal R

b3

0=connected, 1 = disconnected.

b2

DCO setting,

b1

most-significant bits 15:17.

b0

Bits 7:14 of DCO setting

b7

Amount of HFCLK Spectrum Spreading, 4 (four) settings.

b6 b5 EnableSS, enable spectrum spreading.

b4 b3

Frequency Set Value for FLL, most-

b2

significant bits 8:12

b1 b0

Frequency Set Value for FLL, bits 0:7.

IDCode Write Protect, 1 = no writes. Calibration Write Protect, 1 = no writes.

b6

pplication Write Protect, 1 = no writes.

b5

BO Value Write Protect, 1 = no writes.

V

b4

DCO Post-Scaler, 8 (eight) setting:

/1, 2, 4, 8, 16, 32, 64, 128.

REF,

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ADDRESS

0x18

0x1A

NAME

DCOcodeLSB

Status

RESET EVENT

PowerOn

WDog

BrownOut

P W B P W B P W B P W B P W B P W B P W B

P W B

P W B P W B P W B P W B P W B

RESET VALUE

DESCRIPTION

HEX

BINARY

-0-

b7 Reserved, not used

1b6 0b5 0b4

0x40

-0-

0x00

DCO setting,

0b3

least-significant bits 0:6

0b2 0b1 0b0

0 b7 Xtal oscillator is stable

b6

Reserved, not used

b5

Auto CLK shut-down mode (transitions on CLKIN detected).

0b4 0 b3 Backup battery low. 0 b2 Serial I/O parity error. 0 b1 Interrupt status (1 = pending, 0 = idle). 0 b0 FLL locked (1 = locked, 0 = unlocked).

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4. Low-Frequency (LF) Oscillator

The Low Frequency (LF) Oscillator System provides the 32 kHz clock to all internal circuits and to the dedicated output pin, CLK32. The 32 kHz clock can also be output to the CLK the Config register (R0x0E).

OUT pin by setting bit 4 in

If enabled, the CLK32 output continues normal operations when V available; in this case, the output voltage swings between zero and V

DD is absent and backup power is

BATT.

When power is first applied to the SH3000, the RC oscillator takes over. It supplies the 32 kHz clock for start-up and initialization. However, if the CLK

SEL pin is set high, then the crystal oscillator is enabled.

Once the crystal has started and stabilized, the internal 32 kHz clock switches to the very accurate crystal frequency (and the xtal oscillator stable bit, bit 7 in the Status register R0x1A, is set). See Figure 6.

X

IN

5

32768 Hz

Watch Crystal

12.5 pF Load Capacitance

V

REG

-

TAL

RC

External

Reference

Resistor

1M 1% or

variable

CLK

X

OUT

6

SEL

7

R

REF

I

NTERNAL

R

REF ON

9

V

SS

Lock / Unlock

8

V

SS

Logic

4-bit Value 6-bit Value 4-bit Value

1

X-tal stable?

RC

Oscillator

Internal R

REF

Lock Logic

CLK32 O

Internal

32 kHz

Clock

From / To Serial I/O

N

CLK32

13

Figure 6: Low-Frequency (LF) Oscillator

The default calibration values for the RC oscillator are loaded on power-up from the factory-programmed OTP non-volatile memory. They can be reprogrammed at any time, or they can be permanently protected from any changes by setting the Lock flag or an OTP write-protect flag. Factory calibration brings the frequency of the RC oscillator within +/- 3 % of the 32768 Hz for the internal reference resistor, and 2% for the external 1M 1 % resistor, over the entire temperature and supply voltage range.

The frequency of the RC oscillator can be tuned or modulated by varying the external reference resistor,which should be located as close as possible to R

REF, pin 9, to minimize noise pickup.

The crystal oscillator has the unique feature of adjustable load capacitors. It permits tuning of the circuit for initial tolerances of the crystal (often +/- 20 ppm) as well as an adjustment for the required load capacitance (with possible variations from the PCB layout). While the oscillator was designed for a crystal with a nominal load capacitance of 12.5 pF, the circuit accommodates any value from 7–22 pF (depending on parasitics of the layout). All of these corrections can be performed when the part is already installed on the PCB in the actual circuit.

The default value for load capacitance (12.5 pF) loaded on power-up from the factory-programmed OTP non-volatile memory can be re-programmed at any time, or it can be completely protected from any changes by a permanent OTP write-protect flag.

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To reprogram the load capacitance, clear the XTALtune Rewrite-Once Enable bit (bit 7) of the Config register (R0x0E) and then immediately set bits 7:4 of the register Xtune_R desired value; Table 5 shows the available values.

Table 5: Load Capacitance Settings

REFAdj (R0x12) with the

Xtune

code

Padding

capacitance

(pF)

Effective

crystal load

capacitance

Effective

ppm

adjustment

(pF)

0000 26 13 -4 0001 28 14 -10 0010 30 15 -16 0011 32 16 -21 0100 34 17 -26 0101 36 18 -31 0110 38 19 -35 0111 40 20 -37 1000 10 5 118 1001 12 6 91 1010 14 7 70 1011 16 8 52 1100 18 9 36 1101 20 10 23 1110 22 11 15 1111 24 12 4

The adjustment can set the frequency of the crystal oscillator to within +/- 4 ppm of the ideal value. As a reference, a typical 32.768 kHz crystal changes its frequency 4 ppm for a 10°C change in temperature. Since the temperature characteristics of crystals are well known and stable, the host microcontroller is free to implement an algorithm for temperature compensation of the crystal oscillator using the adjustable load capacitors, with the resulting accuracy of +/- 4 ppm over the entire temperature range.

4.1 Low-Frequency (LF) Oscillator Registers

RESET EVENT

NAME

ADDRESS

0x0E

Config

PowerOn

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B PW B

PW B PW B PW B

PW B

WDog

RESET VALUE

BrownOut

HEX

0x88

DESCRIPTION

BINARY

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

1b3CLK 0 b2 W dogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

OUT

, 0 = 32 kHz.

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ADDRESS

0x11

0x12

0x13

0x17

NAME

PAGE

0 IPol_RCtune

0 Xtune_R

0 V

REF

Adj

_DCOcode

0 WP_PostScale

INIT

EVENT

PowerOn

WDog

BrownOut

P W B P W B

P W B P W B P W B P W B P W B

P P P P

P W B P W B P W B P W B

W

P P

W

P

W

P

W

P W B

P W B P W B P W B

P W P W P W P W

P W B P W B

INIT

VALUE

WRITE

PROTECT

DESCRIPTION

Value

BO

HEX

BINARY

IDCode

Calibration

Application

-0-

A

?

C

?

C

?

0x??

C

?

C

?

C

?

C

?

R

?

R

?

R

?

R

?

C

?

C

?

C

?

C

?

C

?

C

?

C

?

C

?

A

?

A

?

A

?

A

?

? b7

0x??

? ? ? ? A b3 CLK32 enable, 1 = enable, 0 = disable. ? A b2 ? A b1 ? A b0

Xtal REWRITE-once

V

b7 Reserved, not used

b6 Interrupt Polarity, 1 = High, 0 = Low. b5

b4

32 kHz RC Oscillator Adjustment,

b3

nominal ~330 Hz per step.

b2 b1 b0

b7

32.768 kHz Xtal Oscillator fine tune

b6

(see notes for use)

b5 b4

b3

Internal R

b2

nominal ~330 Hz per step.

b1

REF

Adjustment,

b0

b7

Adjustment for internal temperature-

b6

compensated Voltage Reference,

b5

Factory-Only temperature drift trim.

b4

Disconnect Internal R

b3

0=connected, 1 = disconnected.

b2

DCO setting,

b1

most-significant bits 15:17.

b0

IDCode Write Protect, 1 = no writes. Calibration Write Protect, 1 = no writes.

b6

pplication Write Protect, 1 = no writes.

b5

BO

Value Write Protect, 1 = no writes.

V

b4

DCO Post-Scaler, 8 (eight) setting:

/1, 2, 4, 8, 16, 32, 64, 128.

REF

,

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0x1A

ADDRESS

Status

NAME

RESET EVENT

PowerOn

WDog

BrownOut

P W B

P W B P W B P W B P W B P W B

RESET VALUE

DESCRIPTION

HEX

BINARY

0 b7 Xtal oscillator is stable

-0-

b6

-0-

0x00

Reserved, not used

b5

Auto CLK shut-down mode (transitions on CLKIN detected).

0b4 0 b3 Backup battery low. 0 b2 Serial I/O parity error. 0 b1 Interrupt status (1 = pending, 0 = idle). 0 b0 FLL locked (1 = locked, 0 = unlocked).

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5. Real-Time Clock (RTC)

The Real-Time Clock (RTC) feature uses the internal 32 kHz clock from the low-frequency (LF) oscillator. As shown in Figure 7, the RTC divides the 32 kHz clock by 128 to produce a 256 Hz clock. The next divider is a modulo-256 counter, which is readable and write-able from the serial interface. The next stage is a divide by 60, which provides seconds in BCD format. Another divide-by-60 counter provides minutes in BCD, followed by a divide-by-24 counter that provides hours in 24-hour mode in BCD format. This in turn clocks a 16-bit binary counter, which can log up to 65535 days (over 179 years).

Using a 4 ppm 32.768 kHz clock from the LF oscillator, the RTC module keeps time with a maximum error as low as 2 minutes per year.

Current Timer

Value

Interrupt

Logic

Serial I/O

IO/IN

14

32768 Hz

/256

Fractions

(BIN)

0 - 255

LSB

/128

1 Hz

/60 /60 /24

Seconds

(BCD)

0 - 59

Minutes

(BCD) 0 - 59

Hours

(BCD)

0 - 23

16-bit Counter

Days (BIN)

0 - 65535

LSB MSB

LOAD

32-bit Latch

32-bit Counter

RESET

32-bit Comparator

LOAD

32-bit Latch

32-bit Time Interval

LSB MSB

Figure 7: Real-Time Support: Real-Time Clock (RTC), Periodic Interrupt, & Wake-up Timer

BAK pin can be connected to a backup power supply for the real-time clock, +2.3 to +5.5 V (+1.8 to

The V +5.5 V typical). This voltage can be higher or lower than V

DD. Connect a backup battery or backup

capacitor (with external recharge circuit).

When reading the RTC registers (R0x08–R0x0D), the register RTCsubseconds (R0x0D) should be read first. When the register RTCsubseconds is read, all six bytes of the RTC counters are latched into the holding registers simultaneously. This avoids problems of counter overflows between individual byte reads.

The RTC registers can be written to in any order. Only when the register RTCsubseconds is written are the entire six byte loaded into the RTC counters.

Note: Check the SH3000 Errata document.

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5.1 Real-Time Clock (RTC) Registers

RESET EVENT

RESET VALUE

SH3000 User Manual

Preliminar

ADDRESS

0x08

0x09

0x0A

0x0B

0x0C

0x0D

NAME

PowerOn

WDog

BrownOut

HEX

RTCdaysMSB P W

RTCdaysLSB P W

RTChours W

RTCminutes P W

RTCseconds P W

RTCsubseconds P W

0x00

0x00 BCD value, 0 to 23.

P

0x00 BCD value, 0 to 59.

0x00 8-bit binary value, 0 to 0xFF (0 to 255)

DESCRIPTION

BINARY

16-bit binary value, 0x0000 to 0xFFFF (0 to 65535, ~ 179.5 years).

When RTCsubseconds is read, all RTC registers are updated. When RTCsubseconds is written,

the whole RTC

counter chain is loaded.

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6. Periodic Interrupt/Wake-up Timer

The periodic interrupt / wakeup timer can be used to create very accurate recurring interrupts for use by the host microcontroller. W ith some minimal software support, it can also be used to create alarms, with practically unlimited duration.

While the timer is running, the host can switch to a low-power mode (halted or stopped). The interrupt wakes up the host, which can perform the requisite task and go back to sleep, until the next periodic interrupt. This mode of operation can achieve extremely low average power consumption.

As shown in Figure 7, a 32-bit counter is clocked by 32.768 kHz, producing a minimum interval of 30.5 µs and a maximum interval of 36.4 hours.

After reset, the timer is stopped until the new 32-bit value for the timer interval is written into the four Period registers (R0x00-R0x03). When the least significant byte (the PeriodLSB register, R0x03) is written, the whole value is moved to the Timer Interval latch, the counter is reset, and the counter starts to increment with the 32 kHz clock.

When the 32-bit comparator detects a match, an interrupt is generated, and the counter is reset and starts the next timing cycle.

Although the counter cannot be written to, the current value from the counter can be read at any time. The whole 32-bit value is loaded into the 32-bit Timer Interval latch when the least significant byte is read. This prevents errors stemming from the finite time between the readings of individual bytes of the current value.

If there is an interrupt pending from the SH3000, and the host microcontroller does not clear the interrupt pending bit, then the SH3000 issues an interrupt after each subsequent read or write cycle until this bit is cleared (see Figure 7).

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6.1 Periodic Interrupt/Wake-up Timer Registers

Preliminar

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x0E

RESET EVENT

RESET VALUE

NAME

PowerOn

WDog

BrownOut

HEX

BINARY

PeriodMSB W B

Period2 W B

Period1 W B

PeriodLSB W B

TimerMSB W B

Timer2 W B

Timer1 W B

TimerLSB W B

Config

P

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B PW B

PW B PW B PW B

PW B

0x00

0x88

Periodic Interrupt / Wake-up Timer setting. With 32.768 kHz clock the period = (32-bit value)/32768. When the value = 0, the Timer is disabled. The whole 32-bit value is loaded into timer logic when PeriodLSB is written.

Free-running counter. This counter is reset when the PeriodLSB is written (Timer started) or the value of the counter is equal to 32bit Period value (Interrupt / Wake-up generated). The whole 32-bit Timer value is loaded into Timer registers when TimerLSB is read.

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

1b3CLK 0 b2 WdogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

DESCRIPTION

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

OUT

, 0 = 32 kHz.

ADDRESS

0x1A

Status

NAME

RESET EVENT

PowerOn

WDog

BrownOut

P W B

P W B P W B P W B P W B P W B

RESET VALUE

DESCRIPTION

HEX

BINARY

0 b7 Xtal oscillator is stable

-0-

b6

-0-

0x00

Reserved, not used

b5

Auto CLK shut-down mode (transitions on CLKIN detected).

0b4 0 b3 Backup battery low. 0 b2 Serial I/O parity error. 0 b1 Interrupt status (1 = pending, 0 = idle). 0 b0 FLL locked (1 = locked, 0 = unlocked).

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7. Serial Interface

7.1 Serial Communications Interface

The SH3000 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. The bit rate is automatically determined by the SH3000. The SH3000 contains 36 addressable registers located at 0x00–0x1F; see the Registers chapter of this manual. Some of these registers are accessed through a page operation. Pin 14, IO/I and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to V inactive.

As shown in Figure 8, the SH3000 and the host communicate with serial data streams. The host always initiates communication. A data stream consists of the following (in this order):

· 3-bit start field

· 3-bit read/write code

· 5-bit address field

· 1 guard bit

· 8-bit data field

· 2 parity bits

Plus, for write streams only:

· 1 guard bit

· 2 acknowledge (ACK) bits

The 3-bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream.

NT, is the serial communications interface

DD when

The 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. This protects against early glitches hat might otherwise put the interface into an invalid read or write access mode.

The 5-bit address field contains the address of the register.

A single guard bit gives the interface a safe period in which to change data direction. The value of a guard bit does not matter.

The 8-bit data field is written to (read from) the register.

Two parity bits: The first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit is the inverse of the first.

For write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write access.

Two guard bits are appended to the end of the access stream (read or write). The host can not start the next access before receiving these bits.

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The interface is self-timed based on the duration of the start bit field, and communication can take place whenever CLK running synchronously to the CLK then a minimum of 4 CLK serial interface is asynchronous to CLK maximum of 1024 CLK

OUT is active, either at 32 kHz or at a higher frequency. If the host microcontroller is

OUT generated by the SH3000 (which should generally be the case),

OUT cycles per bit are required to maintain communication integrity. If the host’s

OUT, then a minimum of 52 cycles per bit are necessary. A

OUT cycles per bit field is supported.

Table 6 displays the minimum and maximum bit periods for the serial communications for CLK frequencies of 16 MHz, 8 MHz, and 2 MHz.

Table 6: Minimum/Maximum Serial Bit Timing

CLKOUT

Frequency

16 MHz 250 ns

8 MHz 500 ns 2 MHz

Minimum Bit

Period

(host

synchronous

to

CLKOUT)

2 ms 13 ms 255 ms

Minimum Bit

Period

(host

asynchronous

to

CLKOUT)

1.625 ms 32 ms

3.25 ms 63.9 ms

Maximum Bit

Period

OUT

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Figure 8: Serial Communication Timing Diagram

g-start

ACK0 ACK1

XXX

P0 P1

Pendin

IN

T

Guard2 Guard3

ACK0 ACK1

Guard1

P0 P1

Guard3

Guard2 Idle

g-start

Pendin

T

IN

If the interrupt did not get cleared,

then it will activate again here

Guard2 Guard3

ACK0 ACK1

XXX

Guard1 Idle

ACK0 ACK1

XXX

P0 P1

then it will activate again here

Guard2 Guard3

ACK0 ACK1

Guard1

P0 P1

ACK0 ACK1

XXX

P0 P1

D0 D7

XXX

... ...

A0 A4

D0 D7

... ...

A0 A4 Guar d0

RW0 RW1 RW2

Start

Post-

Start

Pre-

start

g-start

Pendin

T

IN

Idle

D0 D7

XXX

... ...

...

A0 A4

IO/INT timing scenarios

... ...

A0 A4 Guard0

A0 A4

RW0 RW1 RW2

Start

Post-

Start

Pre-

start

Idle

XXX

...

A0 A4

XXX

... ...

A0 A4

Post-

Pre-

Pendin

IN

... ...

A0 A4 Guard0

RW0 RW1 RW2

Start

start

g-start

T

Idle

XXX

...

A0 A4

P0 P1

...

D0 D7

XXX

...

A0 A4

P0 P1

D0 D7

XXX

... ...

A0 A4

Post-

Pre-

P0 P1

D0 D7

... ...

A0 A4 Guard0

RW0 RW1 RW2

Start

start

Idle

uBuddyIOOut

1. INT disabled, uP initiates write access. Active high interrupt.

SH3000UM version 0.95 2002-08

uPIOOut

State

CombinedIO

2. INT active (high), uP initiates write access

3. INT active (low), uP initiates write access

uBuddyIOOut

uPIOOut

CombinedIO

uBuddyIOOut

uPIOOut

State

CombinedIO

State

4. INT disabled, uP initiates read access

uBuddyIOOut

uPIOOut

CombinedIO

State

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7.2 Interrupt Interface

The serial communications line to the SH3000 (Pin 14, IO/INT) also serves as the interrupt to the host microcontroller. The polarity of the interrupt is software programmable using the interrupt polarity bit (bit

6) of the IPol_RCtune register (R0x11). This pin is asserted for four cycles of CLK

OUT, and then returns

to the inactive state.

The interrupt line is used by the Periodic Interrupt/Wake-up Timer to interrupt the host when it reaches its end of count. See the Periodic Interrupt/Wake-up Timer chapter in this manual.

7.3 Serial Communication/Interrupt Registers

ADDRESS

0x0E

ADDRESS

0x11

NAME

Config

NAME

PAGE

0 IPol_RCtune

RESET EVENT

RESET VALUE

DESCRIPTION

PowerOn

WDog

BrownOut

HEX

BINARY

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B PW B

PW B PW B PW B

PW B

INIT

EVENT

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

0x88

1b3CLK 0 b2 W dogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

INIT

VALUE

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

WRITE

PROTECT

OUT

, 0 = 32 kHz.

DESCRIPTION

Value

BO

PowerOn

WDog

BrownOut

P W B P W B

P W B P W B P W B P W B P W B

0x??

HEX

BINARY

IDCode

Calibration

-0-

A

?

C

?

C

?

C

?

C

?

C

?

C

?

Application

Xtal REWRITE-once

V

b7 Reserved, not used

b6 Interrupt Polarity, 1 = High, 0 = Low. b5

b4

32 kHz RC Oscillator Adjustment,

b3

nominal ~330 Hz per step.

b2 b1 b0

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ADDRESS

0x1A

Status

NAME

RESET EVENT

PowerOn

WDog

BrownOut

P W B

P W B P W B P W B P W B P W B

RESET VALUE

DESCRIPTION

HEX

BINARY

0 b7 Xtal oscillator is stable

-0-

b6

-0-

0x00

Reserved, not used

b5

Auto CLK shut-down mode (transitions on CLKIN detected).

0b4 0 b3 Backup battery low. 0 b2 Serial I/O parity error. 0 b1 Interrupt status (1 = pending, 0 = idle). 0 b0 FLL locked (1 = locked, 0 = unlocked).

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8. Auxiliary Functions

8.1 Scratchpad RAM and ID number

Four bytes of general-purpose RAM reside at addresses R0x00, R0x12, R0x14, and R0x16 on page 1 in the SH3000 register space. Immediately after reset, these four bytes are loaded with the factoryprogrammed values in the OTP memory. For a standard device, these values are all zeroes. Unique serial numbers or other information could be stored here. Since the RAM/ID registers reside on page 1, a 1 must be written to the page bit (bit 6) of the Config register (R0x0E) in order to access the RAM/ID registers.

ADDRESS

0x0E

ADDRESS

0x10

0x12

0x14

0x16

RESET EVENT

RESET VALUE

NAME

PowerOn

WDog

BrownOut

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B

Config

NAME

PAGE

1 ID_RAM_MSB P W B

1 ID_RAM_2 P W B

1 ID_RAM_1 P W B

1 ID_RAM_LSB P W B

PW B PW B

PW B

INIT

EVENT

PowerOn

WDog

0x88

BrownOut

DESCRIPTION

HEX

BINARY

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

1b3CLK 0 b2 WdogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

INIT

VALUE

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

WRITE

PROTECT

OUT

, 0 = 32 kHz.

DESCRIPTION

Value

BO

HEX

0x??

BINARY

IDCode

I

Calibration

Application

Xtal REWRITE-once

V

General-purpose RAM, bits 24:31, bits 24:31 of ID code are loaded on initialization.

General-purpose RAM, bits 16:23, bits 16:23 of ID code are loaded on initialization.

General-purpose RAM, bits 8:15, bits 08:15 of ID code are loaded on initialization.

General-purpose RAM, bits 0:7, bits 00:07 of ID code are loaded on initialization.

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8.2 Write Protect Logic

The SH3000 MicroBuddy™ provides a comprehensive set of write-protect flags to safeguard groups of related bits from inadvertent corruption. Register WP_PostScale (R0x17) contains four write-protect flags, each acting on one group of bits.

The individual protected groups are:

1. V

BO value (controlled by R0x17 bit 4)

2. Application group (controlled by R0x17 bit 5)

3. Calibration group (controlled by R0x17 bit 6)

4. IDCode value (controlled by R0x17 bit 7)

The influence of the individual write-protect bits is shown in the register table on the next page.

If any of these four bits is factory-programmed to “one” in OTP non-volatile memory, then the access to the corresponding group of bits is totally inhibited.

If the write-protect bit is programmed to “zero,” then the access is permitted. The host micro can change the values of any bits within the protected group. When the user desires to enable write-protection, the corresponding write-protect flag should be set. Once any of the write-protect bits is set, it cannot be reset, and write operations on the related group of bits is inhibited.

If the write-protect bit is programmed to “zero,” then the Power-on reset condition or any Watchdog reset condition resets the write-protect flag, and write access is again permitted. The Brownout condition neither resets the write-protect flags nor re-enables the write accesses.

Note: The write-once protection mechanism for the programmable load capacitance of the LF crystal oscillator is independent of these write-protect flags in R0x17. To reprogram the load capacitance, clear the XTALtune Rewrite-Once Enable bit (bit 7) of the Config register (R0x0E) and then immediately write bits 4:7 of the register Xtune_R cleared just before each and every write access to bits 4:7 of the register Xtune_R the LF Oscillator chapter of this manual for the available values.

REFAdj (R0x12) with the desired value; the write-once enable bit must be

REFAdj (R0x12). See

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Write Protect Logic Registers

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ADDRESS

0x0E

ADDRESS

0x15

0x16

0x17

RESET EVENT

RESET VALUE

NAME

PowerOn

WDog

BrownOut

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B

Config

NAME

PAGE

0 SS_FreqSet

0 FreqSetLSB P W B

0 WP_PostScale

PW B PW B

PW B

INIT

EVENT

PowerOn

WDog

P W B P W B P W B

P W B P W B P W B P W B P W B

P W P W P W P W

P W B P W B

0x88

DESCRIPTION

HEX

BINARY

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

1b3CLK 0 b2 WdogClkSelect. 1 = CLK

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

OUT

, 0 = 32 kHz.

0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0. 0 b0 Interrupt Enable. 1 = enable, 0 = disable.

INIT

VALUE

WRITE

PROTECT

DESCRIPTION

Value

BO

BrownOut

HEX

0x??

BINARY

IDCode

Calibration

Application

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

? b7 ? ? ?

? A b3 CLK32 enable, 1 = enable, 0 = disable. ? A b2

? A b1 ? A b0

Xtal REWRITE-once

V

b7

Amount of HFCLK Spectrum Spreading, 4 (four) settings.

b6 b5 EnableSS, enable spectrum spreading.

b4 b3

Frequency Set Value for FLL, most-

b2

significant bits 8:12

b1 b0

Frequency Set Value for FLL, bits 0:7.

IDCode Write Protect, 1 = no writes. Calibration Write Protect, 1 = no writes.

b6

pplication Write Protect, 1 = no writes.

b5

BO Value Write Protect, 1 = no writes.

V

b4

DCO Post-Scaler, 8 (eight) setting:

/1, 2, 4, 8, 16, 32, 64, 128.

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8.3 Voltage Regulator

The VREG pin can be used as a nominal 2.20 V reference voltage or a supply source for small loads (< 5 mA). A bypass capacitor may be necessary between this pin and V transients or a low ripple reference is required.

SS if the load generates large current

Using V

REG to drive external loads may degrade the performance of the SH3000.

8.4 Backup Power

The VBAK pin can be connected to a backup power supply for the real-time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical). This voltage can be higher or lower than V capacitor (with external recharge circuit).

DD. Connect a backup battery or backup

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9. Registers

SH3000 User Manual

Preliminar

Table 7: SH3000 MicroBuddy™ Registers 0x00 to 0x0F

Timer, RTC, Configuration, and Control Registers

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

RESET EVENT

RESET VALUE

NAME

PowerOn

WDog

BrownOut

HEX

BINARY

PeriodMSB W B

Period2 W B

Period1 W B

PeriodLSB W B

TimerMSB W B

Timer2 W B

Timer1 W B

TimerLSB W B

RTCdaysMSB P W

RTCdaysLSB P W

RTChours W

RTCminutes P W

RTCseconds P W

RTCsubseconds P W

Config

FLLcontrol

P

P XTALtune Rewrite-Once Enable (see notes for use) PW B PW B PW B

PW B PW B PW B

PW B

PW B PW B PW B

0x00

0x00 BCD value, 0 to 23.

0x00 BCD value, 0 to 59.

0x00 8-bit binary value, 0 to 0xFF (0 to 255)

0x88

0x00

or

0x01

Periodic Interrupt / Wake-up Timer setting. With 32.768 kHz clock the period = (32-bit value)/32768. When the value = 0, the Timer is disabled. The whole 32-bit value is loaded into timer logic when PeriodLSB is written.

Free-running counter. This counter is reset when the PeriodLSB is written (Timer started) or the value of the counter is equal to 32bit Period value (Interrupt / Wake-up generated). The whole 32-bit Timer value is loaded into Timer registers when TimerLSB is read.

16-bit binary value, 0x0000 to 0xFFFF (0 to 65535, ~ 179.5 years).

1 b7

0 b6 Register Page for R0x10 through R0x17. 0 =Page0, 1 =Page1. 0 b5 ForceDCOon. Forces HF Oscillator to run under all conditions. 0b4CLK

1b3CLK 0 b2 W dogClkSelect. 1 = CLK 0 b1 Interrupt Flag Clear. 1 = clear, 0 = no effect, always reads 0.

0 b0 Interrupt Enable. 1 = enable, 0 = disable.

-0-

b7 Reserved, not used

-0-

b6 Reserved, not used

-0-

b5 Reserved, not used

-0-

b4 Reserved, not used

-0-

b3 Reserved, not used

0 b2 Start FLL fine frequency lock (~5 ms to achieve lock). 0 b1 Start FLL coarse frequency lock (~25 ms to achieve lock).

0/1 b0 Enable FLL. 1 = enabled, 0 = disabled. On Reset =pin CLK

DESCRIPTION

OUT

source. 1 = 32 kHz, 0 = HFCLK.

OUT

Enable. 1 = enable, 0 = disable.

OUT

, 0 = 32 kHz.

When RTCsubseconds is read, all RTC registers are updated. When RTCsubseconds is

t

written, counter chain is loaded.

he whole RTC

SEL

.

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Table 8: SH3000 MicroBuddy™ Registers 0x10 to 0x17

Control, Setting, and Calibration Registers Initialized from OTP Memory

ADDRESS

0x10

0x11

0x12

0x13

0x14

INIT

EVENT

NAME

PAGE

PowerOn

WDog

BrownOut

0 VBOValue

P W P W P W P W P W P W

? ? ? ? ?

P W B P W B

0 IPol_RCtune

P W B P W B P W B P W B P W B

P P P

0 Xtune_R

REF

Adj

P P W B

P W B P W B P W B

P

W

P

W

P

W

P

0 V

REF

_DCOcode

W

P W B

P W B P W B P W B

0 DCOcode1 P W B

INIT

VALUE

HEX

0x??

WRITE

PROTECT

BINARY

IDCode

Calibration

-0-

V V V V V V

?

-0-

A

?

C

?

C

?

C

?

C

?

C

?

C

?

R

?

R

?

R

?

R

?

C

?

C

?

C

?

C

?

C

?

C

?

C

?

C

?

A

?

A

?

A

?

A

?

A

Application

DESCRIPTION

Value

BO

Xtal REWRITE-once

V

b7 Reserved, not used b6 Reserved, not used

b5 b4

V

BO

b3 b2 b1 b0

b7 Reserved, not used

b6 Interrupt Polarity, 1 = High, 0 = Low. b5

b4 b3 b2 b1 b0

b7 b6 b5 b4

b3 b2 b1 b0

b7 b6 b5 b4

b3

b2 b1 b0

Threshold Value, 2.3 V to 4.4 V in

~33.33 mV steps.

32 kHz RC Oscillator Adjustment, nominal ~330 Hz per step.

32.768 kHz Xtal Oscillator fine tune (see notes for use)

Internal R

REF

Adjustment,

nominal ~330 Hz per step.

Adjustment for internal temperaturecompensated Voltage Reference, Factory-Only temperature drift trim.

Disconnect Internal R 0=connected, 1 = disconnected.

DCO setting, most-significant bits 15:17.

Bits 7:14 of DCO setting

REF

,

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Control, Setting, and Calibration Registers Initialized from OTP Memory (continued)

ADDRESS

0x15

0x16

0x17

INIT

EVENT

NAME

PAGE

P W B P W B P W B

0 SS_FreqSet

0 FreqSetLSB P W B

0 WP_PostScale

P W B P W B P W B P W B P W B

P W P W P W P W

P W B P W B

PowerOn

WDog

INIT

VALUE

BrownOut

HEX

0x??

WRITE

PROTECT

DESCRIPTION

Value

BO

BINARY

IDCode

Calibration

Application

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

?

A

? b7 ? ? ?

? A b3 CLK32 enable, 1 = enable, 0 = disable. ? A b2

? A b1 ? A b0

Xtal REWRITE-once

V

b7

Amount of HFCLK Spectrum Spreading, 4 (four) settings.

b6 b5 EnableSS, enable spectrum spreading.

b4 b3

Frequency Set Value for FLL, most-

b2

significant bits 8:12

b1 b0

Frequency Set Value for FLL, bits 0:7.

IDCode Write Protect, 1 = no writes. Calibration Write Protect, 1 = no writes.

b6

pplication Write Protect, 1 = no writes.

b5

BO

Value Write Protect, 1 = no writes.

V

b4

DCO Post-Scaler, 8 (eight) setting:

/1, 2, 4, 8, 16, 32, 64, 128.

0x10

0x11 1

0x12

0x13 1

0x14

0x15 1

0x16

0x17 1

1 ID_RAM_MSB P W B

Reserved

1 ID_RAM_2 P W B

Reserved

1 ID_RAM_1 P W B

Reserved

1 ID_RAM_LSB P W B

Reserved

General-purpose RAM, bits 24:31,

0x??

Reserved, not used.

0x??

Reserved, not used.

0x??

Reserved, not used.

0x??

Reserved, not used.

I

bits 24:31 of ID code are loaded on initialization.

General-purpose RAM, bits 16:23, bits 16:23 of ID code are loaded on initialization.

General-purpose RAM, bits 8:15, bits 08:15 of ID code are loaded on initialization.

General-purpose RAM, bits 0:7, bits 00:07 of ID code are loaded on initialization.

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Table 9: SH3000 MicroBuddy™ Registers 0x18 to 0x1F

Control and Status Registers

NAME

ADDRESS

0x18

0x1A

0x1B

0x1C

0x1D

DCOcodeLSB

0x19 Reserved

Status

ResetEvent

WDogCode P W B

WDogPeriod

0x1E Reserved

0x1F Factory Test

RESET EVENT

PowerOn

P W B P W B P W B P W B P W B P W B P W B

WDog

RESET VALUE

BrownOut

HEX

0x40

BINARY

-0-

b7 Reserved, not used

1b6 0b5 0b4

DCO setting,

0b3

least-significant bits 0:6

0b2 0b1 0b0

Reserved, not used

P W B

P W B P W B P W B P W B P W B

P B

W W

P

0 b7 Xtal oscillator is stable

-0-

b6

-0-

0x00

Reserved, not used

b5

Auto CLK shut-down mode (transitions on CLKIN detected).

0b4 0 b3 Backup battery low. 0 b2 Serial I/O parity error. 0 b1 Interrupt status (1 = pending, 0 = idle). 0 b0 FLL locked (1 = locked, 0 = unlocked).

-0-

b7

-0-

b6

0x02

-0-

0x04

-0-

0x08

0/1 b3 V

or

0/1 b2 Watchdog code violation caused the reset.

0x09

Reserved, not used

b5 b4

DD

dropped below VBO threshold (brown-out).

0/1 b1 Watchdog timeout caused the reset. 0/1 b0 Power-on caused the reset.

Alternate writes of code-Bytes 0x5A and 0xC3 are required to prevent timeout. Watchdog is reloaded after every write

0x00

(only one code has to be written to reload the watchdog, but the value of the code-Byte has to alternate between 0x5A and 0xC3).

0x00

-0-

b7 Reserved, not used

0b6

Watchdog timeout value. Depending on WdogClkSelect bit

0b5

in the Config register (R0x0E, b2), the watchdog will be decremented by either a 32 kHz clock or the signal on the

0b4

CLK

OUT

0b3

when the HFCLK stops). The Watchdog is disabled after the

0b2

reset and started by writing to WDogPeriod. Once started,

0b1

the clock selection or timeout value cannot be changed.

0b0

pin (in which case the watchdog will be suspended

P W B P W B P W B P W B P W B P W B P W B

Reserved, not used

Reserved, do not write to this register.

DESCRIPTION

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38

SEMTECH SH3000 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual