Datasheet SC486 Datasheet (SEMTECH)

1 www.semtech.com

SC486

Complete DDR1/2/3

Memory Power Supply

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Revision: September 13, 2006

The SC486 is a combination switching regulator and linear
source/sink regulator intended for DDR1/2/3 memory
systems. The switching regulator is used to generate the
supply voltage, VDDQ, for the memory system. It is a
pseudo-fixed frequency constant on-time controller
designed for high efficiency, superior DC accuracy, and
fast transient response. The linear source/sink regulator
is used to generate the memory termination voltage, VTT,
with the ability to source and sink a 3A peak current.
For the VDDQ regulator, the switching frequency is
constant until a step in load or line voltage occurs at
which time the pulse density, i.e. frequency, will increase
or decrease to counter the transient change in output or
input voltage. After the transient, the frequency will return
to steady-state operation. At lighter loads, the selectable
Power-Save Mode enables the PWM converter to reduce
its switching frequency and improve efficiency. The
integrated gate drivers feature adaptive shoot-through
protection and soft-switching.
For the VTT regulator, the output voltage tracks VREF,
which is ½ VDDQ to provide an accurate termination
voltage. The VTT output is generated from a 1.2V to VDDQ
input by a linear source/sink regulator which is designed
for high DC accuracy, fast transient response, and low
external component count. Additional features include
cycle-by-cycle current limiting, digital soft-start, power
good (all VDDQ only) and over-voltage and under-voltage
protection (VDDQ and VTT). All 3 outputs (VDDQ, VTT and
REF) are actively discharged when VDDQ is disabled,
reducing external component count and cost. The SC486
is available in a 24 pin MLPQ 4mmx4mm Lead-free
package.

Notebook computers
CPU I/O supplies
Handheld terminals and PDAs
LCD monitors
Network power supplies

DDR1, DDR2 and DDR3 compatible
Constant on-time controller for fast dynamic

response on VDDQ

Programmable VDDQ range - 1.5V to 3V
1% Internal Reference (2% System Accuracy)
Resistor programmable on time for VDDQ
VCCA/VDDP range = 4.5V to 5.5V
VBAT range = 2.5V to 25V
VDDQ DC current sense using low-side R

DS(ON)

sensing or external R

SENSE

in series with low-side

FET

Cycle-by-cycle current limit for VDDQ
Digital soft-start for VDDQ
Combined EN and PSAVE pin for VDDQ
Over-voltage/under-voltage fault protection for

both outputs and PGD output (VDDQ only)

Separate VCCA and VDDP supplies
VTT/REF range = 0.75V – 1.5V
VTT source/sink 3A peak
Internal resistor divider for VTT/REF
VTT is high impedance in S3
VDDQ, VTT and REF are actively discharged in

S4/S5

24-pin MLPQ (4 x 4mm) Lead-free package, fully

WEEE and RoHS compliant

+

C10

VDDQ

C12

1uF

C11

20uF

VTT

C9

1uF

R2

10R

5VRUN5VSUS

C3

no-pop

R7 10R

REF

R6

10R

C6

1uF

R4 10R

C2

1uF

R5

R9

VDDQ

PGOOD

VBAT

C8

1nF

C1

no-pop

C7

no-pop

R8 0R

VDDQ

4

1

2

3

5 6

78

Q1

R10

C13

1uF

C4

0.1uF

D1

R3 470k

5VSUS

C5

10uF

R1

VBAT

L1

PGND1

18

REF

8

EN/PSV

1

TON

2

VDDQS

3

VCCA

5

FB

6

PGD

7

VSSA

4

PGND2

17

DL

19

VDDP

20

ILIM

21

LX

22

DH

23

BST

24

VTTEN

11

VTT

15

PGND2

16

VTTIN

12

VTTIN

13

VTT

14

VTTS

10

COMP

9

PAD

U1 SC486

Description Features

Applications

Typical Application Circuit

SC486

retemaraP lobmyS mumixaM stinU

ASSVotNOT 0.52+ot3.0- V

1DNGPotTSB,HD 0.03+ot3.0- V

1DNGPotXL 0.52+ot0.2- V

1DNGPotPDDV,MILI,LD 0.6+ot3.0- V

LDotPDDV 0.6+ot3.0- V

2DNGPotTTV,NITTV 0.6+ot3.0- V

TTVotNITTV 0.6+ot3.0- V

,NETTV,SQDDV,ACCV,FER,DGP,BF,VSP/NE,PMOC

ASSVOTSTTV

0.6+ot3.0- V

,NETTV,TTV,SQDDV,FER,BF,VSP/NE,PMOCotACCV

STTV,NITTV

0.6+ot3.0- V

ASSVot1DNGP,2DNGPot1DNGP 3.0+ot3.0- V

XLotHD,TSB 0.6+ot3.0- V

tneibmAotnoitcnuJecnatsiseRlamrehT

θ

AJ

92 W/C°

egnaRerutarepmeTnoitcnuJgnitarepO T

J

051+ot04- C°

egnaRerutarepmeTegarotS T

GTS

051+ot56- C°

s04-s01,erutarepmeTwolfeRRIkaeP T

GKP

062 C°

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.

Electrical Characteristics

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Absolute Maximum Ratings

(10)

Test Conditions: V

= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

BAT

retemaraP snoitidnoC C°52 C°521otC°04- stinU

seilppuStupnI

tnerruCgnitarepOACCV I,tniopnoitaluger>BF

3S,tnerruCgnitarepOACCV I,tniopnoitaluger>BF

= 1MΩ

TON

niM pyT xaM niM xaM

A0= 0051 0052 Aµ

QDDV

,A0=

QDDV

0001 Aµ

V0=NETTV

tnerruCgnitarepOPDDV I,tniopnoitaluger>BF

A0= 07 051 Aµ

QDDV

tnerruCgnitarepONOT M1=NOTR Ω 51 Aµ

tnerruCgnitarepONITTV I

NOT+PDDV+ACCV

A0= 1 5 Aµ

TTV

V0=NETTV=VSP/NE 5 11 Aµ

tnerruCnwodtuhS

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Test Conditions: V

BAT

= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

TON

= 1MΩ

Electrical Characteristics (Cont.)

SC486

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rellortnoCQDDV

)1(

dlohserhTrotarapmoCrorrEBF

emiT-nO R

R

NOT

R

NOT

emiT-ffOmuminiM 004 055 sn

ecnatsiseRtupnISQDDV 051 kΩ

nwodtuhSSQDDV

ecnatsiseRegrahcsiD

tnerruCegakaeLBF 0.1- 0.1 Aµ

rellortnoCTTV

tnerruCegakaeLPMOC 0.1- 0.1 Aµ

tnerruCecruoSFER 01 Am

ycaruccAtuptuOFER I

nwodtuhSFER

ecnatsiseRegrahcsiD

niM pyT xaM niM xaM

V5.5otV5.4=ACCV 005.1 584.1 515.1 V

M1= Ω 064 093 035

NOT

k005= Ω C°01-, ≤ TA≤ C°521 562 522 503

k005= Ω C°04-, ≤ TA≤ C°521 522 023

DNG=VSP/NE 22

FER

Am01ot0= 009 288 819 Vm

DNG=VSP/NE 22

sn

Ω

Ω

ycaruccAtuptuOTTV I<A2-

nwodtuhSTTV

A2< FER 02- 02+ Vm

TTV

DNG=VSP/NE 22

ecnatsiseRegrahcsiD

tnerruCegakaeLSTTV 0.1- 0.1 Aµ

gnisneStnerruC

tnerruCMILI 01 9 11 Aµ

tesffOrotarapmoCtnerruC MILI-1DNGP 01- 01 Vm

dlohserhTgnissorC-oreZ V5=VSP/NE,XL-1DNGP 5 Vm

noitcetorPtluaFQDDV

)2(

)evitisoP(timiLtnerruC

R,XL-1DNGP

R,XL-1DNGP

R,XL-1DNGP

k5= Ω 05 53 56 Vm

MILI

k01= Ω 001 08 021

MILI

k02= Ω 002 071 032

MILI

)evitageN(timiLtnerruC XL-1DNGP 521- 061- 09- Vm

tluaFegatloVrednUtuptuO ecnereferlanretniottcepserhtiW 03- 53- 52- %

yaleDtluaFegatloVrednU htVVUwolebdecrofBF 8 sklc

3 2006 Semtech Corp. www.semtech.com

Ω

)3(

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Test Conditions: V

BAT

= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

TON

= 1MΩ

Electrical Characteristics (Cont.)

SC486

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).tnoC(noitcetorPtluaFQDDV

emiTknalBegatloVrednU hgihNEmorF 044 sklc

tluaFegatloVrevOtuptuO ecnereferlanretniottcepserhtiW 61+ 21+ 02+ %

yaleDtluaFegatloVrevO htVVOevobadecrofBF 5 sµ

egatloVtuptuOwoLDGP Am1kniS 4.0 V

tnerruCegakaeLDGP V5=DGP,noitalugerniBF 1 Aµ

dlohserhTVUDGP ecnereferlanretniottcepserhtiW 01- 21- 8- %

yaleDtluaFDGP wodniwDGPedistuodecrofBF 5 sµ

egatloVrednUACCV Vm001siseretsyh,egdegnillaF 0.4 7.3 3.4 V

noitcetorPtluaFTTV

tluaFegatloVrednUtuptuO FERtr/wTTV 21- 61- 8- %

tluaFegatloVrevOtuptuO FERtr/wTTV 21+ 8+ 61+ %

yaleDnwodtuhStluaF wodniwVO/VUedistuoTTV 05 sµ

niM pyT xaM niM xaM

)3(

)5()4(

nwodtuhSlamrehT

061 051 071 C°

stuptuO/stupnI

egatloVwoLtupnIcigoL wolVSP&NE 2.1 V

wolNETTV 6.0

egatloVhgiHtupnIcigoL wolVSP,hgihNE 0.2 V

hgihNETTV 4.2

egatloVhgiHtupnIcigoL hgihVSP,hgihNE 1.3 V

ecnatsiseRtupnIVSP/NE gnicruoS 5.1 MΩ

gnikniS 0.1

tratStfoS

emiTpmaRtratStfoSQDDV hgihDGPothgihVSP/NE 044 sklc

)6(

etaRpmaRtratStfoSTTV

6 sµ/Vm

)3(

sevirDetaG

)7()4(

yaleDnoitcetorPurht-toohS

ecnatsiseRnwoD-lluPLD wolLD 8.0 6.1

gnisirLDroHD 03 sn

Ω

tnerruCkniSLD V

V5.2= 1.3 A

LD

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Test Conditions: V

BAT

= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

TON

= 1MΩ

Electrical Characteristics (Cont.)

Shoot-Through Delay Timing Diagram

SC486

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niM pyT xaM niM xaM

).tnoC(sevirDetaG

ecnatsiseRpU-lluPLD hgihLD 2 4

tnerruCecruoSLD V

V5.2= 3.1 A

LD

ecnatsiseRnwoD-lluPHD V5=XL-TSB,wolHD 2 4

)8(

ecnatsiseRpU-lluPHD

tnerruCecruoS/kniSHD V

HD

V5=XL-TSB,hgihHD 2 4

V5.2= 3.1 A

ecnatsiseRpU-lluPTTV FER<STTV 52.0 54.0

ecnatsiseRnwoD-lluPTTV FER>STTV 52.0 54.0

)9(

tnerruCecruoS/kniSkaePTTV

6.3 0.2 A

Ω

Ω

Ω

Ω

Ω

Notes:

(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the
ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND1 minus the voltage of the source on the
low-side MOSFET.
(3) clks = switching cycles, consisting of one high side and one low side gate pulse.
(4) Guaranteed by design.
(5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.
(6) VTT soft start ramp rate is 6mV/µs typical unless VDDQ/2 ramp rate is slower. If this is true, VTT soft start
ramps at 6mV/µs (typ.) until it reaches VDDQ/2, and then tracks it.
(7) See Shoot-Through Delay Timing Diagram below.
(8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V
(typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2Ω (typ.). This negates the
need for an external gate or boost resistor.
(9) Provided operation below T

is maintained.

J(MAX)

(10) This device is ESD sensitive. Use of standard ESD handling precautions is required.

LX

DL

tplhDL tplhDH

DH

DL

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Top View

#niP emaNniP noitcnuFniP

1 VSP/NE dnaQDDVelbaneotV5+oteiT.QDDVelbasidotdnuorgoteiT.niptupnievaSrewoP/elbanE

,detaolffI.edomnoitcudnocsuonitnocetavitcadnaQDDVelbaneottaolF.edomEVASPetavitca

.roticapacFn01ahtiwASSVotssapyb

2 NOT -noTEFSOMpotehttesdna,NOTR,rotsiserpullupahguorhtTABVesnesotdesusinipsihT

.ASSVotroticapacFn1ahtiwnipsihtssapyB.emit

3 SQDDV esU.TTV/FERVtesotosladnaTEFSOMpotehtrofemit-noehttesotdesU.QDDVrofnipesneS

01a Ω .ASSVotQDDVmorfretlifCRFµ1/

4 ASSV no)1egaPees(9Cdna,8C,7C,6C,9RotyltceridtcennoC.yrtiucricgolanarofecnereferdnuorG

.daplamrehtottcennoC.C.IsaBCPfoedisemas

5 ACCV 01aesU.ylppusgolanaehtroftupniegatlovylppuS Ω .ASSVotSUSV5morfretlifCRFµ1/

6 BF tuptuoehttesotASSVottuptuoehtmorfredividrotsiseraottcennoC.QDDVroftupnikcabdeeF

.ACCVdnaV5.1neewtebegatlov

7 DGP nipsihT.sdlohserhtdoogrewopehtedistuosiQDDVfiwolsiDGP.QDDVroftuptuodoogrewoP

.rotsiserpu-lluplanretxenaseriuqerdnatuptuoSOMNniardneponasi

8 FER QDDV%05otegatlovsihtstesSQDDVmorfredividrotsiserlanretninA.tuptuoecnerefeR

01seiresahtiwnipsihtssapyB.)lanimon( Ω )1egaPees(6RotnoitcennocehT.ASSVotFµ1/

.8nipotesolcedamebdluohs

9 PMOC .tuptuoTTVrofnoitasnepmocreifilpmarorrE

01 STTV .daolehttaTTVottcennoC.TTVrofnipesneS

11 NETTV siQDDVsagnolsatneserpsniamerFERV(TTVelbasidotwolnipsihtlluP.TTVrofnipelbanE

.)tneserp

31,21 NITTV otroticapacFµ1ahtiwnipsihtelpuoceD.rotalugerTTVrofhctiwsedishgihehtrofylppustupnI

.2DNGP

Note:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead-free product. This product is fully WEEE and
RoHS compliant.

Pin Configuration Ordering Information

Pin Descriptions

SC486

ECIVED EGAKCAP

)2(

TRTLMI684CS

BVE684CS draoBnoitaulavE

(MLPQ-24)

)1(

42-QPLM

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POWER MANAGEMENT

Top View

Part Number
yyww = Date Code (Example: 0012)
xxxxx = Semtech Lot No. (Example: E9010
xxx 1-1)

Pin Descriptions (Cont)

Marking Information

51,41 TTV ,2DNGPotsroticapaccimarecFµ01)muminim(owthtiwelpuoceD.rotalugerraenilehtfotuptuO

71,61 2DNGP .enalpdnuorgdnadaplamrehtottcennoC.tuptuoTTVrofdnuorgrewoP

81 1DNGP .enalpdnuorgdnadaplamrehtottcennoC.tuptuoQDDVrofdnuorgrewoP

91 LD .hctiwsTEFSOMediswolehtroftuptuoevirdetaG

02 PDDV .srevirdetagQDDVehtroftupniegatlovylppusV5+

12 MILI ecruosehtrognisnes)no(SDRrofTEFSOMedis-wolfoniardottcennoC.niptupnitimiltnerruC

22 XL .rotcudnituptuoehtdnasTEFmottobdnapotehtneewtebnoitcnujeht-edonesahP

32 HD .hctiwsTEFSOMedishgihehtroftuptuoevirdetaG

42 TSB .evirdetagedishgihehtrofnoitcennocroticapactsooB

SC486

.71dna,61,51,41snipssorcayltceridmehtgnitacol

.rotsisergnisnesdlohserhtahguorhtgnisnesrotsiserrof

- LAMREHT
DAP

detcennoctoN.saivelpitlumgnisuenalpdnuorgottcennoC.sesoprupgniknistaehrofdaP

.yllanretni

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Block Diagram

SC486

Figure 1 - SC486 Block Diagram

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Notes:

(1) EN/PSV = 1 = EN/PSV high or floating.
(2) Discharge resistance = 22Ω typ.
(3) VDDQ is discharged via R4 (see Page 1) so this resistance must be added when calculating discharge times.

Enable Control Logic

sutatSniPelbanE sutatStuptuO

)1(

VSP/NE

NETTV QDDV TTV FER

SC486

0 0 degrahcsiD,FFO

0 1 degrahcsiD,FFO

)3()2(

)3()2(

)2(

degrahcsiD,FFO

)2(

degrahcsiD,FFO

)2(

degrahcsiD,FFO

)2(

degrahcsiD,FFO

1 0 NO ecnadepmIhgiH,FFO NO

1 1 NO NO NO

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Application Information

SC486

+5V Bias Supply

The SC486 requires an external +5V bias supply in
addition to the battery. This is connected to VDDP for
the VDDQ switching drive power and via an RC filter to
VCCA for the chip supply. If stand-alone capability is
required, the +5V supply can be generated with an
external linear regulator.

VTTIN Supply

The VTTIN pins provide the input power for the high side
(sourcing) section of the VTT LDO. These pins should be
decoupled to PGND2. If the output capacitors for the
input supply for VTTIN (whether it is VDDQ or a different
supply) are not close to the chip, additional local bulk
capacitance may be required.

Grounding

The SC486 has three ground connections, VSSA, PGND1
and PGND2 (2 pins). These should all be starred together
at the thermal pad under the device, which in turn will be
connected to the ground plane using multiple vias. VSSA
is the controller ground reference, to avoid interference
between the power and reference sections. PGND1 is
the p ower ground connect ion for the switching
controlle r for VDDQ. PGND2 is the powe r ground
connection for the sink-source LDO for VTT. All external
components referenced to VSSA in the schematic should
be connected directly to the VSSA trace. The supply
decoupling capacitor should be tied between VCCA and
VSSA. A 10Ω resistor should be used to decouple the
VCCA supply from the main VDDP supply. The VDDP
input provides power to the upper and lower gate
drivers of the switching supply. A decoupling capacitor
with no series resistor between VDDP and 5V is required.
See layout guidelines for more details.

Ps eudo-fixe d Freq uency Constant On-Tim e PWM
Controller (VDDQ)

The PWM control architecture consists of a constant on­time, pseudo fixed frequency PWM controller (see Figure
1, SC486 Block Diagram). The output ripple voltage
developed across the output filter capacitor’s ESR
provides the PWM ramp signal eliminating the need for a
current sense resistor. The high-side switch on-time is
determined by a one-shot whose period is directly
proportional to output voltage and inversely proportional
to input voltage. A second one-shot sets the minimum
off-time which is typically 400ns.

On-Time One-Shot (tON)

The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high-side switch directly proportional to output voltage
and inver sely proporti onal to input voltage. Thi s
implementation results in a nearly constant switching
frequency without the need for a clock generator.

12

ON

R

is a resistor connected from the input supply to the

TON

−

TON

3

OUT





)10x37R(10x3.3t

•+•=



V

IN



ns50

+








V

TON pin. Due to the high impedance of this resistor, the
TON pin should always be bypassed to VSSA using a 1nF
ceramic capacitor.

EN/PSV: Enable, PSAVE and Soft Discharge

The EN/PSV pin enables the VDDQ (2.5V or 1.8V) output
and the REF output. VTTEN enables the VTT (1.25V or

0.9V) output provided that VDDQ is present. See Enable
Control Logic on Page 9.
When EN/PSV is pulled high the VDDQ controller is
enabled and power save will also be enabled. When the
EN/PSV pin is tri-stated (allowed to float, a 10nF
capacitor is required in this instance), an internal pull-up
will activate the VDDQ controller and power save will be
di sabled. If PSAVE is enabled, the SC48 6 PSAV E
comparator will look for the inductor current to cross
zero on eight consecutive switching cycles by comparing
the phase node (LX) to PGND1. Once observed, the
controller will enter power save and turn off the low side
MOSFET when the current crosses zero. To improve light­load efficiency and add hysteresis, the on-time is
increased by 50% in power sav e. The eff icienc y
improvement at light-loads more than offsets the
disadvantage of slightly higher output ripple. If the
inductor current does not cross zero on any switching
cycle, the controller will immediately exit power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero
on eight consecutive cycles. This allows the output
voltage to recover quickly in response to negative load
steps even when psave is enabled.

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SC486

EN/PSV: Enable, PSAVE and Soft Discharge (Cont.)

If the EN/PSV pin is pulled low, all three outputs will be
shut down and discharged using switches with a nominal
resistance of 22 Ohms, regardless of the state of the
VTTEN pin. This will ensure that the outputs will be in a
defined state next time they are enabled and also
ensure, since this is a soft discharge, that there are no
dangerous negative voltage excursions to be concerned
ab out. In order for the soft discha rge circuitry to
function correctly, the chip supply must be present.

VTTEN

The VTTEN pin is used to enable the VTT regulator only.
Pulling it high enables the regulator as long as VDDQ/
REF are present. Pulling VTTEN low while EN/PSV is
floating or high will turn off the VTT regulator and leave it
in a high-impedance state for S3 mode (VDDQ and REF
present, VTT high-Z).

VDDQ Output Voltage Selection and Output Sense

The output voltage is set by the feedback resistors R5 &
R9 of Figure 2 below. The internal reference is 1.5V, so
the voltage at the feedback pin will match the 1.5V
reference . Therefore the out put can be set to a
minimum of 1.5V. The equation for setting the output
voltage is:

5R



1 VOUT •






+=

5.1



8R



VDDQS is used to sense the output voltages for the on­time one-shot, tON, and also to generate REF, which is 1/
2 of VDDQ. An RC filter consisting of 10Ω and 1µF from
VDDQ to VSSA is required (R4 and C2 in Figure 2) to filter
switching frequency ripple.

VDDQ Current Limit Circuit

Current limiting of the SC486 can be accomplished in
two ways. The on-state resistance of the low-side
MOSFETs can be used as the current sensing element or
sense resistors in series with the low-side sources can
be used if great er a ccurac y is desired. R

DS (O N)

sensing is more efficient and less expensive. In both
cases, the R
set the over current threshold. This resistor R

resistors between the ILIM pin and LX pin

ILIM

ILI M

is
connected to a 10µA current source within the SC486
which is turned on when the low side MOSFET turns on.
When the voltage drop across the sense resistor or low
side MOSFET equals the voltage across the RILIM
resistor, positive current limit will activate. The high side
MOSFET will not be turned on until the voltage drop across
the sense element (resistor or MOSFET) falls below the
voltage across the R

resistor. In an extreme over-

ILIM

current situation, the top MOSFET will never turn back
on and eventually the part will latch off due to output
undervoltage (see Output Undervoltage Protection).

The current sensing circuit actually regulates the
inductor valley current (see Figure 3). This means that if
the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak ripple current,
and the average current through the inductor would be
10A plus 1/2 the peak-to-peak ripple current. The
equations for setting the valley current and calculating
the average current through the inductor are shown
overleaf.

VDDQ

REF

C1

no-pop

VDDQ

VTT

R5

R4 10R

R9

VBAT

C2

1uF

R7 10R

C7

no-pop

C3

no-pop

R8 0R

C11

20uF

R6

10R

C6

1uF

5VRUN5VSUS

R2

R1

C8

1nF

C12

1uF

U1 SC486

10R

11

3

2

6

8

9

10

5

C9

4

1uF

14
15

12
13

16
17

VTTEN

VDDQS

TON

FB

REF

COMP

VTTS

VCCA

VSSA

VTT
VTT

VTTIN
VTTIN

PGND2
PGND2

PGD

EN/PSV

VDDP

PGND1

BST

ILIM

5VSUS

7

1

24

23

DH

LX

DL

R10

21

22

19

20

C13

1uF

18

R3 470k

D1

C4

0.1uF

4

3

2

Q1

5 6

VBAT

PGOOD

C5

10uF

L1

78

1

VDDQ

+

C10

Figure 2

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POWER MANAGEMENT

T

TIME

Valley Current-Limit Threshold Point

Figure 3: Valley Current Limiting

The equation for the current limit threshold is as follows:

A

R

R

10eI

SENSE

ILIM

6-

LIMIT

•=

Where (referring to Figure 2) R

ILIM

is R10 and R

SENSE

is the

R

DS(ON)

of the bottom of Q1.

For resistor sensing, a sense resistor is placed between
the source of Q1 and PGND1. The current through the
source sense resistor develops a voltage that opposes
the voltage developed across R

ILIM

. When the voltage

developed across the R

SENSE

resistor reaches the voltage

drop across R

ILIM

, a positive over-current exists and the
high side MOSFET will not be allowed to turn on. When
using an external sense resistor R

SENSE

is the resistance

of the sense resistor.

The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the
load to PGND1 through the inductor and bottom MOSFET).
In this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC486 monitors the voltage at LX, and if it is greater
than a set threshold voltage of 125mV (nom.) the
bottom MOSFET is turned off. The device then waits for
approximately 2.5µs and then DL goes high for 300ns
(typ.) once more to sense the current. This repeats until
either the over-current condition goes away or the part
latches off due to output overvoltage (see Output
Overvoltage Protection).

Power Good Output

The VDDQ output has its own power good output. Power
good is an open-drain output and requires a pull-up
resistor. When VDDQ is 16% above or 10% below its set
voltage, PGD gets pulled low. It is held low until the
output voltage returns to within these thresholds. PGD
is also held low during start-up and will not be allowed to
transition high until soft start is over (440 switching
cycles) and the output reaches 90% of its set voltage.
There is a 5µs delay built into the PGD circuitry to
prevent false transitions.

Output Overvoltage Protection

VDDQ: w hen the o utput exceeds 16% o f it s set
voltage the low-side MOSFET is latched on. It stays
latched on and the controller is latched off until reset
(see below). There is a 5µs delay built into the OV
protection circuit to prevent false transitions. An OV fault
in VDDQ will cause REF and VTT to turn off (high-Z) also
when VDDQ drops below 0.5V. Note: to reset from any
fault, VCCA or EN/PSV must be toggled.

VTT: when the output exceeds 12% of its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the OV protection circuit to
prevent false transitions. An OV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.

Output Undervoltage Protection

VDDQ: when the output is 30% below its set voltage the
output is latched in a tri-stated condition. It stays latched
and the controller is latched off until reset (see below).
There is a 5µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VDDQ will cause
REF and VTT to turn off (high-Z) also when VDDQ drops
below 0.5V.

VTT: when the output is 12% below its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.

VDDQ Current Limit Circuit (Cont.)

SC486

INDUCTOR CURREN

I

PEAK

I

LOAD

I

LIMIT

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POWER MANAGEMENT

SC486

POR, UVLO and Softstart

An internal power-on reset (POR) occurs when VCCA
exceeds 3V, starting up the internal biasing. VCCA
undervoltage lockout (UVLO) circuitry inhibits the whole
controller until VCCA rises above 4.2V. At this time the
UVLO circuitry enables the REF buffer, resets the fault
latch and soft start timer, and allows switching to occur,
if enabled. Switching always starts with DL to charge up
th e BST capacito r. With the softstar t circui t
(automatically) enabled, it will progressively limit the
output current (by limiting the current out of the ILIM pin)
over a predetermined time period of 440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time
(for purposes of the on-time one-shot, there is an
internal positive offset of 120mV to VOUT during this
period to aid in startup)

2) 110 cycles at 50% ILIM with normal minimum off-time

3) 110 cycles at 75% ILIM with normal minimum off-time

4) 110 cycles at 100% ILIM with normal minimum
off-time. At this point the output undervoltage and power
good circuitry is enabled.

When VDDQ reaches 0.5V, the REF output is enabled
and rises to VDDQS/2. VTT attempts to track REF but its
own soft start circuitry will limit its rise rate to 6mV/µs. If
VDDQ is rising slow enough, VTT will rise at 6mV/µs until
it reaches VDDQ/2 and then track VDDQ.

There is 100mV of hysteresis built into the UVLO circuit
and when VCCA falls to 4.1V (nom.) the output drivers
are shut down and tri-stated.

MOSFET Gate Drivers

The DH and DL driver s are opt imized for driv ing
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (bel ow ~1V). Semt ech’s
SmartDriver™ FET drive first pulls DH high with a pull-up
resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this
point, an additional pull-up device is activated, reducing
the resistance to 2Ω (typ.). This negates the need for an
external gate or boost resistor. The adaptive dead-time
circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the low­side MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
inductance between the DH and DL outputs to the gate
of each MOSFET.

DDR Reference Buffer

The reference buffer is capable of driving 10mA and
sinking 25µA. Since the output is class A, if additional
sinking is required an external pulldown resistor can be
added. Make sure that the ground side of this pulldown
is tied to VSSA. As with most opamps, a small resistor is
required when driving a capacitive load. To ensure stability
use either a 10Ω resistor in series with a 1µF capacitor
or a 100Ω resistor in series with a 0.1µF capacitor from
REF to VSSA.

VTT Sink/Source Output

The VTT regulator is a sink/source LDO capable of
supplying peak currents up to 3.6A. It has been designed
to operate with output capacitances as low as 20µF (two
10µF 1210 ceramic capacitors). These capacitors need
to be placed directly across the VTT and PGND2 pins to
minimize parasitic resistance and inductance. Additional
ceramic capacitors may be used to improve transient
response further if desired. The VTT input requires a 1µF
ceramic capacitor for bypass purposes located right at
the pin. If the output capacitors for the power rail being
used for VTTIN are far from the part then additional bulk
capacitance of two 10µF ceramic capacitors should be
added.

COMP Pin

The VTT COMP pin is provided to permit the addition of a
zero into the VTT control loop by adding a resistor (less
than 100Ω) between COMP and REF and a capacitor
from COMP to VTTS (R7 and C3 in Figure 2). The zero
frequency should be set to approximately 10 times the
unity gain bandwidth, which is ~1MHz, therefore fZ should
be ~10MHz. fZ is given by the following equation:

=

f

Z

Typically this compensation will not be required, so C3
should be no-pop and R7 should be 0Ω or 10Ω.

VTTS Pin

The VTTS pin is used to kelvin sense the VTT output. An
RC filter (with R from VTT to VTTS less than 100Ω and C
from VTTS to VSSA, R8 and C7 in Figure 2) may be used
to compensate any zeroes created by less than optimal
ESR at the output. With the recommended output
capacitors they are not necessary so R should be 0Ω
and C should be no-pop.

13 2006 Semtech Corp. www.semtech.com

1

CR2

••π•

POWER MANAGEMENT

SC486

Dropout Performance

VDDQ: the output voltage adjust range for
continuous-conduction operation is limited by the fixed
550ns (maximum) minimum off-time one-shot. For best
dropout performance, use the slowest on-time setting
of 200kHz. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on and off times. The IC duty-factor limitation
is given by:

t

DUTY

=

t

)MIN(ON

+

t

)MIN(ON

)MAX(OFF

Be sure to include inductor resistance and MOSFET on­state voltage drops when performing worst-case dropout
duty-factor calculations.

VTT: the minimum input voltage allowed to be applied to
VTTIN (if a supply other than VDDQ is being used) should
be determined using the required maximum output
current and the maximum VTT pull-up resistance, 0.45Ω.
The minimum VTTIN for a given VTT and ITT can be
calculated as follows:

RITTVTT)MIN(VTTIN •+=

)MAX(PULLUP

For example: for VTT = 0.9V out and ITT = 1.25A, VTTIN
can go as low as 1.463V.

VBAT = 6V, then the measured DC output will be 2.525V.
If the ripple increases to 80mV with VBAT = 25V, then
the measured DC output will be 2.540V.

The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. It will not change the frequency. Switching
frequency variation with load can be minimized by
choosing MOSFETs with lower R

DS(ON)

. High R

DS(ON)

MOSFETs
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage.

SC486 System DC Accuracy (VTT Sink/Source LDO)

The VTT LDO is designed to track the voltage at REF, with
a guaranteed DC accuracy of REF +/-20mV for -2A to
+2A. Thus the DDR/DDR2 absolute requirement of
+/-40mV including transients is an easy goal to achieve
provided that careful attention is paid during board layout
to reduce parasitic ESR/ESL.

DDR Supply Selection

The SC486 can be configured so that the VTT supply can
be generated from the VDDQ supply, or from an alternate
supply (usually lower to minimize power dissipation). If
the VTT LDO is going to be powered from the VDDQ output,
the electrical design of the VDDQ output needs to be for
IDDQ(MAX) + ITT(MAX).

SC486 System DC Accuracy (VDDQ Controller)

Two IC parameters affect system DC accuracy, the error
comparator threshold voltage variation and the switching
frequency variation with line and load.

The error comparator threshold does not drift significantly
with supply and temperature. Thus, the error comparator
contributes 1% or less to DC system inaccuracy. Board
components and layout also influence DC accuracy. The
use of 1% feedback resistors contribute 1%. If tighter
DC accuracy is required use 0.1% feedback resistors.

The on-pulse in the SC486 is calculated to give a pseudo
fixed frequency. Nevertheless, some frequency variation
with line and load can be expected. This variation changes
the output ripple voltage. Because constant on-time
regulators regulate to the valley of the output ripple, ½
of the output ripple appears as a DC regulation error.
For example, if the feedback resistors are chosen to
divide down the output by a factor of five, the valley of
the output ripple will be 2.5V. If the ripple is 50mV with

14 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

SC486

Design Procedure - VDDQ Controller

Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure an 8A VDDQ output
being used to power VTT at +/-2A for a total IDDQ of
10A will be designed.

The maximum input voltage (V

) is determined by

BAT(MAX)

the highest AC adaptor voltage. The minimum input
voltage (V

) is determined by the lowest battery

BAT(MIN)

voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
purposes of this design example we will use a V

range

BAT

of 9V to 19.2V.

Four parameters are needed for the output:

1) nominal output voltage, V

(for DDR2 this is 1.8V)

OUT

2) static (or DC) tolerance, TOLST (we will use +/-4% for
this design )

3) transient tolerance, TOLTR and size of transient (we will
use +/-100mV for this design).

4) maximum output current, I

(we are designing for

OUT

10A)

and

V

f

=

)MAX(VBAT_S W

( )

OUT

•

tV

Hz

)MAX(VBAT_ON)MAX(BAT

tON is generated by a one-shot comparator that samples
V

via R

BAT

used to charge an internal 3.3pF capacitor to V

, converting this to a current. This current is

tON

OUT

. The
equations above reflect this along with any internal
components or delays that influence tON. For our DDR2
VDDQ example we select R

t

ON_VBAT(MIN)

f

SW_VBAT(MIN)

= 546ns and t

= 366kHz and f

= 715kΩ:

tON

ON_VBAT(MAX)

SW_VBAT(MAX)

= 283ns

= 332kHz

Now that we know tON we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of I

which will give us a starting place.

OUT

( )

VVL

OUT)MIN(BAT)MIN(VBAT

t

•−=

( )

•

I5.0

OUT

)MIN(VBAT_ON

H

Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. The default R

value of 715kΩ is

tON

suggested as a starting point, but it is not set in stone.
The first thing to do is to calculate the on-time, tON, at
V
V

BAT(MIN)

and R

OUT

and V

tON




)MIN(VBAT_ON





, since this depends only upon V

BAT(MAX)

.

12

( )

tON

3

••+••=

1037R103.3t

V

BAT



V

OUT




)MIN(BAT



−−

9

•+

and




)MAX(VBAT_ON





12

( )

tON

3

1037R103.3t

••+••=

V



V

OUT




)MAX(BAT



−−

9

•+

From these values of tON we can calculate the nominal
switching frequency as follows:

and

( )

VVL

OUT)MAX(BAT)MAX(VBAT

t

•−=

( )

)MAX(VBAT_ON

I5.0

H

OUT

•

For our DDR2 VDDQ example:

L

= 0.8µH and L

VBAT(MIN)

VBAT(MAX)

= 1.0µH

,

We will select an inductor value of 1.5µH to reduce the
ripple current, which can be calculated as follows:

s1050

( )

VVI

t

•−=

OUT)MIN(BAT)MIN(VBAT_RIPPLE

)MIN(VBAT_ON

A

L

and

s1050

( )

VVI

t

•−=

OUT)MAX(BAT)MAX(VBAT_RIPPLE

)MAX(VBAT_ON

L

PP

−

A

PP

−

V

f

=

)MIN(VBAT_SW

( )

OUT

•

tV

Hz

)MIN(VBAT_ON)MIN(BAT

15 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

SC486

Design Procedure (Cont.)

For our DDR2 VDDQ example:

I

RIPPLE_VBAT(MIN)

= 2.62A

and I

P-P

RIPPLE_VBAT(MAX)

= 3.28A

P-P

From this we can calculate the minimum inductor
current rating for normal operation:

II +=

I

)MAX(OUT)MIN(INDUCTOR

2

)MAX(VBAT_RIPPLE

A

)MIN(

For our DDR2 VDDQ example:

I

INDUCTOR(MIN)

= 11.6A

(MIN)

Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R
(R

ESR_ TR(M AX)

R

):

( )

=

)MAX(ST_ESR

I

ESR_ ST( MAX)

) and transient ESR

•−

2ERRERR

DCST

Ohms

)MAX(VBAT_RIPPLE

R

ESR_TR(MAX)

= 5.5mΩ for a full 10A load transient

We will select a value of 7.5mΩ maximum for our
design, which would be achieved by using two 15mΩ
output capacitors in parallel.

Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:

R

=

)MIN(ESR

3

••π•

fC2

SWOUT

This cr iteria should be chec ked once the output
capacitance has been determined.

Now that we know the output ESR we can calculate the
output ripple voltage:

•=

VIRV

PP)MAX(VBAT_RIPPLEESR)MAX(VBAT_RIPPLE

−

and

•=

VIRV

PP)MIN(VBAT_RIPPLEESR)MIN(VBAT_RIPPLE

−

Where ERRST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the feedba ck resist ors, thus 2 % total for 1%
feedback resistors.

For our DDR2 VDDQ example:

ERRST = 72mV and ERRDC = 36mV, therefore

R

ESR_ST( MAX)

R

= 22mΩ

( )

=

)MAX(TR_ESR




I

OUT




−

ERRERR

DCTR

I

+

2



)MAX(VBAT_RIPPLE






Ohms

Where ERRTR is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the I

OUT

term by 2.

For our DDR2 VDDQ example:

For our DDR2 VDDQ example:

V

RIPPLE_VBAT(MAX)

= 25mV

and V

P-P

RIPPLE_VBAT(MIN)

= 20mV

P-P

Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, VFB, should be approximately 15mV
V

, and wor st case no smal ler than 10 mV

BAT

V

RIPPLE_VBAT(MIN)

is less than 15mV

the above component

P-P

at minimum

P-P

P- P

. If

values should be revisited in order to improve this. A small
capacitor, C
feedback resistor, R
enough. C
of C

can be calculated as follows, where R

TOP

, may be required in parallel with the top

TOP

should not be greater than 100pF. The value

TOP

, in order to ensure that VFB is large

TOP

is the

BOT

bottom feedback resistor. Firstly calculating the value of
Z

required:

TOP

R

BOT

Z

TOP

( )

015.0

−•=

)MIN(VBAT_RIPPLE

Ohms015.0V

ERRTR = 100mV and ERRDC = 36mV, therefore

16 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

SC486

Design Procedure (Cont.)

Secondly calculating the value of C

required to achieve

TOP

this:



1






=

C

TOP

−

Z

•π•

f2

For our DDR2 VDDQ example we will use R
and R

V

FB_VBAT(MIN)

= 23.2kΩ, therefore

BOT

= 16.7mV

R

1

TOPTOP

P-P







F

)MIN(VBAT_SW

- good

= 4.64kΩ

TOP

No additional capacitance is required, however a no-pop
space is recommended to allow for adjustment once the
design is complete, laid out and built.

Next we ne ed to ca lculat e th e mi nimum outp ut
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIMTR,
starting from the actual static maximum, V

OUT_ST_POS

, when

a load release occurs:

+=

VERRVV

DCOUTPOS_ST_OUT

For our DDR2 VDDQ example:

V

OUT_ST_POS

= 1.836V

•=

VTOLVPOSLIM

TROUTTR

Where TOLTR is the transient tolerance. For our DDR2
VDDQ example:

POSLIMTR = 1.900V

The minimum output capacitance is calculated as
follows:

calculated by substituting the desired current for the I

OUT

term.

For our DDR2 VDDQ example:

C

OUT(MIN)

= 839µF.

We will select 440µF, u sing two 220µF, 15 mΩ
capacitors in parallel, which will be good for load release
steps of up to 6.7A.

Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:

I

( )

VVVI •−•=

OUT)MIN(BATOUT)RMS(IN

OUT

A

V

RMS

MIN_BAT

For our DDR2 VDDQ example:

I

= 4A

IN(RMS)

RMS

Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10µF,
1210 size , 25V cerami c capa citor can h andle
approximately 3A

. Refer to manufacturer’s data

RMS

sheets.

Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
looks at the “valley current”, which is the average output
current minus half the ripple current. We use the
maximum room temperature specification for MOSFET
R

at VGS = 4.5V for purposes of this calculation:

DS(ON)

I

−=

II

OUTVALLEY

)MIN(VBAT_RIPPLE

A

2

The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under
normal operating conditions.

2



)MAX(VBAT_RIPPLE






F

2

POS_ST_OUT

I

OUT

I

+

2

−

TR







•=

LC

)MIN(OUT

( )

2

VPOSLIM

This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highe st. The
capacitance required for smaller transient steps my be

•

4.1R

( )

VALLEYILIM

••=

2.1IR

For our DDR2 VDDQ example R

I

= 8.69A and R

VALLEY

)ON(DS

•

1010

= 13.1kΩ

ILIM

−

6

DS(ON)

Ohms

= 9mΩ:

We select the next lowest 1% resistor value: 13.0kΩ

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POWER MANAGEMENT

SC486

Thermal Considerations

The junction temperature of the device may be calculated
as follows:

°θ•+=

CPTT

JADAJ

Where:
TA = ambient temperature (°C)
PD = power dissipation in (W)

θJA = thermal impedance junction to ambient from

absolute maximum ratings (°C/W)

The power dissipation may be calculated as follows,
assuming that VTT spends 50% of its time sourcing
current and 50% sinking:

•+•=

IVDDPIVCCAP

VDDPVCCAD

••+••+

gg

( )

•−+

DmA1VBSTfQV

WITTVTTVTTIN

Where:
VCCA = chip supply voltage (V)
I

= operating current (A)

VCCA

VDDP = gate drive supply voltage (V)
I

= gate drive operating current (A)

VDDP

Vg = gate drive voltage, typically 5V (V)
Qg = FET gate charge, from the FET datasheet (C)
f = switching frequency (Hz)
VBST = boost pin voltage during tON (V)
D = duty cycle
VTTIN = input voltage for VTT LDO (V)
ITT = maximum VTT current (A)

Inserting the following values for VBAT

condition (since

(MIN)

this is the worst case condition for power dissipation in
the controller) as an example):

TA = 85°C

θJA = 29°C/W

VCCA = VDDP = 5V
I

= 2500µA (data sheet maximum)

VCCA

I

= 150µA (data sheet maximum)

VDDP

Vg = 5V
Qg = 60nC
f = 366kHz
VBAT
VBST
D

= 8V

(MIN)

= VBAT

(MIN)

= 1.8/8 = 0.225

1(MIN)

+VDDP = 13V

(MIN)

VDDQ = VTTIN = 1.8V
VTT = 0.9V
ITT = 1.2A

gives us:

66

D

−

( )

•+•=

39

=•−+

−−

e1505e25005P

••+••+

225.0mA113e366e605

W206.12.19.08.1

and therefore:

C12029206.185T

J

°=•+=

As can be seen, the heating effects due to internal power
dissipation are dominated by the VTT LDO, but they can
be managed comfortably by the MLPQ-24 package which
is heatsunk to the ground plane using 4 vias from its
thermal pad.

18 2006 Semtech Corp. www.semtech.com

SC486

POWER MANAGEMENT

Layout Guidelines

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star
connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are
referenced to VSSA should connect to it directly on the chip side, and not through the ground plane.

VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip.
Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and
PGND1) and connected directly to them on the same side.
VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to
the part to minimize parasitics.

The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections). Power components should be placed to minimize loops and
reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not
use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most
critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an accurate signal.

We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout
guidelines in more detail.

5VSUS 5VRUN

VDDQ

REF

C1

no-pop

VDDQ

VBAT

R2

R1

R4 10R

23k2

C2

1u

R7 10R

C10

no-pop

C3

no-pop

R9 0R

C15

10u

R6

R8

10R

C9

1u

R5 4k64

VTT

715k

C11

1n

C16

10u

10R

C12

1u

C17

1u

U1 SC486

11

VTTEN

3

VDDQS

2

TON

6

FB

8

REF

9

COMP

10

VTTS

5

VCCA

4

VSSA

14

VTT

15

VTT

12

VTTIN

13

VTTIN

16

PGND2

17

PGND2

PAD

PGD

EN/PSV

BST

ILIM

VDDP

PGND1

5VSUS

7

1

24

23

DH

LX

DL

R10 13k0

21

22

19

20

C18

1u

18

R3 470k

D1

C4

0.1uF

Q1

IRF7811AV

Q2

FDS6676S

VBAT

C5

2n2/50V

L1 1u5

PGOOD

C6

0u1/25VC710u/25VC810u/25V

VDDQ

+

C13
220u/15m

+

C14
220u/15m

Figure 4: DDR2 Reference Design and Layout Example

Sample DDR2 Design Using SC486
VBAT = 9V to 19.2V
VDDQ = 1.8V @ (8+2)A
VTT = 0.9V @ 2A

19 2006 Semtech Corp. www.semtech.com

SC486

Figure 8: Example VSSA 0.020” Trace

POWER MANAGEMENT

Layout Guidelines (Cont.)

The layout can be considered in three parts, the control section referenced to VSSA, the VTT output, and the
switcher power section. Looking at the control section first, locate all components referenced to VSSA1 on the
schematic and place these components at the chip. Connect VSSA using a wide (>0.020”) trace. Very little current
flows in the chip ground therefore large areas of copper are not needed. Connect the VSSA pin directly to the
thermal pad under the device as the

only connection to PGND from VSSA.

5VRUN

VDDQ

REF

C1

no-pop

R4 10R

R8

23k2

11

C12

1u

3

2

6

8

9

10

5

4

14
15

12
13

16
17

C2

1uR5 4k64

R7 10R

C10

no-pop

C3

no-pop

C11

1n

R6

10R

C9

1u

Figure 7: Components Connected to VSSA

U1 SC486

VTTEN

VDDQS

TON

FB

REF

COMP

VTTS

VCCA

VSSA

VTT
VTT

VTTIN
VTTIN

PGND2
PGND2

PAD

PGD

EN/PSV

BST

DH

ILIM

DL

VDDP

PGND1

7

1

24

23

21

22

LX

19

20

C18

18

1u

20 2006 Semtech Corp. www.semtech.com

SC486

POWER MANAGEMENT

Layout Guidelines (Cont.)

In Figure 8, all components referenced to VSSA have been placed and have been connected using a 0.020” trace.
Decoupling capacitor C12 is as close as possible to VCCA and VSSA and the VDDP decoupling capacitor C18 is as
close as possible to VDDP and PGND1. The feedback components R5, R8 and C1 along with the VDDQ sense
components, R4 and C2 are also located at the chip and the feedback trace from the VDDQ output should route
from the top of the output capacitors (C13 and C14) in a quiet layer back to these components. In Figure 8, the
VDDQ feedback trace would connect to the red trace.

C1

no-pop

R4 10R

R5 4k64

R8

23k2

VDDQ FEEDBACK

U1 SC486

11

VTTEN

3

C2

1u

VDDQS

2

TON

6

FB

8

REF

9

COMP

10

VTTS

5

VCCA

4

VSSA

14

VTT

15

VTT

12

VTTIN

13

VTTIN

16

PGND2

17

PGND2

PAD

EN/PSV

PGND1

PGD

BST

DH

ILIM

VDDP

7

1

24

23

21

22

LX

19

DL

20

18

Figure 9: VDDQ Feedback and Sense Components and Feedback Trace

+

C13
220u/15m

+

VDDQ

C14
220u/15m

21 2006 Semtech Corp. www.semtech.com

SC486

Figure 11: Example VDDQ Power Section Layout

POWER MANAGEMENT

Layout Guidelines (Cont.)

Next, looking at the switcher power section, the schematic in Figure 10 below shows the power section for VDDQ:

Q1 IRF 7811AV

1

S

2

S

3

S
G4D

8

D

7

D

6

D

5

D

8

D

7

D

6

D

5

Q2F DS6676 S

1

S

2

S

3

S

4

G

VBAT

C5

2n2/50V

L1 1u5

C6

0u1/25VC710u/25VC810u/25V

VDD Q

+

C13
220u/15m

+

C14
220u/15m

Figure 10: VDDQ Power Section and Input Loop

The highest di/dts occur in the input loop (highlighted in red) and thus this should be kept as small as possible. The
input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large
copper pours to minimize losses and parasitics. See Figure 11 below for an example.

22 2006 Semtech Corp. www.semtech.com

SC486

POWER MANAGEMENT

Layout Guidelines (Cont.)

Key points for the switcher power section:

1) there should be a very small input loop, well decoupled.

2) the phase node should be a large copper pour, but compact since this is the noisiest node.

3) input power ground and output power ground should not connect directly, but through the ground planes instead.

Connecting the control and switcher power sections should be accomplished as follows (see Figure 12 below):

1) Route VDDQ feedback trace in a “quiet” layer away from noise sources.

2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies,
thus should be kept as short as practical. DH has LX as its return path.

3) BST is also a noisy node and should be kept as short as possible.

4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.

U1 SC486

11

VTTEN

3

VDDQS

2

TON

6

FB

8

REF

9

COMP

10

VTTS

5

VCCA

4

VSSA

14

VTT

15

VTT

12

VTTIN

13

VTTIN

16

PGND2

17

PGND2

PAD

EN/PSV

PGND1

PGD

BST

ILIM

VDDP

DH

7

1

24

Q1

23

21

22

LX

19

DL

20

18

R10 13k0

IRF7811AV

L1 1u5

Q2

FDS6676S

Figure 12: Connecting Control and Switcher Power Sections

Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical. Use multiple
vias when switching between layers. Locate the current limit resistor (R10) at the chip with a kelvin connection to
the phase node.

23 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Figure 14: Example VTT Output Component Placement and Starred Ground

Output capacitors C15 and C16 are placed across the device pins, and connect to the ground plane using multiple
vias. Input capacitor C17 connects directly to the device pins and connects to the ground plane using two vias. Note
that PGND1, PGND2 and VSSA all connect to the pad under the device, which should also connect to the ground
plane using multiple vias.

Layout Guidelines (Cont.)

Next looking at the VTT output:

SC486

VDD Q

VTT

C15

10u

C16

10u

C17

1u

U1 SC 486

11

VTTEN

3

VDD QS

2

TON

6

FB

8

REF

9

COMP

10

VTTS

5

VCC A

4

VSSA

14

VTT

15

VTT

12

VTTIN

13

VTTIN

16

PGND 2

17

PGND 2

PAD

EN/ PSV

PGND 1

PGD

BST

DH

ILI M

DL

VDD P

7

1

24

23

21

22

LX

19

20

18

Figure 13: VTT Output

The output capacitors should be connected right at the chip, on the same side as the chip and right across the pins.
The input capacitor may be placed on the opposite side, if desired. See Figure 14 below:

24 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Outline Drawing - MLPQ-24 (4 x 4mm)

SC486

PIN 1

INDICATOR

(LASER MARK)

A

aaa C

E1

A

A1

2

1

D

D1

LxN

B

E

A2

SEATING

C

E/2

PLANE

DIM

MIN

.031

A

A1

.000

-

A2

b .007

.152 .163

D

D1

.100

E

.152 .163

E1

.100

e
L

.012

N

aaa
bbb

DIMENSIONS

INCHES

NOM

MAX

.039

.035

.002

.001

(.008)

.020 BSC

-

.010
.157
.106

.110
.157
.106 .110 2.55

.020

.016

24
.004
.004

MILLIMETERS

NOM

0.90

0.02

(0.20)

0.25

4.00

2.70

4.00 4.153.85

2.70

0.50 BSC

0.40
24

0.10

0.10

MAX

1.00

0.05

-

0.30

4.153.85

2.80

2.80

0.50

MIN

0.80

0.00

-

0.18.012

2.55

0.30

N

e

D/2

bxN

bbb C A B

NOTES:

1.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

2.

25 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Land Pattern - MLPQ-24 (4 x 4mm)

K

(C)

H

X

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.

2.

THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.

SC486

DIMENSIONS

DIM

C
G

G

Z

H

K
P
X
Y

(.156)

.122
.106
.106
.020
.010
.033

MILLIMETERSINCHES

(3.95)

3.10

2.70

2.70

0.50

0.25

0.85

4.80.189Z

Contact Information

Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012

Phone: [phone] FAX [phone]

26 2006 Semtech Corp. www.semtech.com