SEMTECH SC4808B-1 Technical data

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Description Features

The SC4808B-1 is a dual-ended, high frequency, integrated
PWM controller, optimized for isolated applications that
require minimum space. It can be configured for current
or voltage mode operation with required control circuitry
where secondary side error amplifier is used.

Some of the key features are high frequency operation of
1 MHz that allows the use of smaller components thus
saving cost and valuable board space. An internal ramp
on the Current Sense pin allows Internal Slope
Compensation programmed by an external resistor. Other
features include programmable frequency up to 1MHz,
Pulse by Pulse current and Line Monitoring Input with
Hysteresis to reduce stress on the power components.

A unique oscillator is used to synchronize two SC4808B­1’s to work out of phase. This minimizes the input and
output ripple thus reducing noise on the output line and
reducing stress and size of input/output filter components.
The dual outputs can be configured in Push-Pull, Half Bridge
and Full Bridge format with programmable dead time
between two outputs depending on the size of the timing
components.

The SC4808B-1 also features a turn on threshold of 4.4V
and is available in MSOP-10 package.

 120µA starting current
 Pulse by pulse current limit
 Programmable operation up to 1MHz
 Internal soft start
 Programmable line undervoltage lockout
 Over current shutdown
 Dual output drive stages on push-pull configuration
 Programmable internal slope compensation
 Programmable mode of operation (peak current mode

or voltage mode)

 External frequency synchronization
 Bi-phase mode of operation
 -40 to 105 °C operating temperature
 MSOP-10 lead free package. This product is fully WEEE

and RoHS compliant

Applications



 Telecom equipment and power supplies




 Networking power supplies


 Industrial power supplies
 Push-pull converter
 Half bridge converter
 Full bridge converter
 Isolated VRM’s

SC4808B-1

High Performance Dual

Ended PWM Controller

Typical Application Circuit

Vin

Gnd_In

RSENSE

SYNC

OUTA

OUTB

CS

VCC

SYNC

LUVLO

SC4808

Vo

Gnd_Out

RC

REF

FB

GND

Revision: January 11, 2006

1 www.semtech.com

SC4808B-1

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Absolute Maximum Ratings

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.

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Electrical Characteristics

Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C

CC

CC

BF

FER

B/ATUO

ecruos

knis

D

θ

AJ

J

GTS

DAEL

DSE

81ot5.0-V

02Am

V(ot5.0-

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FER

01Am

81ot5.0-V

052-Am

052Am

501.1W

1.311W/C°

051ot04-C°

051ot56-C°

003+C°

2Vk

retemaraPsnoitidnoCtseTniMpyTxaMtinU

MWP

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849405%

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BTUOroATUOtaderusaeM

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2 2006 Semtech Corp. www.semtech.com

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Electrical Characteristics (Cont.)

Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C

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dlohserhTtratS 0.404.45.4V

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tuokcoLegatloVrednUeniL

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SC4808B-1

siseretsyHk41=32R Ω k01=33R, Ω )11egapees(

tratStfoS

pmaRtratStfoSlanretnI 002V/sµ

noitaruDtratStfoSk1=scR Ω

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)81egapnonoitcesnoitamrofni

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pmaRrotallicsO 2/FERV

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egnaRycneuqerFrotallicsO 050001zHK

KCOLC/cnyS

dlohserhTCNYSkcolC 0.1V

egnaRycneuqerFcnyS F

pagdnaB

k11= Ω C,

cso

cso

Fp002=054005055zHK

fo%6.5

FERV

21sµ

52.0+

cso

Vm

V

3.1*zHK

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Pin Configuration Ordering Information

SC4808B-1

Top View

(MSOP-10)

rebmuNtraPegakcaPT(egnaR.pmeT

)2()1(

TRTSM1-B8084CS

01-POSMC°501otC°04-

A

Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.

)

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Pin Descriptions

SC4808B-1

FB: The inverting input to the PWM comparator. Stray in­ductances and parasitic capacitance should be minimized
by utilizing ground planes and correct layout guide lines
(see page 19).

REF: Bandgap reference output It should be by passed with
a 2.2uF low ESR capacitance, right at the IC pin.

CS: Current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feed back volt­age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro­vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved.

RC: The oscillator programming pin. The oscillator should
be referenced to a stable reference voltage for an accu­rate and stable frequency. Only two components are re­quired to program the oscillator, a resistor (tied to Vref and
RC), and a capacitor (tied to the RC and GND). The follow­ing formula can be used for a close approximation of the
oscillator frequency.

F

≅

_

AOSC

1

CR

×

TOTOSC

F

≅

_

8.0

BOSC

1

CR

9.0

×

TOTOSC

where:

CCCC ++=

CircuitSCOSCTOT

4808

LUVLO: Line undervoltage lockout pin. An external resis­tive divider will program the undervoltage lockout level. The
external divider should be referenced to the quiet analog
ground (see page 19). During the LUVLO, the driver out­puts are disabled and the softstart is reset. This pin can
also function as an Enable/Disable.

SYNC: SYNC is a positive edge triggered input with a thresh­old set to 1.0V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization
clock within the SYNC frequency range (see page 3). In
the Bi-Phase operation mode SYNC pins could be con­nected to the Cosc (Timing Capacitors) of the other con­troller. This will force an out of phase operation (see page

12).

GND: Device power and analog ground. Careful attention
should be paid to the layout of the ground planes (see page

19).

OUTA and OUTB: Out of phase gate drive stages. The
driver’s peak source and sink current drive capability of
100mA, enables the use of an external MOSFET driver or
a NPN/PNP transistor buffer.
The oscillator RC network programs the oscillator frequency,
which is twice the OUTA/OUTB frequency. To insure that
the outputs do not overlap, a dead time can be generated
between the two outputs by sizing the oscillator timing
capacitor (see page 11).

VCC: The supply input for the device. Once VCC has ex­ceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. A low ESR capacitance,
should be used for decoupling right at the IC pin to mini­mize noise problems.

pFC

≅

SC224808

Where the frequency is in Hertz, resistance in ohms, and
capacitance in farads. The recommended range of timing
resistors is between 10 kohm and 200kohm and range of
timing capacitors is between 100pF and 1000pF. Timing
resistors less than 10 kohm should be avoided.
Refer to layout guide lines on (page 19) to achieve best
results.

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Block Diagram

SC4808B-1

VCC

REF

Bandgap

UVLO

LUVLO

Marking Information

LUVLO

SQ

R

OVER CURRENT

SOFT
START

500mv

Slope Comp.

Enable

R

2R

FB

Peak Current

OSC

RC

CS

OUTA

Disable

LUVLO

OUTB

GND

SYNC

SYNC

SQ

R

Q

T

Q

Top Mark

AB1B

yyww

Bottom Mark

xxxx

xxxx

yyww = Datecode (Example: 9912)
xxxx = Semtech Lot # (Example: E901
xxxx 01-1)

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SC4808B-1 Typical Characteristics
(SC4808B-1A)

SC4808B-1

100.0

Start up Iq, Vcc = 4V

95.0

90.0

85.0

Iq(uA)

80.0

75.0

70.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Iq (start up) vs. Temperature

3.90

3.85

3.80

3.75

Iq (mA)

3.70

3.65

Operating Iq, Vcc = 5V

Operating Iq, Vcc = 5.25V

1.69

1.68

1.67

1.66

1.65

1.64

1.63

FB to CS offset (V)

1.62

1.61

1.60

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

FB to CS Offset

FB to CS Offset vs. Temperature

1100

1000

Current Sense (mV)

900

800

700

600

500

Max Current Sense Signal

Over Current Signal

3.60

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Iq (operating) vs. Temperature

3.22

Reference, Vcc = 5V

3.21

3.2

3.19

Reference (V)

3.18

3.17

3.16

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Reference vs. Temperature

400

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Current sense vs. Temperature

4.500

4.450

4.400

4.350

Vcc UVLO (V)

4.300

4.250

4.200

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Vcc UVLO (Rising)

Vcc UVLO (Falling)

Vcc UVLO vs. Temperature

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SC4808B-1 Typical Characteristics (Cont.)

SC4808B-1

100

98

96

94

92

90

88

Vcc UVLO Hysteresis (mV)

86

84

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Vcc UVLO (Hysteresis)

Vcc UVLO Hysteresis vs. Temperature

3.170

3.165

3.160

3.155

3.150

3.145

3.140

LUVLO (V)

3.135

3.130

3.125

3.120

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

LUVLO (Rising)

Line UVLO vs. Temperature

1400

1200

1000

Oscillator Frequency (kHz)

800

600

400

200

Oscillator Frequency 1MHz

Oscillator Frequency 500kHz

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Oscillator Frequency vs. Temperature

664

662

660

658

656

654

Synchronization Frequency (kHz)

652

650

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Sync. Frequency @ Fosc = 500kHz

Synchronization Frequency vs. Temperature

140

135

130

125

120

115

110

LUVLO Hysteresis (mV)

105

100

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

LUVLO (Hysteresis)

Line UVLO Hysteresis vs. Temperature

49.5

Maximum Duty Cycle

49.5

49.5

49.4

49.4

49.4

Maximum Duty Cycle (%)

49.4

49.4

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Maximum Duty Cycle vs. Temperature

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SC4808B-1 Typical Characteristics (Cont.)

SC4808B-1

180

170

160

150

140

130

120

110

Soft Start Delay Time (us)

100

90

80

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ta (°C)

Soft Start Delay Time

Soft Start Delay time vs. Temperature

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Application Information

THEORY OF OPERATION

SC4808B-1

The SC4808B-1 is a versatile double ended, high speed,
low power, pulse width modulator that is optimized for ap­plications requiring minimum space.
The device contains all of the control and drive circuity re­quired for isolated or non isolated power supplies where
an external error amplifier is used. A fixed oscillator fre­quency (up to 1MHz) can be programmed by an external
RC network.
The SC4808B-1 is a peak current or voltage mode
controller, depending on the amount of slope
compensation, programmable with only one external
resistor. The cycle by cycle peak current limit prevents core
saturation when a transformer is used for isolation while
the overcurrent circuitry initiates the softstart cycle.
The SC4808B-1 dual output drive stages are arranged in a
push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip flop. The dead time
between the two outputs is programmable depending on
the values of the timing capacitor and resistors, thus limiting
each output stage duty cycle to less than 50%.
The SC4808B-1 also provides flexibility with programmable

LUVLO thresholds, with built-in hysteresis.

SUPPLY

A single supply, VCC is used to provide the bias for the
internal reference, oscillator, drivers, and logic circuitry of
SC4808B-1. To ensure proper operation during start up,
VCC slew rate of less than 10V/mS is recommended.

PWM CONTROLLER

SC4808B-1 is a double ended PWM controller that can be
used in voltage or current mode applications. The
SC4808B-1 provides a 4.4V VCC UVLO, and a 3.125V ref­erence. The oscillator frequency is programmed by a resis­tor and a capacitor network connected to an external refer­ence provided by the SC4808B-1. The two outputs, OUTA
and OUTB, are 180 degrees out of phase and run at half of
the oscillator frequency.
An external error amplifier will provide the error signal to
the FB pin of the SC4808B-1.
The current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feedback volt-

age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro­vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved. The error amplifier signal at the FB pin will be
used in conjunction with the CS signal to achieve regula­tion.
Two levels of undervoltage lockout are also available. The
LUVLO (line under voltage lockout) pin via an external re­sistive divider will program the undervoltage lockout level.
During the LUVLO, the driver outputs are disabled and the
softstart is reset.
Once VCC has exceeded the UVLO (VCC under voltage lock­out) limit, the internal reference, oscillator, drivers and logic
are powered up.

SYNC is a positive edge triggered input with a threshold
set to 1.0V.
By connecting an external control signal to the SYNC pin,
the internal oscillator frequency will be synchronized to the
positive edge of the external control signal. In a single con­troller operation, SYNC should be grounded or connected
to an external synchronization clock within the SYNC fre­quency range (see page 3).
In the Bi-phase operation mode a very unique oscillator
is utilized to allow two SC4808B-1 to be synchronized
together and work out of phase. This feature is setup by
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of
phase. This feature minimizes the input and output
ripples, and reduces stress on the capacitors.

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0

0

Application Information (Cont.)

SC4808B-1

VCC UNDER VOLTAGE LOCK OUT

Depending on the application and the voltages available,
the SC4808B-1 (UVLO = 4.4V) can be used to provide the
VCC undervoltage lock out function to ensure the convert­ers controlled start up.
Before the VCC UVLO has been reached, the internal refer­ence, oscillator, OUTA/OUTB drivers, and logic are disabled.

LINE UNDER VOLTAGE LOCK OUT

The SC4808B-1 also provides a line undervoltage (LUVLO
= Vref) function. The LUVLO pin is programmed via an ex­ternal resistor divider connected as shown below. The ac­tual start-up voltage can be calculated by using the equa­tion below:

33R23R

+

()

×=

33R

VCC

6

7

8

9

C33

101

0.1u,25V

10k

R33

R27
15k

C31
200p

REF

5

4

3

2

REF

FB

CS

RC

SYNC

Vin

2.2u,16V

U4

SC4808

C26

GND

OUTB

OUTA

VCC

LUVLOSYNC

56.2k

R23

R28
10

15

R26

2.2k

C29

82p

VV

R24 10k

R25 18

REFStartup

OSCILLATOR

The oscillator frequency is set by connecting a RC network
as shown below.

VCC

C33

0.1u,25V

10k

R33

R28
10

6

7

8

9

101

R27
15k

C31
200p

REF

5

4

3

2

REF

FB

CS

RC

SYNC

Vin

2.2u,16V

U4

SC4808

C26

GND

OUTB

OUTA

VCC

LUVLOSYNC

56.2k

R23

The oscillator has a ramp voltage of about Vref/2. The os­cillator frequency is twice the frequency of the OUTA and
OUTB gate drive controls.

The oscillator capacitor C31 is charged by a current sourced
from the Vref through R27. Once the RC pin reaches about
Vref/2, the capacitor is discharged internally by the
SC4808B-1. It should be noted that larger capacitor val­ues will result in a longer dead time during the down slope
of the ramp.
The following equation can be used as an approximation
of the oscillator frequency and the Dead time:

F

≅

_

AOSC

1

CR

×

TOTOSC

F

≅

_

8.0

BOSC

1

CR

9.0

×

TOTOSC

REFERENCE

A 3.125V(SC4808B-1) reference voltage is available that
can be used to source a typical current of 5mA to the ex­ternal circuitry. The Vref can be used to provide the oscilla­tor RC network with a regulated bias.

where:

CCCC ++=

CircuitSCOSCTOT

4808

pFC

≅

SC224808

T

deadtime

≅

VC

103

⋅

5.0

××

REFOSC

3

−

The recommended range of timing resistors is between 10
kohm and 200kohm, range of timing capacitors is between
100pF and 1000pF. Timing resistors less than 10 kohm
should be avoided.

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Application Information (Cont.)

SC4808B-1

SYNC/Bi-Phase operation

In noise sensitive applications where synchronization of
the oscillator frequency to a reference frequency is required,
the SYNC pin can accept the external clock. By connecting
an external control signal to the SYNC pin, the internal os­cillator frequency will be synchronized to the positive edge
of the external control signal. SYNC is a positive edge trig­gered input with a threshold set to 1.0V (SC4808B-1).
In a single controller operation, SYNC should be grounded
or connected to an external synchronization clock within
the SYNC frequency range (see page 3).

OUTA (PWM1)

OUTB (PWM1)

OUTA (PWM2)

OUTB (PWM2)

Rosc1

Cosc1

REF

U1

5

REF

4

FB

3

CS

2

RC

LUVLOSYNC

GND

OUTB

OUTA

VCC

6

7

8

9

101

Rosc2

Cosc2

REF

U2

5

REF

4

FB

3

CS

2

RC

LUVLOSYNC

GND

OUTB

OUTA

VCC

6

7

8

9

101

FEED BACK

The error signal from the output of an external error ampli­fier such as SC431 or SC4431 is applied to the inverting
input of the PWM comparator at the FB pin either directly
or via an opto coupler for the isolated applications. For best
stability, keep the FB trace length as short as possible.

Vref

R37

2.2k

C40
22pF

6

5

MOCD207

FB

R34

3

4

C38

0.1u

5

C39
22n

C35

1

4

SC4431

Vref

2

VoutVout

R35C36

R32

R36

C37

R38

The signal at the FB pin is then compared to the 3X ampli­fied signal from the current sense/ slope compensation
CS pin. Matched out of phase signals are generated to
control the OUTA and OUTB gate drives of the two phases.
A single ramp signal is used to generate the control sig­nals for both phases, hence achieving a tightly matched
per phase operation.
Voltages below 1.5V at the FB pin, will produce a 0% duty
cycle at the OUTA/OUTB gate drives. This offset is to pro­vide enough head room for the opto coupler used in iso­lated applications.

GATE DRIVERS

SC4808

SC4808

In the Bi-phase operation mode a very unique oscillator is
utilized to allow two SC4808B-1’s to be synchronized
together and work out of phase. This feature is set up by a
simple connection of the SYNC input to the RC pin of the
other part. The fastest oscillator automatically becomes
the master, forcing the two PWMs to operate out of phase.
This feature minimizes the input and output ripples, and
reduces stress on the capacitors.

OUTA and OUTB are out of phase bipolar gate drive output
stages, that are supplied from VCC and provide a peak
source/sink current of about 100mA. Both stages are ca­pable of driving the logic input of external MOSFET drivers
or a NPN/PNP transistor buffer. The output stages switch
at half the oscillator frequency. When the voltage on the
RC pin is rising, one of the two outputs is high, but during
fall time, both outputs are off. This “dead time” between
the two outputs, along with a slower output rise and fall
time, insures that the two outputs can not be on at the
same time. The dead time is programmable and depends
upon the timing capacitor.

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F

Application Information (Cont.)

It should be noted that if high speed/high current drivers
such as the SC1301 are used, careful layout guide lines
must be followed in order to minimize stray inductance,
which might cause negative voltages at the output of the
drivers. This negative voltage can be clamped to a reason­able level by placing a small Schottky diode directly at the
output of the driver as shown below.

VCC

EN

SC1301A
U3

C23

R28
10

0.1u

C34

0.1u

VCC

C26

2.2u,16V

U4

5

REF

4

FB

3

CS

2

RC

SC4808

SYNC

Vin

OUTB

OUTA

LUVLOSYNC

GND

VCC

56.2k

R23

6

7

8

9

C33

101

0.1u,25V

10k

R33

325

1 4

VCC

EN

SC1301A
U6

3

5

1 4

2

Gate_B

D_B

Gate_A

D_A

SC4808B-1

OVER CURRENT

Two levels of over current protection are provided by the
SC4808B-1. The current information is sensed at the CS
pin and compared to a peak current limit level of 525mV.
If the 525mV limit is exceeded, the OUTA and OUTB pulse
widths and duty cycle is reduced until the CS pin reaches a
second threshold of 950mV. At that point, the OUTA and
OUTB are disabled, and after a delay of 140µs, the inter­nal softstart sequence is started. After the softstart dura­tion (see page 18 for calculation of softstart time), normal
operation is achieved, unless the over current condition is
still present.

13 2006 Semtech Corp. www.semtech.com

SC4808B-1

POWER MANAGEMENT

Application Information (Cont.)

SLOPE COMPENSATION (Current or Voltage mode of operation)

In applications where a current mode control is used for regulation, the peak inductor current information is used to
produce the average output current. If a small perturbation due to changes in supply voltage or noise pick up is gener­ated, instability may occur if the duty cycle is >50%.
This phenomenon is graphically shown below. The inductor current and disturbed inductor current are shown for three
different duty cycles conditions.
The top wave form shows the applications where the duty cycle D is less than 50%. As shown, even if an error is
introduced, after only a few cycles the error converges to zero.
The second wave form shows the case where D = 50%. Under this condition, even though the error does not completely
disappear, it stays constant and is not getting larger. This will be seen as jitter at the inductor voltage.
The bottom wave form shows D>50%. As shown, a very small error results in a much larger error only after a few cycles.
This will cause instability in the converter and the average output inductor current. The output load will not be able to be
kept in regulation.

i

: Small Inductor current perturbation

L

: Inductor current

I

L

D<50%

Error

Error

Time

D=50%

Time

I

I

i

L

L

L

i

L

Instability in current mode operation

due to Duty cycle >50%

Note: After a few c ycles the perturbation
disappear s and stable operation returns .

i

L

Note: After a few c ycles the perturbation
is still present, although this will cause
jitter, but there is no instability.

Error

D>50%

Time

I

i

L

L

Note: After a few c ycles the perturbation
becom es larger, and caus es instability.

14 2006 Semtech Corp. www.semtech.com

i

L

POWER MANAGEMENT

()

Application Information (Cont.)

SC4808B-1

The instability can be corrected by modification of the peak
current information slope. One of the methods to alter the
peak current information is to add a positive going ramp to
the output of the current sensing circuitry.
The SC4808B-1 achieves this by using an internal slope
compensation circuit. The oscillator ramp is internally buff­ered and an internal 25kOhms resistor in conjunction with
an external resistor at the CS pin will program the level of
slope compensation.

Current Transformer

N = 100

10k

R

D

Rsense

RSlope Comp

Cfilter

82p

RSlope Comp value will determine the Mode of operation (Voltage or Current)

Rosc
15k

Cosc
200p

REF

C

2.2u,16V

5

REF

4

FB

25k

3

CS

2

RC

1

SYNC

SC4808

GND

6

7

The Peak current information is sensed and the result is
realistically summed to the buffered oscillator ramp, as
shown above. The value of the external resistor R

slope comp

will determine the percentage of the slope compensation.
As the value for R

slope comp

is reduced, the current informa­tion becomes more dominant and the mode of operation
becomes more current mode. At the same time the slope
of the current information is modified to provide the slope
compensation.

If the R

slope comp

is increased, the internal ramp becomes the
dominant signal and more voltage mode of operation is
achieved. As it can be calculated from the second formula
below, a 100% voltage mode operation can be achieved by
choosing R

slope comp

100% current mode of operation is required, R

to be greater than 6.25K ohms. Also if a

slope comp

is
reduced to zero and the contribution from the internal ramp
is completely eliminated.

+

RR

×

V

Ramp

=

Comp_Slope%

()

V

CS

senseComp_slope

++

RRR

ernalintsenseComp_slope

or



RR

•≅

ernalintexternal




()

×

()

×−

Comp_slope%2.0

Comp_slope%2.01






Next page illustrates how the buffered oscillator ramp is
used to modify the sensed inductor current.
It should be noted that in order for the slope compensa­tion to be effective, the current sensed signal slope should
be at least 50% less steeper than the oscillator positive
ramp slope. The slope will include the magnetizing current
of the transformer and the inductor output current in iso­lated applications. In non-isolated applications, the slope
will only include the inductor output current.

15 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Application Information (Cont.)

i

: Sm all Inductor current perturbation

L

: Inductor current

I

L

I

: Sensed Mosfet current

Sense

: Sum m ation of Isense and s lope compensation, at the C S pin of the SC4808.

I

CS

I

L

I

Sense

SC4808B-1

Slope Compensation generation from

Buffered Oscillator Ramp

D>50%

Note: Below wave form s are not to scale.

Buffered
Oscillator
Ramp

I

CS

16 2006 Semtech Corp. www.semtech.com

SC4808B-1

POWER MANAGEMENT

Application Information (Cont.)

Below the benefits from the slope compensation become apparent. The top wave form shows the stable operation
before the perturbation. The second wave form shows the perturbation and the instability caused from it if no slope
compensation is added to the current information. The last wave form shows the slope compensation and the effect of
it. The increase in the slope of the current information results in an early termination of the inductor current, hence a
reduction in the amount of error. As the cycle is repeated, the perturbation is reduced and finally eliminated.

δ

i

: Small Inductor current perturbation

L

∆

: Inductor current

I

L

: Sensed Mosfet current

I

Sense

: Summation of Isense and slope compensation, at the CS pin of the SC4808.

I

CS

Stable operation
( no perturbation)

∆

I

L

I

Sense

Instable operation
( with perturbation)

∆

I

L

δ

i

I

Sense

Stable operation
(Slope Compensation Added)

L

Stable current mode operation with Slope

Compensation

D>50%

Error Signal from Error amplifier

Note: After a few cycles the perturbation
becomes larger, and causes instability.

Error Signal from Error amplifier

Note: After a few cycles the perturbation
disappears and stable operation returns.

Error Signal from Error amplifier

∆

I

L

I

CS

δ

i

L

17 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT





Application Information (Cont.)

SC4808B-1

SOFT START

During start up of the converter, the discharged output ca­pacitor and the load current have large supply current re­quirements. To avoid this a soft start scheme is usually
implemented where the duty cycle of the regulator is gradu­ally increased from 0% until the soft start duration is
elapsed.
SC4808B-1 has an internal soft start circuit that limits the
duty cycle for a duration approximated by the formula be­low. Also the soft start circuitry is activated if an over cur­rent condition occurs. After an over current condition, OUTA
and OUTB are disabled and kept low for a duration of about
140µs. After the delay, the OUTA and OUTB are enabled
while the soft start limits the duty cycle. If the over current
condition persists, the soft start cycle repeats indefinitely.
Approximate internal soft start duration can be calculated
as below:

T

SoftStart

VREF

()

Ramp

SoftStart

≅



R




R

SlopeComp_Internal



×




GND_to_CS




2






1

+



START UP SEQUENCE

Initially during the power up, the SC4808B-1 is in under
voltage lock out condition. As the Vcc supply exceeds the
UVLO limit of the SC4808B-1, the internal reference, oscil­lator, and logic circuitry are powered up.
The OUTA and OUTB drivers are not enabled until the line
under voltage lock out limit is reached. At that point, once
the FB pin is above 1.5V, soft start circuitry starts the out­put drivers, and gradually increases the duty cycle from
0%. The soft start duration is internally set (see formula in
Soft Start section).
As the output voltage starts to increase, the error signal
from the error amplifier starts to decrease. If isolation is
required, the error amplifier output can drive the LED of
the opto isolator. The output of the opto is connected in a
common emitter configuration with a pull-up resistor to a
reference voltage connected to the FB pin of the SC4808B-

1. The voltage level at the FB pin provides the duty cycle
necessary to achieve regulation.
If an over current condition occurs, the outputs are dis­abled and after a soft start delay time of about 100µs, the
softstart sequence mentioned above is repeated.

If longer soft start durations are required, the simple exter­nal circuit shown below can be implemented.

VCC

C33

0.1u,25V

10k

R33

R28
10

6

7

8

9

101

MOCD207

R37
1k

6

C40

NA

5

Csoft start

REF

56.2K

R27
15k

C31
200p

REF

5

4

3

2

REF

FB

CS

RC

SYNC

SC4808

Vin

C26

2.2u,16V

U4

GND

OUTB

OUTA

VCC

LUVLOSYNC

56.2k

R23

Approximate soft start duration can be calculated as be­low:

37RCT

SoftStartSoftStart

×≅

18 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Application Information (Cont.)

LAYOUT GUIDELINES

SC4808B-1

Careful attention to layout requirements are necessary for
successful implementation of the SC4808B-1 PWM con­troller.
High current switching is present in the application and
their effect on ground plane voltage differentials must be
understood and minimized.

1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and po­sition of ground plane interruptions should be such as to
not unnecessarily compromise ground plane integrity. Iso­lated or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas, such as the input capacitor and FET
ground.

2). In the loop formed by the Input Capacitor(s) (Cin), the
FET must be kept as small as possible. This loop contains
all the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in electri­cally “cleaner” grounds for the rest of the system and c)
minimize source ringing, resulting in more reliable gate
switching signals.

3). The connection between FETs and the Transformer
should be a wide trace or copper region. It should be as
short as practical. Since this connection has fast voltage
transitions, keeping this connection short will minimize EMI.

4) The Output Capacitor(s) (Cout) should be located as close
to the load as possible. Fast transient load currents are
supplied by Cout only, and connections between Cout and
the load must be short, wide copper areas to minimize in­ductance and resistance.

5) The SC4808B-1 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin FET loop flowing in
this area. GND should be returned to the ground plane close
to the package and close to the ground side of (one of) the
VCC supply capacitor(s). Under no circumstances should
GND be returned to a ground inside the Cin, Q1, Q2 loop.
Avoid making a star connection between the quiet GND
planes that the SC4808B-1 will be connected to and the
noisy high current GND planes connected to the FETs.

6) The feed back connection between the error amplifier
and the FB pin should be kept as short as possible The
GND connections should be connected to the quiet GND
used for the SC4808B-1.

7) If an Opto isolator is used for isolation, quiet primary
and secondary ground planes should be used. The same
precautions should be followed for the primary GND plane
as mentioned in item 5 mentioned above. For the second­ary GND plane, the GND plane method mentioned in item
4 should be followed.

8) All the noise sensitive components such as LUVLO re­sistive divider, reference by pass capacitor, Vcc bypass ca­pacitor, current sensing circuitry, feedback circuitry, and
the oscillator resistor/capacitor network should be con­nected as close as possible to the SC4808B-1. The GND
return should be connected to the quiet SC4808B-1 GND
plane.

9) The connection from the OUTA and OUTB of the
SC4808B-1 should be minimized to avoid any stray induc­tance. If the layout can not be optimized due to constraints,
a small Schottky diode may be connected from the OUTA/
B pins to the ground directly at the IC. This will clamp ex­cessive negative voltages at the IC. If drivers are used, the
Schottky diodes should be connected directly at the IC from
the output of the driver to the driver ground (See page

13).

10) If the SYNC function is not used, the SYNC pin should
be grounded at the SC4808B-1 GND to avoid noise pick
up.

19 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Gain & Phase Margin

SC4808B-1

50

40

30

20

10

Gain (dB)

0

-10

-20

Phase

Gain

Gain

Phase (deg)

225

180

135

90

45

0

Phase (deg)

-45

-90

-135

-180

-30
10 100 1000 10000 100000

Freq (Hz)

-225

Typical SC4808B-1 Push Pull Converter Gain/Phase plot at Vin = 36V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz

20 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Gain & Phase Margin (Cont.)

SC4808B-1

50

40

30

20

10

Gain (dB)

0

-10

-20

Phase

Gain

Gain

Phase (deg)

225

180

135

90

45

0

Phase (deg)

-45

-90

-135

-180

-30
10 100 1000 10000 100000

Freq (Hz)

-225

Typical SC4808B-1 Push Pull Converter Gain/Phase plot at Vin = 48V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz

21 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Gain & Phase Margin (Cont.)

SC4808B-1

50

40

30

20

10

Gain (dB)

0

-10

-20

Phase

Gain

Gain

Phase (deg)

225

180

135

90

45

0

Phase (deg)

-45

-90

-135

-180

-30

10 100 1000 10000 100000

Freq (Hz)

-225

Typical SC4808B-1 Push Pull Converter Gain/Phase plot at Vin = 72V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz

22 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Typical Step Load

SC4808B-1

Vout

500mV/Div

Iout

5A/Div

Cout = 6X22uF (132uF) Ceramic

Typical SC4808B-1 Push Pull Converter Step Load plot at Vin = 48V, Vout = 3.3V, Step = 37% to 75% Iout, Fosc = 650kHz

100us/Div

23 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

V

Evaluation Board Schematics

Size Document Number Rev

Date: Sheet of

SC4808EVB__non_sync 1.1

11Monday, October 07, 2002

For output power > 30W, adequate air flow should be provided to avoid over dissipation.

Title

SC4808 Push Pull 3.3V 50W non Synchronous

Note:

SEMTECH CORPORATION

SC4808B-1

Vin-

ON/OFF

4

2

2

R10

Vout-

D4

1N5819HW

M1

M2

1N5819HW

U7

CBRHD-02

5

0

D3

AC

EBC

VCC = 15V

1 3

1N5819HW

1

1

34

T1

0

2

1u,100V

1u,100V

R8

VCC

1u,100V

N = 100

SUD19N20-90

3

3

SUD19N20-90

R3116.2

4T

6

D2

0

R7

TBD

6

Sense-

C11

C12

Q1

C13

1

3

R6

in+

1

20k

FZT853

8

C32.2n

4

1

22u,6.3V

22u,6.3V

22u,6.3V

22u,6.3V

22u,6.3V

22u,6.3V

0.1u

0.1u

CON2

R3

R4

250

8 7

6T 1T

R510

MBRB2535CTL

0.9uH

C4

C5

C6

C7

C8

C9

C10

C2

7

Trim

GRM55DR72E105KW01

GRM55DR72E105KW01

P8208T

T2

6T 1T

253

4

PA0500

10

9

C12.2n

R210

4

MBRB2535CTL

D1

1

3

1 2

PG0006.102T

L1

Murata GRM32DR60J226KA01

R1

0

8

9

Sense+

Vout+

CON1

3input_half_brick

R12

56.2k

2.2uF 16V

56.2k

C35

R32

REF

ZM4743A

C14

LS4448

453

FB

OUTB

OUTA

VCC

G_A

3

4

1u,16V

C20

Sync Drive Supply

1k

15k

REFCSRC

GND

10

1

6

CMOSH-3

CMOSH-3

R16

R17

U1

R18

T3

D10

D11

2

CMOSH-3

0

D8

R13 10k

R14 15

J1

REF

2.2u,16V

C19

J2

VCC

C17

0.1u

1 4

VCC

3
5

SC1301A

U2

CMOSH-3

D7

D9

G_B

22nF

C18

R15

R2110k

2

CMOSH-3

C21

82p

C22

82p

JP1

2

J3

SYNC

SC4808

LUVLOSYNC

VCC

1016789

C23

0.1u,25V

C24

0.1u

1 4

3
5

SC1301A

U3

CMOSH-3

D14

D15

Q2

FMMT718

C2510nF

PE-68386

R19

0

0

CMOSH-3

D13

CMOSH-3

D12

R24

1k

REF

C28

NA

8

7

6

5

MOCD207

A

C

100

D16

1N5819HW

2

Vref

SC4431

R30

15k

4

R29

R26

2.2k

C32

0.1u

C33

22n

5

1

1nF

C30

4

U5

C29100pF

R27

15k

R28

25.5k

R25

11.5k

C31

470pF

3

Sync Drive Supply

2

U6

1

2

R20

2.2k

C26

0.1u

C27

22n

5

Sync Drive Supply

1

Vref

4

U4

SC4431

R23

18.2k

R22

37.4k

C34

.1uF

GRM32DR61C106KA01

G_B

G_A

VCC

GRM32DR61C106KA01

10u,16V

C16

1 2

LQH43MN102K011

R11

TBD

.1u,16V

C15

10u,16V

D5

2.2

R9

2.2

D6

L2

1 2

5output_half_brick

24 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Evaluation Board Bill of Materials

SC4808 Push Pull 3.3V 50W non Synchronous
SC4808EVB__non_sync Revision: 1.1

Bill Of Materials October 7,2002 13:35:18

1 1 CON1 5output_half_brick CON\5OUTPUT_HALF_BRICK
2 1 CON2 3input_half_brick CON\3INPUT_HALF_BRICK
3 2 C3,C1 2.2n SM/C_1206
4 6 C2,C10,C17,C24,C26,C32 0.1u SM/C_0805
5 6 C4,C5,C6,C7,C8,C9 22u,6.3V GRM32DR60J226KA01 SM/C_1210_GRM
6 3 C11,C12,C13 1u,100V GRM55DR72E105KW01 SM/C_2220
7 1 C14 .1u,16V SM/C_0805
8 2 C15,C16 10u,16V GRM32DR61C106KA01 SM/C_1210_GRM

9 1 C18 22nF SM/C_1206
10 1 C19 2.2u,16V SM/C_1206
11 1 C20 1u,16V GRM32RR71H105KA011 SM/C_1210_GRM
12 2 C22,C21 82p SM/C_0805
13 1 C23 0.1u,25V SM/C_1206
14 1 C25 10nF SM/C_0805
15 2 C27,C33 22n SM/C_0805
16 1 C28 NA SM/C_0805
17 1 C29 100pF SM/C_0805
18 1 C30 1nF SM/C_0805
19 1 C31 470pF SM/C_0805
20 1 C34 .1uF SM/C_0805
21 1 C35 2.2uF 16V SM/C_0805
22 2 D2,D1 MBRB2535CTL DIODE_D2PAK
23 4 D3,D5,D6,D16 1N5819HW SOD123
24 1 D4 ZM4743A SMB/DO214
25 8 D7,D9,D10,D11,D12,D13, CMOSH-3 CMOSH-3 (Central Semiconductor) SOD523

D14,D15
26 1 D8 LS4448 SM/DO213AC
27 1 JP1 short VIA\2P
28 1 J1 REF ED5052
29 1 J2 Vcc ED5052
30 1 J3 SYNC ED5052
31 1 L1 0.9uH PG0006
32 1 L2 LQH43MN102K011 LQH43MN102K01L SDIP0302
33 2 M1,M2 SUD19N20-90 SUD19N20-90 DPAKFET
34 1 Q1 FZT853 SM/SOT223_BCEC
35 1 Q2 FMMT718
36 4 R1,R7,R15,R19 0 SM/R_0805
37 2 R5,R2 10 SM/R_1206
38 1 R3 20k SM/R_1206
39 1 R4 250 SM/R_1210_MCR
40 2 R6,R11 TBD SM/R_0805
41 1 R8 0 SM/R_1206
42 2 R9,R10 2.2 SM/R_0805
43 1 R12 56.2k SM/R_1206
44 1 R13 10k SM/R_0805
45 1 R14 15 SM/R_0805
46 2 R16,R24 1k SM/R_0805
47 3 R17,R27,R30 15k SM/R_0805
48 1 R18 10 SM/R_0805
49 2 R26,R20 2.2k SM/R_0805
50 1 R21 10k SM/R_1206
51 1 R22 37.4k SM/R_0805
52 1 R23 18.2k SM/R_0805
53 1 R25 11.5k SM/R_0805
54 1 R28 25.5k SM/R_0805
55 1 R29 100 SM/R_0805
56 1 R31 16.2 SM/R_1206
57 1 R32 56.2k SM/R_0805
58 1 T1 PA0500 PA0500
59 1 T2 P8208T P8208T
60 1 T3 PE-68386 PE-68386
61 1 U1 SC4808 MSOP10
62 2 U2,U3 SC1301A SOT23_5PIN
63 2 U4,U5 SC4431 SOT23_5PIN
64 1 U6 MOCD207 SO-8
65 1 U7 CBRHD-02 CBRHD-02

SC4808B-1

Manufacturer # Foot PrintItem Quantity Reference Part

25 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Evaluation Board Gerber Plots

SC4808B-1

Board Layout Assembly Top

Board Layout Assembly Bottom

Board Layout Top

Board Layout Bottom

26 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Evaluation Board Gerber Plots

SC4808B-1

Board Layout INNER1 Board Layout INNER2

27 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Outline Drawing - MSOP-10

SC4808B-1

e

A

N

2X

E/2

PIN 1

INDICATOR

ccc

C

2X N/2 TIPS

aaa C

SEATING
PLANE

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

1.

DATUMS AND TO BE DETERMINED AT DATUM PLANE

2. -A- -H-

DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

3.
OR GATE BURRS.

REFERENCE JEDEC STD MO-187, VARIATION BA.4.

12

B

D

C

bxN

bbb C A-B D

SIDE VIEW

-B-

A1

E1

A2

D

E

A

SEE DETAIL

DIM

aaa
bbb

GAGE

PLANE

0.25

A

DIMENSIONS

INCHES

MIN NOM MAX MIN MAX

--­A1
A2

E1

L1

01

ccc

A

b
c

D

E

e
L

N

.000
.030
.007
.003
.114
.114

.016

0°

.118

.118
.193 BSC
.020 BSC

.024

(.037)

10

.004

.003

.010

H

-

-

-

-

.043
.006
.037 0.75
.011 0.17
.009
.122
.122

.032

8° 0°

DETAIL

MILLIMETERS

-

0.00

0.08

2.90

2.90

4.90 BSC

0.50 BSC

0.40

(L1)

A

NOM

3.00

3.00

0.60
(.95)

10

0.10

0.08

0.25

L

-

1.10

-

0.15

-

0.95

-

0.27

-

0.23

3.10

3.10

0.80

-

8°

c

01

Land Pattern - MSOP-10

NOTES:

Contact Information

X

DIMENSIONS

DIM INCHES

(C)

P

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.

G

Z

Y

C
G
P
X
Y
Z

(.161)

.098
.020
.011
.063
.224

Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012

Phone: [phone] FAX [phone]

MILLIMETERS

(4.10)

2.50

0.50

0.30

1.60

5.70

28 2006 Semtech Corp. www.semtech.com