Semtech SC471, SC471A Datasheet

Synchronous Buck Controller with

NOT RECOMMENDED FOR NEW DESIGN

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FOR NEW DESIGN

Multi-Level VOUT Transition Support

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Description Features

SC471/SC471A

The SC471/A is a versatile, constant on-time synchronous
buck, pseudo-fi xed-frequency, PWM controller intended for
notebook computers and other battery operated portable
devices. The SC471/A contains all the features needed to
provide cost-effective control of system elements needing
voltage slewing. Two integrated switches provide four
resistor-programmable DC output voltages, controlled by
the G0 and G1 inputs.

The output voltage is adjustable from 0.75V to 5V.
Additional features for each output include cycle-by-cycle
current limit, voltage soft-start, under-voltage protection,
programmable over-current protection, soft shutdown,
automatic power save and non-overlapping gate drive.
The SC471/A provides an enable input and a power good
output which is automatically blanked during output
voltage transitions.

The constant on-time topology provides fast dynamic
response. The excellent transient response means that
SC471/A based solutions require less output capacitance
than competing fi xed-frequency converters. Switching
frequency is constant until a step in load or line voltage
occurs, at which time the pulse density and frequency
will increase or decrease to counter the change in
output voltage. After the transient event, the controller
frequency returns to steady state operation. At light loads,
the automatic power save mode reduces the SC471/A
frequency for improved effi ciency.

 V

Programmable 0.75V to 5.25V with Integrated

OUT

Transition Support

 V
 Soft Shutoff at Output
 Current Sense Using Low-side R

Range 3V to 25V

BAT

or Resistor

DS(ON)

Sensing

 Adjustable Cycle-by-Cycle Valley Current Limit
 325kHz Fixed-Frequency
 Constant On-Time for Fast Dynamic Response and

Reduced Output Capacitance

 Automatic Smart Power Save
 Internal Soft-Start
 Over-Voltage/Under-Voltage Fault Protection
 Power Good Output with Transition Blanking
 1μA Typical Shutdown Current
 500μA Typical Operating Current
 Tiny 3×3mm, 16 Pin MLPQ Package
 Low External Part Count
 Industrial Temperature Range
 0.85% Internal Reference
 1A/3A Non-Overlapping Gate Drive with

†

SmartDriver™ Technology

 High Effi ciency > 90%
 This Product is Fully WEEE and RoHS Compliant

†

Patent Pending

Applications

 Notebook/Sub-Notebook Graphics Voltage

Controllers

 Tablet PCs
 Embedded Applications

Mar 19, 2008

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Typical Application Circuit

VCC

C4

SC471/SC471A

G1

VBAT

VOUT

C1

C3

L1

Q1

Q2

D1

R5

13

14

15

LX

BST

VCC

DL

T

16

G1

DH

U1

SC471/A

GND

RTN

5

6

G0

ILIM

EN

PGOOD

VOUT

FB

D17D0

8

R2 R3

C2

1

2

VCC

R1 R4

3

4

12

11

10

9

G0

EN

PGOOD

VOUT

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SC471/SC471A

NOT RECOMMENDED FOR NEW DESIGN

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FOR NEW DESIGN

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Absolute Maximum Rating

Exceeding the specifi cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the
Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.

Parameter Symbol Min Max Units

DH, BST to GND (DC)
DH, BST to GND (transient - 100nsec max)

DL to GND (DC)
DL to GND (transient - 100nsec max)

LX to GND (DC)

LX to GND (transient - 100nsec max)

BST to LX -0.3 +6.0 V

RTN to GND -0.3 +0.3 V

VCC to RTN -0.3 +6.0 V

D0, D1, EN, FB, G0, G1, ILIM, PGOOD, VOUT to RTN -0.3 VCC + 0.3 V

Operating Junction Temperature Range T

Storage Temperature Range T

Thermal Resistance, Junction to Ambient

Peak IR Refl ow Temperature, (10-40sec) T

ESD Rating (Human Body Model) 2

Note:

1) Calculated from package in still air, mounted 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

(1)

θ

J

STG

JA

PKG

-0.3

-2.0

-0.3

-2.0

-0.3

-2.0

-40 +125

-65 +150

45

+30
+33

+6.0
+6.0

+25
+28

+260

o

C/Watt

V

V

V

o

C

o

C

o

C

kV

Electrical Characteristics

Test Conditions: V

Parameter Conditions

Input Supplies

VBAT Input Voltage 3.0 25 V

VCC Input Voltage 4.5 5.5 V

VCC Shutdown Current EN = 0V

VCC Operating Current FB > 0.8V 500

Controller

FB On-Time Threshold

Output Voltage Adjust Range

D0/D1 Pull-Down Resistance

= 15V, V

BAT

= 1.5V, TA = 25 oC, 0.1% resistor dividers; VCC = 5.0V.

OUT

0 to 85°C

-40 to 85°C 0.7425 0.7575

(1)

D0/D1 to RTN;

SC471 G0/G1 = 5V; SC471A G0/G1 = 0V

25°C -40° to 85°C

Min Typ Max Min Max

1

0.75

15 40 Ω

0.7436 0.7564

0.75 5.25 V

5 μA

1000 μA

Units

V

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SC471/SC471A

NOT RECOMMENDED FOR NEW DESIGN

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Electrical Characteristics (continued)

25°C -40° to 85°C

Parameter Conditions

Min Typ Max Min Max

Regulation

Line Regulation Error Typical Application Circuit 0.04 %/V

Load Regulation Error Typical Application Circuit 0.3 %

Timing

On-Time VOUT = 1.1V 250 225 275 ns

Minimum On-Time 100 ns

Minimum Off-Time 350 ns

Units

Maximum Duty Cycle V

Soft-Start

Soft-Start Time I

Analog Inputs/Outputs

VOUT Input Resistance 500 kΩ

FB Input Bias Current -1 +1 μA

Current Sense

Zero Crossing
Detector Threshold

Power Good

Power Good Threshold 1% Hysteresis Typical -20% -17% -23% V

Threshold Delay Time

Voltage Transition Blank Time

Leakage 1 μA

(1)

(1)

BAT

= V

+ 0.2 FB < 0.7V 85 80 %

OUT

= I

OUT

LX - GND 0 -7 +7 mV

G0 or G1 Transition 32 clks

/2 1000 μs

LIM

5 μs

Fault Protection

ILIM Source Current 10 9 11 μA

ILIM Comparator Offset 0 -10 +10 mV

Current Limit (Negative) LX - GND 80 60 100 mV

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SC471/SC471A

NOT RECOMMENDED FOR NEW DESIGN

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Electrical Characteristics (continued)

25°C -40° to 85°C

Parameter Conditions

Min Typ Max Min Max

Fault Protection (continued)

Output Under-Voltage Fault FB with Respect to Nominal -30 -35 -25 %

Units

Steady-State
Over-Voltage Fault

Steady-State
Over-Voltage Fault Delay

G0/G1 Transition
Over-Voltage Fault

Smart Power Save Threshold FB with Respect to Nominal +8 %

Over-Temperature Shutdown

Logic Inputs/Outputs

Logic Input High Voltage EN, G0, G1 1.2 V

Logic Input Low Voltage EN, G0, G1 0.4 V

EN Input Bias Current EN = 5V -1 +1 μA

G0, G1 Input Bias Current G0, G1 = 5V 5 0 10 μA

Power Good Output
Low Voltage

Gate Drivers

FB with Respect to Nominal +20 +17 +23 %

FB Forced 50mV Above

Over-Voltage Fault Threshold

FB with Respect to Nominal;

valid for 32 cycles after G0/G1

Transition

(1)

Latching, >10°C Hysteresis 160 °C

R

= 10kΩ to VCC 0.4 V

PWRGD

5 μs

+50 %

Shoot-Through
Protection Delay

DL Pull-Down Resistance 0.8 1.6 Ω

DL Sink Current VDL = 2.5V 3.1 A

DL Pull-Up Resistance 2 4 Ω

DL Source Current VDL = 2.5V 1.3 A

DH Pull-Down Resistance BST - LX = 5V 2 4 Ω

DH Pull-Up Resistance

DH Sink/Source Current VDH = 2.5V 1.3 A

Notes:

1) Guaranteed by design.

2) Semtech’s SmartDriver™ FET drive fi rst pulls DH high with a pull-up resistance of 10Ω (typical) until LX = 1.5V (typical). At this point, an ad-
ditional pull-up device is activated, reducing the resistance to 2Ω (typical). This negates the need for an external gate or boost resistor.

© 2008 Semtech Corp.

(1)

(2)

DH or DL Rising 30 ns

BST - LX = 5V 2 4 Ω

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Pin Confi guration Ordering Information

SC471/SC471A

LX

BST

VCC

DL

G0

G1

DH

16 15 14

1

TOP VIEW

2

3

4

5678

GND

MLPQ16: 3X3 16 LEAD

T

RTN

13

D1

ILIM

D0

12

11

10

9

EN

PGOOD

VOUT

FB

Device Package

SC471MLTRT

SC471AMLTRT

SC471EVB Evaluation Board

SC471AEVB Evaluation Board

Notes:

1) Available in tape and reel packaging only. A reel contains 3000
devices.

2) Available in lead-free packaging only. This product is fully WEEE,
RoHS and J-TD-020B compliant. This component and all homog­enous subcomponents are RoHS compliant.

(1)

(1)

MLPQ-16 3X3

MLPQ-16 3X3

(2)

Marking Information

471

yyww

xxxx

Marking for the 3x3mm MLPQ 16 Lead Package
nnn = Part Number (Example: 471)
yyww = Date Code (Example: E652)
xxxx = Semtech Lot No. (Example: E901)

471A

yyww

xxxx

Marking for the 3x3mm MLPQ 16 Lead Package
nnn = Part Number (Example: 471A)
yyww = Date Code (Example: E652)
xxxx = Semtech Lot No. (Example: E901)

© 2008 Semtech Corp.

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Pin Descriptions

Pin Pin Name Pin Function

1 LX Switching (phase) node.

2 BST Boost capacitor connection for high-side gate drive.

3 VCC 5V power input for the internal circuits and gate drive outputs.

4 DL Gate drive output for the low-side external MOSFET.

SC471/SC471A

5 GND

6RTN

7 D1 Drain of second internal MOSFET which is controlled by G1.

8 D0 Drain of fi rst internal MOSFET which is controlled by G0.

9FB

10 VOUT Output voltage sense point for determining On-Time.

11 PGOOD

12 EN Enable input - connect EN to RTN to disable the SC471/A.

13 ILIM

14 G0

Power ground. This is the return point for the DL driver output, and the reference point for the
ILIM and zero cross circuits.

Return or analog ground for the FB input and FB resistor divider . Connect to GND directly at the
IC. All feedback components should connect to this ground.

Feedback sense point. The FB threshold is 0.75V; the resistor divider ratio between VOUT and
FB sets the output voltage. This ratio can be modifi ed using the G0/G1 inputs to switch resistors
in/out at D0/D1.

Open-drain power good indicator - a high impedance indicates power is good - an external pull-up
resistor is required.

Current limit sense point — to program the current limit connect a resistor from ILIM to
LX or to a current sense resistor.

Control input for the D0 MOSFET. A logic high (low) energizes the D0 MOSFET on the SC471
(SC471A), pulling D0 to ground.

15 G1

16 DH Gate drive output for the high-side external MOSFET.

TPAD

© 2008 Semtech Corp.

Control input for the D1 MOSFET. A logic high (low) energizes the D1 MOSFET on the SC471
(SC471A), pulling D1 to ground.

Mounting pad. Not connected internally - connect to system (power) ground plane through prefer­ably one large via or multiple smaller vias.

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Block Diagram

VBAT

VOUT

DH

LX

DL

DRV

DRV

+5V

BST

ILIM

Valley
I-Limit

QS

QB R

TON

Predictor

SC471/SC471A

+5V

VCC

UVLO

0.75V REF

RTN

VOUT

FB

D1

D0

Note: Shown is SC471; GO and G1 are inverted on SC471A.

G0

G1

Control

and Status

EN

+5V

PGD

Power

Good

PAD

GND

© 2008 Semtech Corp.

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NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

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Applications Information

SC471/A Synchronous Buck Controller

The SC471/A is a synchronous power supply controller
which simplifi es the task of designing a multi-level power
supply suitable for controlling video chip sets and other
multi-voltage circuits. The SC471/A provides two inputs
(G0/G1) which control internal pull-down transistors used
to select up to four adjustable output voltages.

Battery and +5V Bias Supplies

The SC471/A requires an external +5V bias supply in
addition to the VBAT supply. If stand-alone capability is
required, the +5V bias supply can be generated with an
external linear regulator.

Pseudo-Fixed-Frequency Constant On-Time
PWM Controller

The PWM control method is a constant-on-time, pseudo­fi xed-frequency PWM controller, see Figure 1. The ripple
voltage seen across the output capacitor’s ESR provides
the PWM ramp signal, eliminating the need for a current
sense resistor. The on-time is determined by an internal
one-shot whose period is proportional to output voltage,
and inversely proportional to input voltage. A separate
one-shot sets the minimum off-time (typically 350ns).

C

IN

L

TON

V

+

Figure 1

FB

ESR

C

OUT

V

LX

FB Threshold

0.75V

V

OUT

R1

FB

R2

Q1

Q2

VBAT

V

LX

SC471/SC471A

On-Time One-Shot (T

The internal on-time one-shot comparator has two inputs.
One input senses output voltage via the VOUT pin, while
the other input samples VBAT via the LX pin and creates
a proportional current which charges an internal capaci­tor. The TON time is the time required for this capacitor
to charge from zero volts to VOUT, thereby making TON
directly proportional to output voltage and inversely pro­portional to input voltage. This implementation results in
a fairly constant switching frequency without the need of
a clock generator. The internal frequency is optimized for
325kHz.

The general equation for the on-time is:

TON (nsec) = 2560 • (V
FREQ

(kHz) = 10

NOM

Immediately after the DH on-time, the DL output drives high
to energize the low-side MOSFET. DL has a minimum high
time of typically 350nsec, after which DL will continue to
stay high until one of the following occur:

FB drops to the 0.75V reference

•
The Zero Cross detector trips if power save is active

•
The Negative Current Limit detector trips

•

The Zero Cross detector monitors the voltage across the
low-side MOSFET and trips when it reaches zero. If this oc­curs on eight consecutive cycles, then DL will subsequently
shut off when the Zero Cross detector trips. See the PSAVE
Operation section. Both MOSFETS will then stay off until
FB drops to 0.75V, which will begin the next DH on-time.
This is normal operation at light load.

The Negative Current Limit detector trips when the drain
voltage at the low-side MOSFET reaches typically +80mV,
indicating a large negative current is being drawn through
the inductor from VOUT. When this occurs, DL drives low.
Both MOSFETS will then stay off until FB drops to 0.75V,
which will begin the next DH on-time. Tripping the Negative
Current detector is rare.

If DL drives low because FB has dropped to the 0.75V refer­ence, then another DH on-time is started: this is normal
operation at heavy load. If DL drives low because of the

ON)

OUT/VBAT) + 35

6

• VOUT/(2560 • VOUT + 35 • VBAT)

© 2008 Semtech Corp.

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Applications Information (continued)

Zero Cross detector, then both DH and DL will remain low
until FB drops to the 0.75V reference, at which point the
next DH on-time will begin. This is normal operation at
light load.

The typical operating frequency is 325kHz. It is possible to
raise the frequency by placing a resistor divider between
the output and the VOUT pin, see Figure 2. This reduces
the voltage at the VOUT pin which is used to generate the
on-time according to the previous equation. Note that
this places a small minimum load on the output. The new
frequency is approximated by the following equation:

FREQ (kHz) = FREQ

• (1 + R1/R2)

NOM

VCC

V

LX

L

ESR

C

OUT

+

Figure 3

SC471/SC471A

Power Output

R1 R2

1nF

V

OUT

pin 10

(VOUT)

V

LX

L

ESR

C

OUT

+

R2

Power Output

V

R1

pin 10

(VOUT)

1nF

OUT

Figure 2

It is also possible to lower the frequency using a resistive
divider to the 5V bias supply, see Figure 3. This raises
the voltage at the VOUT pin which will increase the on­time. Note that this results in a small leakage path from
the 5V supply to the output voltage. The resistor values
should be large to prevent the output voltage from drifting
up during shutdown conditions.

Note: the feedback resistors act as a dummy load to limit how
far the output can rise.

The new operating frequency is approximated by the
equation:

FREQ (kHz) = FREQ

•(R1 + R2) / (R1 + R2•VCC/VOUT)

NOM

VOUT Voltage Selection

Output voltage is regulated by comparing VOUT as seen
through a resistor divider to the internal 0.75V reference,
see Figure 1. With D0/D1 in the open state, the output
voltage is its lowest value and is set by the equation:

V

OUT = 0.75 • (1 + R1/R2)

Voltage Transition Control

The SC471/A provides G0/G1 control inputs to allow for the
selection of up to four output voltages. The output voltage
is regulated by comparing the FB pin (connected to VOUT via
an external resistor divider) to the internal 0.75V reference.
The G0/G1 inputs control the gates of internal MOSFETS,
and the sources are connected to D0/D1. Using G0/G1,
the user controls whether D0/D1 are grounded or open,
which then controls the resistor divider ratio for VOUT. The
SC471 uses active high logic for the G0/G1 inputs: a high
signal on G0/G1 will tie D0/D1 to ground. The SC471A
uses active low logic for the G0/G1inputs: a low signal on
G0/G1 will tie D0/D1 to ground.

When either the G0 or G1 input changes state, this change
quickly causes three actions:

The corresponding control output (D0 or D1) also

1.
changes state.
The power good PGD output is temporarily latched

2.
into its present state. This prevents chattering or
false tripping while VOUT moves to the new level.

© 2008 Semtech Corp.

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Applications Information (continued)

The output over-voltage OVP point is raised to 50%

3. Voltage Transitioning
above nominal, or 1.125V at FB. When going from
a higher to lower voltage, the G0/G1 change causes
rapid change of D0/D1, which in turns cause a rapid
change at FB. The temporary increase in OVP allows
the output to slew down to the new level without
tripping the OVP function.

VOUT Voltage Selection

VOUT voltage is regulated through the FB pin via resistors
R1 through R4 as shown in Figure 4.

R1

R2

V

OUT

+

G1
G0

FB

0.75V

TON

Logic

Control

R4

D1 D0

SC471/A

R3

Figure 4

The G0/G1 pins allow VOUT to transition to both higher
and lower values. The two directions have differing
responses.

When doing a down transition, the D0/D1 change will
cause FB to go above the 0.75V threshold. Depending on
the level of VOUT change and the load, the IC responds in
different ways. At light load conditions when power-save
is active, and when the downward change is 8% or greater,
the rapid change of D0/D1 is large enough to cause FB
to rise up to the Smart Power Save threshold (810mV).
DL will drive high to turn on the low-side MOSFET and
draw current from the output capacitor via the inductor.
DL will remain on until FB falls to 0.75V, at which point
a normal DH switching cycle begins, see Figure 5. This
causes the output to transition to the new voltage level
quickly, typically 10~20 usec. Refer to the Smart Power

Save Protection section for a full description.

A rapid downward change in VOUT also occurs for downward
changes less than 8%, provided the load is high enough
such that power-save is not active. In this case, after D0
opens and FB rises above the 0.75V trip point, DL will drive
high and stay high until FB drops to the trip point.

SC471/SC471A

The following table shows the equations that set VOUT as
a function of control inputs G0/G1:

D0/D1

SC471 SC471A

VOUT Equation

G1 G0 G1 G0

0.75 • (1 + R1/R2) 0011

0.75 • (1 + R1/R2 + R1/R3) 0110

0.75 • (1 + R1/R2 + R1/R4) 1001

0.75 • (1 + R1/R2 + R1/R3 + R1/R4) 1100

Note: the RDSON of the internal D0/D1 mosfets is in series
with R3/R4, which adds typically 15 ohms in series.

VOUT

© 2008 Semtech Corp.

11

D0/D1

FB

DL

DL

R3/R4

R1

R2

RTN

(Smart Psave threshold)

Figure 5

V

OUT

(FB threshold)

FB

810mV

750mV

Initial VOUT

Final VOUT

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Applications Information (continued)

SC471/SC471A

For the case where the down transition is less than
8%, and the load is light such that power-save is active,
the Smart Power Save detector will not activate. In this
case, with FB already above the 0.75V reference there
is no switching activity. DL and DH will remain off, and
the output voltage will slowly fall as the output capacitors
discharge into the load, see Figure 6.

Note: at light loads it can take many msec for the output to fall
to the new value. This should have no adverse effect. Many
loads such as graphics chipsets can have a minimum load of
several hundred mA, which will naturally pull VOUT down to the

next level.

V

OUT

R1

R3/R4

D0/D1

R2

FB

When doing an up transition (from lower to higher VOUT),
the G0/G1 change will affect D0/D1 and cause FB to drop
below the 0.75V internal reference. This quickly trips the
FB comparator regardless of whether psave is active or
not, generating a DH on-time and a subsequent DL high
time. At the end of the minimum off-time (350nsec), if FB
is still below 0.75V then another DH on-time is started,
Figure 7. This continues until FB reaches the normal
operating point.

V

OUT

R1

R3/R4

D0/D1

R2

D0/D1

RTN

FB

D0/D1

FB

VOUT

RTN

COUT Discharge due to load

(Smart Psave threshold)

< 810mV

(FB threshold)

Initial

VOUT

Final

VOUT

FB

DH

DL

VOUT

If the VOUT change is signifi cant, there can be several

Figure 6

consecutive cycles of DH on-time followed by minimum DL
time. This can cause a rapid increase in inductor current:

The time needed to reach the fi nal voltage is found from
the following equation, where COUT is in μF, and LOAD is
in Amps:

typically it only takes a few switching cycles for the induc­tor current to rise up to the Current Limit. At some point
the FB voltage will rise up to the 0.75V reference and the
DH pulses will cease, but the inductor’s LI

Time (μsec) = C

Note: the preceding equation applies only to the condition
where the VOUT downward change is less that the 8% limit
for Smart Psave, and also the load is light such that Psave is

active.

© 2008 Semtech Corp.

OUT • (VINITIAL – VFINAL)/LOAD

then fl ow into the output cap. This can create a signifi cant
overshoot as shown in Figure 8.

12

Figure 7

750mV

(FB threshold)

Final

VOUT

Initial

VOUT

2

energy must

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Applications Information (continued)

V

OUT

SC471/SC471A

V

OUT

R3/R4

D0/D1

D0/D1

FB

DH

DL

Voltage overshoot

VOUT

RTN

R1

R2

FB

750mV

(FB threshold)

Final

VOUT

Initial

VOUT

D0/D1

R3/R4

D0/D1

FB

DH

DL

VOUT

VS

CS

CS

R1

FB

RS

R2

RTN

750mV

(FB threshold)

Final

VOUT

Initial

VOUT

Figure 8

The overshoot can be approximated by the following
equation, where ICL is the current limit, V

is the desired

FINAL

setpoint for the fi nal voltage, L is in μH and COUT is in μF.

MAX = √( ICL

V

2

• L/COUT + VFINAL2 )

This overshoot can be eliminated by using a small RC
circuit to smooth the voltage seen at FB, see Figure 9.
The presence of Rs/Cs will prevent the rapid changes at
D0/D1 from moving FB too quickly. The result is a gradual
change from VOUT

INITIAL

to VOUT

, which prevents the

FINAL

build-up of high inductor current and reduces overshoot.

Note: Cs can be connected to either VOUT or GND. VOUT is
preferred because this results in higher ripple seen at the FB

pin, which improves stability.

Figure 9

Note: that Rs/Cs are part of the FB resistor divider and therefore
affect the output voltage sensing. To minimize the effect of

this, select Rs and Cs according to the following guidelines:

The total of Rs + R3/R4 should be chosen to give the
correct total resistance needed to adjust VOUT. Set RS
= R3/R4.

Cs should be chosen to give a time constant equal to
approximately 18μsec for 325 kHz operation. Note that
Cs is charging through a resistive network composed of
Rs/R1/R2/R3/R4. The effective resistance seen by Cs
is equal to the parallel combination of (R1 + Rs) and R3
or R4. For example, if the values for R1/R2/Rs/R3 are
10K/50K/18.7K/18.7K, then the effective resistance for
(10K + 18.7K) paralleled with 18.7K, which is 11.2K. To
set a time constant of 18μsec, CS should be approximately
18μsec/11.2k = 1600pF.

© 2008 Semtech Corp.

13

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Applications Information (continued)

SC471/SC471A

It is recommended for simplicity to add the RC smooth
to both D0 and D1 outputs. However, it is possible to
combine them into one RC combination as shown in
Figure 10.

V

OUT

D0

D1

R3

R4

CS

VS

RS

CS

R1

FB

R2

Figure 10

Note: the presence of Rs/Cs will affect the effective resistance
at the FB pin, and therefore modifi es the VOUT setpoints when
D0 or D1 are grounded. If Rs is used, the following table shows

the calculated values for VOUT.

SC471 SC471A

VOUT Equation

G1 G0 G1 G0

0.75 • (1 + R1/R2) 0011

0.75 • (1 + R1/R2 + R1/(R3+Rs)) 0110

crosses zero. To add hysteresis, the on-time is increased
by 25% in power save. The effi ciency improvement at light
loads more than offsets the disadvantage of slightly higher
output ripple. If the inductor current does not cross zero
on any switching cycle, the controller immediately exits
power save. Since the controller counts zero crossings,
the converter can sink current as long as the current does
not cross zero on eight consecutive cycles. This allows the
output voltage to recover quickly in response to negative
load steps, or to voltage transitions from a higher to a
lower voltage where the change exceeds 8%.

Smart Power Save Protection

In some applications, active loads on VOUT can leak
current from a higher voltage and thereby cause VOUT to
slowly rise and reach the OVP threshold, causing a hard
shutdown; the SC471/A uses Smart Power Save to prevent
this. When FB exceeds 8% above nominal (810mV), the
IC exits power save (if already active) and DL drives high to
turn on the low-side MOSFET, which starts to draw current
from VOUT via the inductor. When FB drops to the 0.75V
trip point, a normal TON switching cycle begins. This cycles
energy from VOUT back to VBAT and prevents a hard OVP
shutdown, and also minimizes operating power by avoiding
continuous conduction-mode operation. If a light load is
present, the switching continues for 8 consecutive clock
cycles and then the IC will re-enter power save to reduce
operating power.

0.75 • (1 + R1/R2 + R1/(R4+Rs)) 1001

Current Limit Circuit

Current limiting can be accomplished in two ways. The

0.75 • (1 + R1/R2 +
R1/(Rs+(R3*R4)/(R3+R4))

1100

RDSON of the lower MOSFET can be used as a current
sensing element, or a sense resistor at the lower MOSFET
source can be used if greater accuracy is needed. RDSON

Enable Input

The EN is used to disable or enable the SC471/A. When
EN is low (grounded), the SC471/A is off and in its lowest­power state. When EN is high the controller is enabled
and switching will begin.

sensing is more effi cient and less expensive. In both
cases, the R
The R

connects from the ILIM pin to either the lower

ILIM

MOSFET drain (for RDSON sensing) or the high side of the
current-sense resistor. R
source from the ILIM pin which turns on when the low-

PSAVE Operation

The SC471/A provides automatic power save operation at
light loads. The internal Zero-Cross comparator looks for
inductor current (via the voltage across the lower MOSFET)
to fall to zero on eight consecutive switching cycles. Once
observed, the controller enters power save and turns off
the low-side MOSFET on each cycle when the current

© 2008 Semtech Corp.

side MOSFET turns on, after the on-time DH pulse has
completed. If the voltage drop across the sense resistor
or low-side MOSFET exceeds the voltage across the R
resistor, current limit will activate. The high-side MOSFET
is held off until the voltage drop across the sense element
(resistor or MOSFET) falls below the voltage across the
R

resistor.

ILIM

14

resistor sets the over-current threshold.

ILIM

connects to a 10μA current

ILIM

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SC471/SC471A

This current sensing scheme actually regulates the
inductor valley current, (see Figure 11). This means that
if the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak ripple current,
and the average current through the inductor would be
10A plus 1/2 the peak-to-peak ripple current.

I

PEAK

I

LOAD

I

LIMIT

INDUCTOR CURRENT

TIME

Valley Current Limit

Figure 11

The RDSON sensing circuit is shown in Figure 12 with
RILIM = R1 and RDSON of Q2.

+5V

VBAT

R1

Q1

Q2

R4

VBAT

D2

+

C1

L1

Vout

+

C3

BST

DH

LX

ILIM

VDD

DL

GND

SC471/A

+5V

D1

C2

Figure 13

For resistor sensing, the current through the lower MOSFET
and the source sense resistor develops a voltage that
opposes the voltage developed across RILIM. When the
voltage developed across the RSENSE resistor reaches
voltage drop across RILIM, an over-current exists and the
high-side MOSFET will not be allowed to turn on.

The following over-current equation can be used for both
RDSON or resistive sensing. For RDSON sensing, the
MOSFET RDSON rating is used for the value of RSENSE.

D1

BST

DH

LX

ILIM

VDD

DL

GND

SC471/A

Q1

C2

R1

Q2

+

C1

L

VOUT

Power Good Output

D2

+

C3

The power good (PGD) output is an open-drain output
which requires a pull-up resistor. When the output
voltage as sensed at FB is -20% from the 0.75V reference
(600mV), PGD is pulled low. It is held low until the output
voltage returns above -20% of nominal. PGD is held low
during start-up and will not be allowed to transition high

Figure 12

until soft-start is completed when FB reaches 0.75V.
There is a 5μs delay built into the PGD circuit to prevent
false transitions.

The resistor sensing circuit is shown in Figure 13 with
RILIM = R1 and RSENSE = R4.

PGD also transitions low if the FB pin exceeds +20% of
nominal, which is also the over-voltage shutdown point.

© 2008 Semtech Corp.

15



IL x

OC

Aƫ10Valley

R

ILIM

R

SENSE

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SC471/SC471A

When G0 or G1 changes state, PGD is immediately
latched into its present state for 32 clock cycles while
VOUT and FB change to the new level, after which the
latch is disabled.

Output Over-Voltage Protection

In steady state operation, when FB exceeds 20% of
nominal (900mV), DL latches high and the low-side
MOSFET is turned on. DL stays high and the SMPS stays
off until the EN/PSV input is toggled or VCC is recycled.
There is a 5μs delay built into the OVP detector to prevent
false transitions. PGD is also held low after an OVP.

During G0/G1 transitions, the OVP threshold is temporarily
increased to 50% above nominal (1.125V), for 32 clock
cycles. This is for cases where the output voltage is
slewing from a higher to a lower voltage: the change in
G0/G1 affects the D0/D1 pins immediately, which in turn
affects the FB voltage immediately. The increase in OVP
from 20% to 50% is to prevent nuisance OVP tripping
caused by the immediate change at FB. It also protects
against the case of output overshoot for a lower to higher
VOUT transition.

Note: since the temporary OVP point is 50%, it is not possible
to change the output voltage down by more than 50% in one
step. To transition the output voltage more than 50% requires
at least two sequential step transitions to prevent OVP, or the

use of the RC smoothing circuit.

Output Under-Voltage Protection

When FB falls 30% below nominal (525mV) for eight
consecutive clock cycles, the output is shut off; the DL/
DH drives are pulled low to tristate the MOSFETS, and the
SMPS stays off until the Enable input is toggled or VCC is
recycled.

Soft-Start

The soft-start is accomplished by ramping the FB
comparator’s internal reference from zero to 0.75V in
30mV increments. Each 30mV step typically lasts for
eight clock cycles.

During the soft-start period, the Zero Cross Detector is
active to monitor the voltage across the lower MOSFET
while DL is high. If the inductor current reaches zero, the
FB comparator’s internal ramp reference is immediately
overridden to match the voltage at the FB pin. This soon
causes the FB comparator to trip which forces DL to turn
off and the next DH on-time will begin. This prevents the
inductor current from going too negative which would
cause droop in the VOUT startup waveform. The next
30mV step on the internal reference ramp occurs from the
new point at the FB pin. Since any of the internal 30mV
steps can be overridden by the FB waveform, the startup
time is therefore dependent upon operating conditions.
This override feature will stop when the FB pin reaches
approximately 600mV.

At start-up, during the fi rst 32 switching cycles, the over-
current threshold is reduced by 50%, to reduce overshoot
caused by the fi rst set of switching pulses.

MOSFET Gate Drivers

The DH and DL drivers are optimized for moderate, high­side, and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low­side MOSFET from turning on until DH is fully off.

Note: be sure there is low resistance and low inductance
between the DH and DL outputs to the gate of each MOSFET.

POR and UVLO

Under-voltage lockout circuitry (UVLO) inhibits switching
and tristates the DH/DL drivers until VCC rises above

4.4V. An internal power-on reset (POR) occurs when VCC

exceeds 4.4V, which resets the fault latch and the soft­start counter, to prepare the PWM for switching. At this
time the SC471/A will come out of UVLO and begin the
soft-start cycle.

© 2008 Semtech Corp.

Design Procedure

Prior to designing a switch mode supply, the input voltage,
load current, switching frequency and inductor ripple
current must be specifi ed.

For notebook systems the maximum input voltage (VIN
is determined by the highest AC adaptor voltage, and
the minimum input voltage (VIN
lowest battery voltage after accounting for voltage drops
due to connectors, fuses and battery selector switches.

16

) is determined by the

MIN

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MAX

)

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Applications Information (continued)

SC471/SC471A

In general, four parameters are needed to defi ne the
design:

1) Nominal output voltages (VOUT)

2) Static or DC output tolerance

3) Transient response

4) Maximum load current (IOUT)

There are two values of load current to consider: continuous
load current and peak load current. Continuous load
current is concerned with thermal stresses which drive
the selection of input capacitors, MOSFETs and diodes.
Peak load current determines instantaneous component
stresses and fi ltering requirements such as inductor
saturation, output capacitors and design of the current
limit circuit.

Design example:

VBAT = 10V min, 20V max
VOUT1 = 0.9V +/- 4%
VOUT2 = 1.05V +/-4%
VOUT3 = 1.1V +/-4%
VOUT4 = 1.15V+/-4%
Load = 20A maximum

Inductor Selection

Low inductor values result in smaller size but create
higher ripple current. Higher inductor values will reduce
the ripple current but are larger and more costly. Because
wire resistance varies widely for different inductors and
because magnetic core losses vary widely with operating
conditions, it is often diffi cult to choose which inductor
will optimize effi ciency. The general rule is that higher
inductor values have better effi ciency at light loads due
to lower core losses and lower peak currents, but at high
load the smaller inductors are better because of lower
resistance. The inductor selection is generally based on
the ripple current which is typically set between 20% to
50% of the maximum load current. Cost, size, output ripple
and effi ciency all play a part in the selection process.

The switching frequency is optimized for 325kHz. The
equation for on-time is:

TON (nsec) = 2560 • (VOUT/VBAT) + 35

During the DH on-time, voltage across the inductor is (VBAT

- VOUT). To determine the inductance, the ripple current
must be defi ned. Smaller ripple current will give smaller
output ripple and but will lead to larger inductors. The ripple
current will also set the boundary for PSAVE operation.
The switcher will typically enter PSAVE operation when the
load current decreases to 1/2 of the ripple current; (i.e.
if ripple current is 4A then PSAVE operation will typically
start for loads less than 2A. If ripple current is set at 40%
of maximum load current, then PSAVE will commence for
loads less than 20% of maximum current).

The equation for determining inductance is:

L = (VBAT - VOUT) • TON / IRIPPLE

Use the maximum value for VBAT, and for TON use the
value associated with maximum VBAT. For selecting the
inductor, we start with the highest VOUT setting and a
maximum ripple current of 5A.

TON = 182 nsec at 20VBAT, 1.15VOUT

L = (20 - 1.15) • 182 nsec / 5A = 0.69μH

We will select a slightly larger value of 0.7μH, which will
decrease the maximum IRIPPLE to 4.91A.

Note: the inductor must be rated for the maximum DC load
current plus 1/2 of the ripple current.

The minimum ripple current under is also checked .This
occurs when VBAT and VOUT are set to their minimum
values of 10V and 0.9V.

TONVBATMIN = 2560 • (0.9/10) + 35 = 265 nsec

IRIPPLE = (VBAT - VOUT) • TON / L
IRIPPLE_VBATMIN = (10 - 0.9) • 265 nsec / 0.7μH = 3.45A

Capacitor Selection

The output capacitors are chosen based on required ESR
and capacitance. The ESR requirement is driven by the
output ripple requirement and the DC tolerance. The
output voltage has a DC value that is equal to the valley
of the output ripple, plus 1/2 of the peak-to-peak ripple.
Change in the ripple voltage will lead to a change in DC
voltage at the output.

© 2008 Semtech Corp.

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Applications Information (continued)

SC471/SC471A

The design goal is +/-4% output regulation. The internal

0.75V reference tolerance is 1%, assuming 1% tolerance

for the FB resistor divider, this allows 2% tolerance due to
VOUT ripple. Since this 2% error comes from 1/2 of the
ripple voltage, the allowable ripple is 4%, or 46mV for a

1.15V output.

The maximum ripple current of 4.05A creates a ripple
voltage across the ESR. The maximum ESR value allowed
would create 46mV ripple:

ESRMAX = VRIPPLE/IRIPPLEMAX = 46mV / 4.91A

ESRMAX = 9.4 mΩ

The output capacitance is typically chosen based on
transient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, defi nes the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in a very small time), the
output capacitor must absorb all the inductor’s stored
energy. This will cause a peak voltage on the capacitor
according to the equation:

COUTMIN = L • (IOUT + 1/2 • IRIPPLEMAX)2 / (VPEAK2 - VOUT2)

With a peak voltage VPEAK of 1.230 (80mV rise above

1.15 upon load release), the required capacitance is:

COUTMIN = 0.7μH•(10 + 1/2•4.91)2/(1.242 - 1.152)

COUTMIN = 570μF

The above requirements (570μF, 9.4mΩ) will be met using
two capacitors, 330μF 6mΩ.

If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 0.75V reference, the DL
output is high and the low-side mosfet is on. During this
time, the voltage across the inductor is approximately

-VOUT. This causes a downslope or falling di/dt in the

inductor. If the load di/dt is not much faster than the
di/dt in the inductor, then the inductor current can track
change in load current, and there will be relatively less
overshoot from a load release.

The following can used to calculate the needed capacitance
for a given dILOAD/dt.

Peak inductor current,

ILPEAK = ILOADMAX + 1/2 • IRIPPLEMAX

ILPEAK = 10 + 1/2 • 4.91 = 12.45A

Rate of change of Load current = dILOAD/dt

IMAX = maximum DC load current = 10A

COUT = ILPEAK • (L •ILPEAK / VOUT - IMAX/dILOAD /dt)
2 • (VPEAK - VOUT)

Example: Load dI/dt = 2.5A/μsec

This would cause the output current to move from 10A to
zero in 4μsec.

COUT = 12.45•(0.7μH•12.45/1.15 - 10/(2.5/1μsec)
2 •(1.23 - 1.15)

COUT = 278 μF

Stability Considerations

Unstable operation shows up in two related but distinctly
different ways: double-pulsing and fast-feedback loop
instability. double-pulsing occurs due to switching noise
seen at the FB input or because the ESR is too low, causing
insuffi cient voltage ramp in the FB signal. This causes
the error amplifi er to trigger prematurely after the 350ns
minimum off-time has expired. double-pulsing will result
in higher ripple voltage at the output, but in most cases
is harmless. In some cases, however, double-pulsing can
indicate the presence of loop instability, which is caused
by insuffi cient ESR.

One simple way to solve this problem is to add some trace
resistance in the high current output path. A side effect
of doing this is output voltage droop with load. Another
way to eliminate doubling-pulsing is to add a small (e.g.
10pF) capacitor across the upper feedback resistor
divider network, (this capacitor is shown in Figure 14).
This capacitance should be left out until confi rmation that
double-pulsing exists. Adding this capacitance will add

© 2008 Semtech Corp.

18

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Applications Information (continued)

SC471/SC471A

a zero in the transfer function and should eliminate the
problem. It is best to leave a spot on the PCB in case it is
needed.

Dropout Performance

The VOUT adjust range for continuous-conduction
operation is limited by the fi xed 350nS (typical) minimum
Off-time One-shot. When working with low input voltages,
the duty-factor limit must be calculated using worst-case

G1
G0

FB

0.75V

Logic

Control

TON

R4

D1 D0

SC471/A

R3

R2

R1

OUT

C

V

+

values for on and off times.

The IC duty-factor limitation is given by:

DUTY = TON

Be sure to include inductor resistance and MOSFET on­state voltage drops when performing worst-case dropout
duty-factor calculations.

SC471/A System DC Accuracy (VOUT Controller)

Figure 14

Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the switching frequency variation with

Loop instability can cause oscillations at the output as a
response to line or load transients. These oscillations can
trip the over-voltage protection latch or cause the output

line and load, and the external resistor tolerance. The
error comparator offset is trimmed so that it trips when
the feedback pin is 0.75V, 1%.

voltage to fall below the tolerance limit.

The on-time pulse in the SC471/A is calculated to give

The best way for checking stability is to apply a zero-to­full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of
ringing after the initial step is a sign that the ESR should
be increased.

a pseudo-fi xed frequency of 325kHz. Nevertheless, some
frequency variation with line and load is expected. This
variation changes the output ripple voltage. Because
constant on-time converters regulate to the valley of
the output ripple, ½ of the output ripple appears as a
DC regulation error. For example, If the output ripple is

SC471/A ESR Requirements

The constant on-time control used in the SC471/A
regulates the valley of the output ripple voltage. This
signal consists of a term generated by the output ESR of
the capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging

50mV with VIN = 6 volts, then the measured DC output
will be 25mV above the comparator trip point. If the ripple
increases to 80mV with VIN = 25 volts, then the measured
DC output will be 40mV above the comparator trip. The
best way to minimize this effect is to minimize the output
ripple.

during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For
most applications the minimum ESR ripple voltage is
dominated by PCB layout and the properties of SP or
POSCAP type output capacitors. For applications using
ceramic output capacitors, the absolute minimum ESR
must be considered. If the ESR is low enough the ripple
voltage is dominated by the charging of the output
capacitor. This ripple voltage lags the on-time due to the
LC poles and can cause double pulsing if the phase delay

To compensate for valley regulation it is often desirable
to use passive droop. Take the feedback directly from the
output side of the inductor, placing a small amount of trace
resistance between the inductor and output capacitor.
This trace resistance should be optimized so that at full
load the output droops to near the lower regulation limit.
Passive droop minimizes the required output capacitance
because the voltage excursions due to load steps are
reduced.

exceeds the off-time of the converter. To prevent double
pulsing, the ripple voltage present at the FB pin should be
10-15mV minimum over the on-time interval.

The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required use 0.1% resistors.
The output inductor value may change with current. This

© 2008 Semtech Corp.

19

MIN/(TONMIN + TOFFMAX)

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Applications Information (continued)

SC471/SC471A

will change the output ripple and thus the DC output
voltage. The output ESR also affects the ripple and thus
the DC output voltage.

Switching Frequency Variations

The switching frequency will vary somewhat due to line
and load conditions. The line variations are a result
of a fi xed offset in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VBAT increases, these factors make the actual DH on-time
slightly longer than the idealized on-time. The net effect
is that frequency tends to fall slightly with increasing input
voltage.

The load variations are due to losses in the power train
from IR drop and switching losses. For a conventional
PWM constant-frequency topology, as load increases
the duty cycle also increases slightly to compensate for
IR and switching losses in the MOSFETs and inductor. A
constant on-time topology must also overcome the same
losses by increasing the duty cycle (more time is spent
drawing energy from VBAT as losses increase). Since the
on-time is constant for a given VOUT/VBAT combination,
the way to increase duty cycle is to gradually shorten
the off-time. The net effect is that switching frequency
increases slightly with increasing load.

Layout Guidelines

One or more ground planes are recommended to minimize
the effect of switching noise and copper losses and to
maximize heat removal. The analog ground reference,
RTN, should connect directly to the thermal pad, which
in turn connects to the ground plane through preferably
one large via. There should be a RTN plane or copper
are near the chip; all components that are referenced to
RTN should connect to this plane directly, not through the
ground plane, and located on the chip side of the PCB if
possible.

special attention given to avoiding indirect connections
between RTN and GND which will create ground loops.
As mentioned above, the RTN plane must be connected to
the GND plane at the chip near the RTN/GND pins.

The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses. Make all the power connections on
one side of the PCB using wide copper fi lled areas if
possible. Do not use “minimum” land patterns for power
components. Minimize trace lengths and maximize trace
widths between the gate drivers and the gates of the
MOSFETs to reduce parasitic impedances (and MOSFET
switching losses); the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive
signals. Use multiple vias as required by current handling
requirement (and to reduce parasitic) if routed on more
than one layer.

For an accurate ILIM current sense connection, connect
the ILIM trace to the current sense element (MOSFET or
resistor) directly at the pin of the element, and route that
trace over to the ILIM resistor on another layer if needed.

The layout can be generally considered in two parts; the
analog control section referenced to RTN, and the switcher
power section referenced to GND.

Looking at the control section fi rst, locate all components
referenced to RTN on the schematic and place these
components near the chip and on the same side if
possible. Connect RTN using a wide trace. Very little
current fl ows in the RTN path and therefore large areas
of copper are not needed. Connect the RTN pin directly to
the thermal pad under the device as the only connection
between RTN and GND.

GND should be a separate plane which is not used for
routing analog traces. The VCC input provides power to
the internal analog circuits and the upper and lower gate
drivers.

The VCC supply decoupling capacitor should be tied
between VCC and GND with short traces. All power GND
connections should connect directly to this plane with

© 2008 Semtech Corp.

The chip supply decoupling capacitor (VCC/GND) should
be located near to the pins. Since the DL pin is directly
between VCC and GND, and the DL trace must be a wide,
direct trace, the VCC decoupling capacitor is best placed
on the opposite side of the PCB, routed with traces as short
as possible and using at least two vias when connecting
through the PCB.

20

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Applications Information (continued)

SC471/SC471A

There are two sensitive, feedback-related pins at the chip:
VOUT and FB. Proper routing is needed to keep noise
away from these signals. All components connected to
FB should be located directly at the chip, and the copper
area of the FB node minimized. The VOUT trace that
feeds into the VOUT pin, which also feeds the FB resistor
divider, must be kept far away from noise sources such
as switching nodes, inductors and gate drives. Route the
VOUT trace in a quiet layer if possible, from the output
capacitor back to the chip.

For the switcher power section, there are a few key
guidelines to follow:

1) There should be a very small input loop between

the input capacitors, MOSFETs, inductor, and output
capacitors. Locate the input decoupling capacitors
directly at the MOSFETs.

2) The phase node should be a large copper pour, but still

compact since this is the noisiest node.

3) The power GND connection between the input

capacitors, low-side MOSFET, and output capacitors
should be as small as is practical, with wide traces or
planes.

4) The impedance of the power GND connection

between the low-side MOSFET and the GND pin should
be minimized. This connection must carry the DL drive
current, which has high peaks at both rising and falling
edges. Use mulitple layers and multiple vias to minimize
impedance, and keep the distance as short as practical.

Finally, connecting the control and switcher power sections
should be accomplished as follows:

1) Route the VOUT feedback trace in a “quiet” layer, away
from noise sources.

2) Route DL, DH and LX (low side FET gate drive, high side
FET gate drive and phase node) to the chip using wide
traces, with multiple vias if using more than one layer.
These connections are to be as short as possible for loop
minimization, with a length to width ratio less than 20:1
to minimize impedance. DL is the most critical gate drive,
with power GND as its return path. LX is the noisiest node
in the circuit, switching between VBAT and ground at high
frequencies, thus should be kept as short as practical. DH
has LX as its return path. DL, DH, LX, and BST are high­noise signals and should be kept well away from sensitive
signals, particularly FB and VOUT.

3) BST is also a noisy node and should be kept as short
as possible. The high-side DH driver is relies on the boost
capacitor to provide the DH drive current, so the boost
capacitor must be placed near the IC and connect to the
BST and LX pins using short, wide traces to minimize
impedance.

4) Connect the GND pin on the chip to the VCC decoupling
capacitor and then drop vias directly to the ground plane.

Locate the current limit resistor RLIM at the chip with a
kelvin connection to the drain of the lower MOSFET at the
phase node, and minimize the copper area of the ILIM
trace.

© 2008 Semtech Corp.

21

www.semtech.com

POWER MANAGEMENT

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

2400

2600

5101520

VBAT (V)

TON (nsec)

100

200

300

400

500

600

700

800

900

1000

5101520

VBAT (V)

TON (nsec)

1.07

1.08

1.09

1.10

1.11

1.12

1.13

0 2 4 6 8 101214161820

Load (A)

VOUT (V)

1.07

1.08

1.09

1.10

1.11

1.12

1.13

10 12 14 16 18

VBAT (V)

VOUT (V)

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Typical Characteristics

SC471/SC471A

TON vs. VBAT - VOUT > 2.5V

3.3V

2.5V

5V

Frequency vs. BAT

400

390

380

370

360

350

340

Frequency (kHz)

330

320

310

300

5 7 9 11 13 15 17 19 21 23

1.1V

1.0V

VBAT (V)

1.8V

0.9V

1.5V

1.25V

0.75V

TON vs. VBAT - VOUT < 1.8V

1.1V

0.75V

1.8V

1.5V

Effi ciency vs. Load - VOUT = 1.15V

95%

10V

90%

85%

Efficiency (%)

80%

75%

0 2 4 6 8 101214161820

15V

19V

Load (A)

© 2008 Semtech Corp.

10V

19V

15V

22

No Load

10A

Line RegulationLoad Regulation

3A

15A

www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Typical Characteristics (continued)

SC471/SC471A

Startup 1.15V 19VBAT No load

Load Transient Response 0A to 20A

Startup 1.15V 19VBAT 20A load

Load Transient Response 20A to 0A

© 2008 Semtech Corp.

23

www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Typical Characteristics (continued)

SC471/SC471A

VOUT Up Transition

VOUT = 0.9 to 1.15V, VBAT = 15V 1A Load

VOUT Down Transition

VOUT = 0.9 to 1.15V, VBAT = 15V 1A Load

VOUT Up Transition

VOUT = 0.9 to 1.15V, VBAT = 15V 15A Load

VOUT Down Transition

VOUT = 0.9 to 1.15V, VBAT = 15V 15A Load

© 2008 Semtech Corp.

24

www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Reference Design

SC471/SC471A

VOUT

C5*

+

VBAT

C1

10UF

C6*

+

330uF/6mohm

C7
1UF

0.7uH

C2

10UF

RJK0305DP

MBRS140L

C3

56789

10UF

D

Q1

123

L1

56789

D

D2

AC

123

4

C4

100NF

VCC

4

Q2

RJK0302DP

VCC

D1

BAT54A

R7 10K

LX

1

2

3

4

17

C8
1UF

EN

G0

G1

LX

BST

VCC

DL

PAD

GND

5

15DH16

G1

U1

SC471

RTN

6D17D08

VCC

R3

10K

ILIM

13G014

ILIM

12

EN

PGD

VOUT

FB

D1D1

PGD

11

VSNSVSNSVSNSVSNS

10

FB

9

R11 18.7K

R14 28.7K

R16

18.7K

PGD

C9

1500PF

C12
10nF

R8
10K

VOUT

C6

NO_POP

R12

49.9K

Reference Design — 0.90, 1.05, 1.1, 1.15V 20A

Bill of Materials

Component Value Manufacturer Part Number Web

C1, C2, C3 10uF, 25V Murata GRM32DR71E106KA12L www.murata.com

C5, C6 330uF/6mohm/2V Panasonic EEFSX0D331XR www.panasonic.com

L1 0.7uH, 24A NEC Tokin C-PI-1350-0R7S http://www.nec-tokin.com

Q1 10mohm/30V Renesas RJK0305DBP www.renesas.com

Q2 3.5mohm/30V Renesas RJK0302 www.renesas.com

D1 200mA/30V OnSemi BAT54C www.onsemi.com

D2 1A/40V OnSemi MBSR140LT3 www.onsemi.com

© 2008 Semtech Corp.

25

www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Outline Drawing - MLPQ-16 3 x 3

SC471/SC471A

PIN 1

INDICATOR

(LASER MARK)

A

aaa

C

NOTES:

1.

2.

3.

A

D

B

DIM

A
A1
A2

E

A2

SEATING
PLANE

A1

E1

2

1

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

DAP IS 1.90 x 1.90mm.

D1

e/2

N

e

D/2

C

LxN

E/2

bxN

bbb C A B

b .007.009.0120.180.230.30

D
D1

E
E1

e
L

N

aaa
bbb

DIMENSIONS

INCHES

MIN

NOM

-

.031

-

.000

-

(.008)

.114 .118 3.00.122 2.90 3.10
.06116.067

.118

.114

.003
.004 0.10

MILLIMETERS

.040

0.80

.002-0.00

-

.071 1.55

2.90

.122

1.55

.071.067.061

0.30.012 .020.016 0.40 0.50

-

-

(0.20)

3.00 3.10

1.70 1.80

0.50 BSC.020 BSC

16

0.08

MAXMINMAX NOM

1.00

0.05

-

1.801.70

© 2008 Semtech Corp.

26

www.semtech.com

POWER MANAGEMENT

H

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Land Pattern - MLPQ-16 3 x 3

SC471/SC471A

R

(C)

K

X

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.

THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD

2.
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.

Z

G

Y

DIMENSIONS

DIM

C
G
H
K .067 1.70
P
R
X
Y
Z

INCHES

(.114)

.083
.067

.020
.006 0.15
.012
.031
.146

MILLIMETERS

(2.90)

2.10

1.70

0.50

0.30

0.80

3.70

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: [phone] Fax: [phone]

www.semtech.com

© 2008 Semtech Corp.

27

www.semtech.com