Semtech SC411 Datasheet

Download

Page 1

POWER MANAGEMENT

SC411

Synchronous Buck Pseudo-Fixed

Frequency Power Supply Controller

Description

The SC411 is a constant on-time synchronous buck PWM controller in a space-saving MLPQ package intended for use in notebook computers and other battery operated portable devices. Features include high efﬁ ciency and a fast dynamic response with no minimum on-time. The excellent transient response means that SC411 based solutions will require less output capacitance than competing ﬁ xed frequency converters.

The switching frequency is constant until a step-in load or line voltage occurs. During this time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady-state operation. At light loads, Powersave Mode enables the SC411 to skip PWM pulses for better efﬁ ciency.

The output voltage can be adjusted from 0.5V to VCCA. A frequency setting resistor sets the on-time for the controller. The integrated gate drivers feature adaptive shoot-through protection and soft-switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and under-voltage protection, a Power Good output and soft discharge upon shutdown.

Features

 Constant on-time for fast dynamic response  Programmable VOUT range = 0.5 – VCCA  VBAT range = 1.8V – 25V  DC current sense using low-side RDS(ON)

Sensing or sense resistor

 Resistor programmable frequency  Cycle-by-cycle current limit  Digital soft-start  Powersave option  Over-voltage/under-voltage fault protection  10μA typical shutdown current  Low quiescent power dissipation  Power good indicator  1.2% reference  Integrated gate drivers with soft switching  Enable pin  16 pin MLPQ (4mm x 4mm)  Output soft discharge upon shutdown

Applications

 Notebook Computers  CPU/IO Supplies  Handheld Terminals and PDAs  LCD Monitors  Network Power Supplies

Typical Application Circuit

VBAT

RTON1

PGOOD

1nF

June 2007

VOUT

10R

5VSUS

1uF

VBAT5VSUS

C1 0.1uF

TON

VOUT

VCCA

PGD

NC5VSSA6PGND7DL

EN/PSV

SC411

TPAD

BST

ILIM

VDDP

1uF

10uF

VOUT

www.semtech.com1

Page 2

SC411

POWER MANAGEMENT

Absolute Maximum Ratings

Exceeding the speciﬁ cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters speciﬁ ed in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.

Parameter Symbol Maximum Units

(1)

TON to VSSA -0.3 to +25.0

DH, BST to PGND -0.3 to +30.0

LX to PGND -2.0 to +25.0

PGND to VSSA -0.3 to +0.3

BST to LX -0.3 to +6.0

DL, ILIM, VDDP to PGND

0.3 to +6.0

EN/PSV, FB, PGD, VCCA, VOUT to VSSA -0.3 to +6.0

VCCA to EN/PSV, FB, PGD, VOUT -0.3 to +6.0

(2)

Thermal Resistance Junction to Ambient

Operating Junction Temperature Range T

Storage Temperature Range

IR Reﬂ ow (Soldering) 10s to 30s T

Notes:

1) This device is ESD sensitive. Use of standard ESD handling precautions is required.

2) Calculated from package in still air, mounted to 3” to 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

(2)

STG

PKG

-40 to +125

-65 to +150 °C

260 °C

°C/W

°C

Electrical Characteristics

Test Conditions: V

Parameter Conditions

Input Supplies

VCCA 5.0 4.5 5.5 V

VDDP 5.0 4.5 5.5 V

VBAT Voltage Off-time > 800ns 1.8 25 V

VDDP Operating Current

VCCA Operating Current

= 15V, EN/PSV = 5V, VCCA = VDDP = 5V, V

BAT

FB > regulation point,

= 0A

LOAD

FB > regulation point,

= 0A

LOAD

=1.25V, R

OUT

= 1MΩ.

TON

25°C -40°C to 125°C

Min Typ Max Min Max

70 150 μA

700 1100 μA

Units

Page 3

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Parameter Conditions

Input Supplies (Cont.)

SC411

25°C -40°C to 125°C

Units

Min Typ Max Min Max

TON Operating Current R

Shutdown Current

Controller

VCCA = 4.5V to 5.5V Error Comparator Threshold (FB Turn-on Threshold)

Output Voltage Range 0.5 VCCA

On-Time, V

Minimum Off-Time 400 550 ns

VOUT Input Resistance 500 kΩ

VOUT Shutdown Discharge Resistance

= 2.5V

BAT

(1)

Includes variations of

internal x3 gain stage, com-

parator, and 1.5V REF

EN/PSV = GND 22

= 1M 15 μA

TON

EN/PSV = 0V -5 -10 μA

VCCA 5 10 μA

VDDP, TON 0 1 μA

0.500 -1.2% +1.2%

= 1MΩ 1761 1409 2113

TON

= 500kΩ 936 749 1123

TON

FB Input Bias Current -1.0 +1.0 μA

Over-Current Sensing

ILIM Source Current DL high 10 9 11 μA

Current Comparator Offset PGND - ILIM -10 10 mV

PSAVE

Zero-Crossing Threshold

Fault Protection

(PGND - LX), EN/PSV = 5V

5mV

Page 4

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Parameter Conditions

SC411

25°C -40°C to 125°C

Units

Min Typ Max Min Max

(PGND - LX), R

Current Limit (Positive)

Fault Protection (Cont.)

Current Limit (Negative) (PGND - LX) -125 -160 -90 mV

Output Under-Voltage Fault With respect to internal ref. -30 -40 -25 %

Output Over-Voltage Fault With respect to internal ref. +16 +12 +20 %

Over-Voltage Fault Delay

PGD Low Output Voltage Sink 1mA 0.4 V

PGD Leakage Current

PGD UV Threshold With respect to internal ref. -10 -12 -8 %

PGD Fault Delay

(2)

(PGND - LX), R

FB forced above

OV Threshold

FB in regulation,

PGD = 5V

FB forced outside

PGD window

= 5kΩ 50 35 65 mV

ILIM

= 10kΩ 100 80 120 mV

ILIM

= 20kΩ 200 170 230 mV

ILIM

5 μs

1 μA

5 μs

VCCA Under-Voltage Threshold

Over-Temperature Lockout 10°C Hysteresis 165 °C

Inputs/Outputs

Logic Input Low Voltage EN/PSV Low 1.2 V

Logic Input High Voltage

Logic Input High Voltage EN/PSV High 3.1 V

EN/PSV Input Resistance

Falling

(100mV Hysteresis)

EN High,

PSV Low (Floating)

R Pullup to VCCA 1.5

R Pulldown to VSSA 1.0

4.0 3.7 4.3 V

2.0 V

MΩ

Page 5

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Parameter Conditions

Soft-Start

SC411

25°C -40°C to 125°C

Units

Min Typ Max Min Max

Soft-Start Ramp Time EN/PSV High to PGD High 440 clks

Under-Voltage Blank Time EN/PSV High to UV High 440 clks

(3)

Gate Drivers

Shoot-Through Delay

(4)

DH or DL Rising 30 ns

DL Pull-Down Resistance DL Low 0.80 1.75 Ω

DL Sink Current DL = 2.5V 3.1 A

DL Pull-Up Resistance DL High 2 4 Ω

DL Source Current DL = 2.5V 1.3 A

Notes:

1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage.

2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests.

3) clks = Switching cycles.

4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 8.

5) Semtech’s SmartDriver pull-up device is activated, reducing the resistance to 2Ω (typ). This negates the need for an external gate or boost resistor.

FET drive ﬁ rst pulls DH high with a pull-up resistance of 10Ω (typ) until LX = 1.5V (typ). At this point, an additional

Page 6

POWER MANAGEMENT

Block Diagram

SC411

VCCA (2)

EN/PSV (15)

TON (16)

VOUT (1)

FB (3)

PGD (4)

VSSA (6)

DSCHG

POR / SS

TON

TOFF

1.5V REF

Error Comparator

FAULT

MONITOR

OFF

PWM

ZERO

CONTROL

LOGIC

ISENSE

BST (13)

DH (12)

LX (11)

ILIM (10)

VDDP (9)

DL (8)

PGND (7)

NC (5)

Note: the Error Comparator tolerances are approximately x3 gain stage = +/- 0.1% gain error comparator = +/- 3mV offset error

1.5V REF = +/- 1.0%

REF + 16%

REF - 10%

REF - 30%

NC (14)

Page 7

POWER MANAGEMENT

Pin Conﬁ guration Ordering Information

SC411

VOUT

VCCA

PGD

Pin Descriptions

TON

16 15 14

EN/PSV

TOP VIEW

5678

VSSA

PGND

MLPQ16: 4X4 BODY

BST

ILIM

VDDP

Device Package

SC411MLTRT

(2)

MLPQ-16

(1)

SC411EVB Evaluation Board

Notes:

1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE, RoHS and J-STD-020B compliant.

Pin # Pin Name Pin Function

1 VOUT Output voltage sense input. Connect to the output at the load.

2 VCCA Supply voltage input for the analog supply. Use a 10Ω /1μF RC ﬁ lter from 5VSUS to VSSA.

3FB

4 PGD

Feedback input. Connect to a resistor divider located at the IC from VOUT to VSSA to set the output voltage from 0.5V to VCCA.

Power Good open drain NMOS output. Goes high after a ﬁ xed clock cycle delay (440 cycles) following power up.

5 NC Not Connected.

6 VSSA Ground reference for analog circuitry. Connect directly to thermal pad.

7 PGND Power ground. Connect directly to thermal pad.

8 DL Gate drive output for the low side MOSFET switch.

9 VDDP

10 ILIM

+5V supply voltage input for the gate drivers. Decouple this pin with a 1μF ceramic capacitor to PGND.

Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor.

11 LX Phase node (junction of top and bottom MOSFETs and the output inductor) connection.

Page 8

POWER MANAGEMENT

Pin Descriptions (Cont.)

12 DH Gate drive output for the high side MOSFET switch.

13 BST Boost capacitor connection for the high side gate drive.

14 NC Not connected.

Enable/Power Save input. Pull down to VSSA to shut down VOUT and discharge it through

15 EN/PSV

22Ω (nom.). Pull up to enable VOUT and activate PSAVE mode. Float to enable VOUT activate continuous conduction mode (CCM). If ﬂ oated, bypass to VSSA with a 10nF ceramic capacitor.

SC411

16 TON

Thermal

Pad

This pin is used to sense VBAT through a pullup resistor, RTON, and to set the top MOSFET on-time. Bypass this pin with a 1nF ceramic capacitor to VSSA.

Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.

Shoot-Through Delay Timing Diagram

tplhDL tplhDH

Page 9

POWER MANAGEMENT

Application Information

+5V Bias Supplies

The SC411 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951.

SC411

in a nearly constant switching frequency without the need for a clock generator. For VOUT < 3.3V:

⎞

⎛

OUT

⎟

⎜

•+•=

)10x37R(10x3.3t

⎜

BAT

⎝

ns50

⎟ ⎠

−

TON

For optimal operation, the controller has its own ground reference, VSSA, which should be tied along with PGND directly to the thermal pad under the part, which in turn should connect to the ground plane using multiple vias. All external components referenced to VSSA in the Typical Application Circuit on Page 1 located near their respective pins. Supply decoupling capacitors should be located adjacent to their respective pins. A 10Ω resistor should be used to decouple VCCA from the main VDDP supply. All ground connections are connected directly to the ground plane as mentioned above. VSSA and PGND should be starred at the thermal pad. The VDDP input provides power to the upper and lower gate drivers; a decoupling capacitor is required. No series resistor between VDDP and 5V is required. See Layout Guidelines on page 17 for more details.

Pseudo-Fixed Frequency Constant On-Time PWM Controller

The PWM control architecture consists of a constant ontime, pseudo ﬁ xed frequency PWM controller (Block Dia- gram, Page 6). The output ripple voltage developed across the output ﬁ lter capacitor’s ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns.

On-Time One-Shot (tON)

The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage-proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results

For 3.3V ≤ VOUT ≤ 5V:

⎞

⎛

−

is a resistor connected from the input supply (VBAT)

TON

OUT

⎟

⎜

•+••=

)10x37R(10x3.385.0t

⎜

BAT

⎝

ns50

⎟ ⎠

to the TON pin. Due to the high impedance of this resistor, the TON pin should always be bypassed to VSSA using a 1nF ceramic capacitor.

EN/PSV: Enable, PSAVE and Soft Discharge

The EN/PSV pin enables the supply. When EN/PSV is tied to VCCA the controller is enabled and power save will also be enabled. When the EN/PSV pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. If PSAVE is enabled, the SC411 PSAVE comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (LX) to PGND. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve light-load efﬁ ciency and add hysteresis, the on-time is increased by 50% in power save. The efﬁ ciency improvement at light- loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when PSAVE is enabled. If the EN/PSV pin is pulled low, the related output will be shut down and discharged using a switch with a nominal resistance of 22 Ohms. This will ensure that the output is in a deﬁ ned state next time it is enabled and also ensure, since this is a soft discharge, that there are no dangerous negative voltage excursions to be concerned about. In order for the soft discharge circuitry to function correctly, the chip supply must be present.

Page 10

POWER MANAGEMENT

Application Information (Cont.)

Output Voltage Selection

The output voltage is set by the feedback resistors R3 & R5 of Figure 2 below. The internal reference is 1.5V, so the voltage at the feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be set to a minimum of 0.5V. The equation for setting the output voltage is:

= ( 1 + ――― ) • 0.5

OUT

VOUT

20k0

0402

56p

0402

14k3

0402

VOUT

VCCA

PGD

R3 R5

TON

EN/PSV

SC411

VSSA

13NC14

BST

ILIM

VDDP

PGND

TPAD

SC411

tor. In an extreme over-current situation, the top MOSFET will never turn back on and eventually the part will latch off due to output under-voltage (see Output Under-voltage Protection).

The current sensing circuit actually regulates the inductor valley current (see Figure 3). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:

Figure 2: Setting The Output Voltage

Current Limit Circuit

Current limiting of the SC411 can be accomplished in two ways. The on-state resistance of the low-side MOSFET can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. R ﬁ cient and less expensive. In both cases, the R

sensing is more ef-

DS(ON)

ILIM

resistor between the ILIM pin and LX pin sets the over current threshold. This resistor RILIM is connected to a 10μA current source within the SC411 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the R

ILIM

resis-

Figure 3: Valley Current Limiting

The equation for the current limit threshold is as follows:

Where (referring to Figure 4 on Page 17) R R

is the R

SENSE

LIMIT

DS(ON)

of Q2.

= 10μA × R

ILIM

/ R

(Amps)

SENSE

is R4 and

ILIM

For resistor sensing, a sense resistor is placed between the source of Q2 and PGND. The current through the source sense resistor develops a voltage that opposes the voltage developed across R oped across the R across R

a positive over-current exists and the high

ILIM,

resistor reaches the voltage drop

SENSE

. When the voltage devel-

ILIM

side MOSFET will not be allowed to turn on. When using an external sense resistor R

is the resistance of the

SENSE

sense resistor.

Page 11

POWER MANAGEMENT

Application Information (Cont.)

The current limit circuitry also protects against negative over-current (i.e. when the current is ﬂ owing from the load to PGND through the inductor and bottom MOSFET). In this case, when the bottom MOSFET is turned on, the phase node, LX, will be higher than PGND initially. The SC411 monitors the voltage at LX, and if it is greater than a set threshold voltage of 125mV (nom) the bottom MOSFET is turned off. The device then waits for approximately

2.5μs and then DL goes high for 300ns (typ) once more to sense the current. This repeats until either the overcurrent condition goes away or the part latches off due to output over-voltage (see Output Over-voltage Protection).

Power Good Output

The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 16%

above or 10% below its set voltage, PGD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. PGD is also held low during start-

up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. There is a 5μs delay built into the PGD circuitry to prevent false transitions.

Output Over-Voltage Protection

SC411

resets the fault latch and soft-start counter, and allows switching to occur if the device is enabled. Switching always starts with DL to charge up the BST capacitor. With the soft-start circuit (automatically) enabled, it will progressively limit the output current (by limiting the current out of the ILIM pin) over a predetermined time period of 440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mV to VOUT during this period to aid in startup).

2) 110 cycles at 50% ILIM with normal minimum offtime.

3) 110 cycles at 75% ILIM with normal minimum off-time.

4) 110 cycles at 100% ILIM with normal minimum offtime.

At this point the output under-voltage and power good circuitry is enabled.

There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V (nom) the output drivers are shut down and tri-stated.

When the output exceeds 16% of the its set voltage the low-side MOSFET is latched on. It stays latched on and the controller is latched off until reset*. There is a 5μs delay built into the OV protection circuit to prevent false transitions.

Output Under-Voltage Protection

When the output is 30% below its set voltage the output is latched in a tri-stated condition. It stays latched and the controller is latched off until reset*. There is a 5μs delay built into the UV protection circuit to prevent false transitions.

POR, UVLO and Soft-Start

An internal power-on reset (POR) occurs when VCCA exceeds 3V, starting up the internal biasing. VCCA undervoltage lockout (UVLO) circuitry inhibits the controller until VCCA rises above 4.2V. At this time the UVLO circuitry

* Note: to reset from any fault, VCCA or EN/PSV must be toggled.

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off (below ~1V). Semtech’s SmartDriverTM FET drive ﬁ rst pulls DH high with a pull-up resistance of 10Ω (typ) until LX = 1.5V (typ). At this point, an additional pull-up device is activated, reducing the resistance to 2Ω (typ); This negates the need for an external gate or boost resistor. The adaptive dead time circuit also monitors the phase node, LX, to determine the state of the high side MOSFET, and prevents the low side MOSFET from turning on until DH is fully off (LX below ~1V). Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.

Page 12

POWER MANAGEMENT

Application Information (Cont.)

Dropout Performance

The output voltage adjust range for continuous-conduction operation is limited by the ﬁ xed 550ns (maximum) mini- mum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:

DUTY+=

Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations.

SC411 System DC Accuracy

Two IC parameters affect system DC accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. The error comparator threshold does not drift signiﬁ cantly with supply and temperature. Thus, the error comparator contributes

1.2% or less to DC system inaccuracy. Board components and layout also inﬂ uence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors.

The on-pulse in the SC411 is calculated to give a pseudo- ﬁ xed frequency. Nevertheless, some frequency varia- tion with line and load can be expected. This variation changes the output ripple voltage. Because constant-on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of ﬁ ve, the valley of the output ripple will be VOUT. For example: if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, then the measured DC output will be 2.525V. If the ripple increases to 80mV with VBAT = 25V, then the measured DC output will be

2.540V.

)MI N(ON

)MA X(OFF

SC411

Switching frequency variation with load can be minimized by choosing MOSFETs with lower RDS(ON). High RDS(ON) MOSFETs will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage.

Design Procedure

Prior to designing an output and making component selections, it is necessary to determine the input voltage range and the output voltage speciﬁ cations. For purposes of demonstrating the procedure the output for the schematic in Figure 4 on Page 17 will be designed.

The maximum input voltage (V highest AC adaptor voltage. The minimum input voltage (V

) is determined by the lowest battery voltage after

BAT(MIN)

accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a V

range of 8V to 20V.

BAT

Four parameters are needed for the output:

1) nominal output voltage, V

OUT

2) static (or DC) tolerance, TOLST (we will use +/-4%).

3) transient tolerance, TOLTR and size of transient (we will use +/-8% and 6A for purposes of this demonstration).

4) maximum output current, I

Switching frequency determines the trade-off between size and efﬁ ciency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. A default R

tON

as a starting point, but this is not set in stone. The ﬁ rst thing to do is to calculate the on-time, tON, at V V

, since this depends only upon V

BAT(MAX)

For VOUT < 3.3V:

-12

ON_VBAT(MIN)

3.3 10

RtON+ 37 10

) is determined by the

BAT(MAX)

(we will use 1.2V).

(we will design for 6A).

OUT

value of 1MΩ is suggested

and

BAT(MIN)

, V

OUT

and R

+ 50 10-9s

tON

BAT

BAT(MIN)

The output inductor value may change with current. This will change the output ripple and thus the DC output voltage but it will not change the frequency.

Page 13

POWER MANAGEMENT

Application Information (Cont.)

SC411

and,

ON_VBAT(MAX)

3.3 10

-12

RtON+ 37 10

BAT(MAX)

OUT

+ 50 10-9s

From these values of tON we can calculate the nominal switching frequency as follows:

and,

)MI N(VBAT_SW

()

)MA X(VBAT_SW

()

OUT

•

OUT

•

)MI N(VBAT_ON)MI N(BAT

)MA X(VBAT_ON)MA X(BAT

tON is generated by a one-shot comparator that samples V

via R

BAT

used to charge an internal 3.3pF capacitor to V

, converting this to a current. This current is

tON

OUT

. The equations above reﬂ ect this along with any internal com- ponents or delays that inﬂ uence tON. For our example we select R

ON_VBAT(MIN)

fSW_VBAT(MIN)

= 1MΩ:

tON

= 563ns and t

= 266kHz and f

ON_VBAT(MAX)

SW_VBAT(MAX)

= 255ns

= 235kHz

Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of I

OUT

which will give us a starting place.

VBAT(MIN)

= V

BAT(MIN)VOUT

ON_VBAT(MIN)

0.5 I

OUT

and,

VBAT(MAX)

= V

BAT(MAX)VOUT

ON_VBAT(MAX)

0.5 I

OUT

For our example:

= 1.3μH and L

VBAT(MIN)

VBAT(MAX)

= 1.6μH

and,

RIPPLE_VBAT(MAX)

= V

BAT(MAX)VOUT

ON_VBAT(MAX)

P-P

For our example:

RIPPLE_VBAT(MIN)

= 1.74A

P-P

and I

RIPPLE_VBAT(MAX)

= 2.18A

P-P

From this we can calculate the minimum inductor current rating for normal operation:

II +=

)MAX(OU T)MI N(INDUCTOR

)MAX(VBAT_RIPPL E

)MIN(

For our example:

INDUCTOR(MIN)

= 7.1A

(MIN)

Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (R (R

ESR_TR(MAX)

Where ERRST is the static output tolerance and ERRDC is

ESR_ST(MAX)

()

)MA X(ST_ES R

) and transient ESR

2ERRERR

•−

DCST

Ohm s

)MA X(VBAT_RIPP LE

the DC error. The DC error will be 1.2% plus the tolerance of the feedback resistors, thus 2.2% total for 1% feedback resistors.

For our example:

ERRST = 48mV and ERRDC = 26.4mV, therefore,

ESR_ST(MAX)

= 19.8mΩ

)MA X(TR_ESR

()

⎛ ⎜

OUT

⎜ ⎝

ERRERR

−

DCTR

⎞

)MA X(VBAT_RIPPLE

⎟

⎟ ⎠

Ohm s

We will select an inductor value of 2.2μH to reduce the ripple current, which can be calculated as follows:

RIPPLE_VBAT(MIN)

= V

BAT(MIN)VOUT

ON_VBAT(MIN)

P-P

Where ERRTR is the transient output tolerance. Note that this calculation assumes that the worst case load transient is full load. For half of full load, divide the I

OUT

term

by 2.

Page 14

POWER MANAGEMENT

Application Information (Cont.)

For our example:

ERRTR = 96mV and ERRDC = 26.4mV, therefore,

ESR_TR(MAX)

= 9.8mΩ for a full 6A load transient

Firstly calculating the value of Z

BOT

TOP

()

015.0

required:

TOP

−•=

)MIN(VBAT_RIPPLE

SC411

Ohms015.0V

We will select a value of 12.5mΩ maximum for our design, which would be achieved by using two 25mΩ output capacitors in parallel.

Note that for constant-on converters there is a minimum ESR requirement for stability which can be calculated as follows:

)MIN(ESR

••π•

fC2

SWOUT

This criteria should be checked once the output capacitance has been determined.

Now that we know the output ESR we can calculate the output ripple voltage:

•=

VIRV

PP)MAX(VBAT_RIPPLEESR)MA X(VBAT_RIPPL E

−

and,

•=

VIRV

PP)MIN(VBAT_RIPPLEESR)MIN(VBAT_RIPPLE

−

Secondly calculating the value of C

required to achieve

TOP

this:

⎛

⎜

TOP

⎜

⎝

•π•

For our example we will use R

⎞

⎟

−

⎟

TOPTOP

⎠

)MIN(VBAT_SW

= 20.0kΩ and R

TOP

14.3kΩ, therefore,

= 6.67kΩ and C

TOP

We will select a value of C

= 60pF

TOP

= 56pF. Calculating the

TOP

value of VFB based upon the selected C

⎛ ⎜

⎜ ⎜

•=

⎜

)MIN(VBAT_RIPPLE)MI N(VBAT_FB

⎜

BOT

⎜ ⎜

⎝

TOP

BOT

For our example:

FB_VBAT(MIN)

= 14.8mV

- good

P-P

TOP

BOT

⎞ ⎟

⎟ ⎟

⎟

−

⎟ ⎟

••π•+

Cf2

TOP)MIN(VBAT_SW

⎟ ⎠

For our example:

RIPPLE_VBAT(MAX)

= 27mV

and V

P-P

RIPPLE_VBAT(MIN)

= 22mV

P-P

Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mV case no smaller than 10mV 15mV

the above component values should be revisited

P-P

at minimum V

P-P

. If V

P-P

RIPPLE_VBAT(MIN)

, and worst

BAT

is less than

in order to improve this. Quite often a small capacitor, C

, is required in parallel with the top feedback resis-

TOP

tor, R should not be greater than 100pF. The value of C be calculated as follows, where R

, in order to ensure that VFB is large enough. C

TOP

is the bottom feed-

BOT

TOP

can

back resistor.

Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, V

OUT_ST_POS

, when a load

release occurs:

VERRVV

DCOUTPOS_ST_OU T

For our example:

OUT_ST_POS

= 1.226V

•=

VTOLVPOSLIM

TROUTTR

Page 15

POWER MANAGEMENT

Application Information (Cont.)

Where TOLTR is the transient tolerance. For our example:

POSLIMTR = 1.296V

The minimum output capacitance is calculated as follows:

SC411

Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the “valley current”, which is the average output current minus half the ripple current. We use the maximum room temperature speciﬁ cation for MOSFET R at VGS = 4.5V for purposes of this calculation:

DS(ON)

COUT(MIN)

OUT

POSLIM

RIPPLE_VBAT(MAX)

OUT_ST_POS

This calculation assumes the absolute worst case condition of a full-load to no load step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps may be calculated by substituting the desired current for the I

OUT

term.

For our example:

OUT(MIN)

= 626μF.

We will select 440μF, using two 220μF, 25mΩ capacitors in parallel. For smaller load release overshoot, 660μF may be used. Alternatively, one 15mΩ or 12mΩ, 220μF, 330μF or 470μF capacitor may be used (with the appropriate change to the calculation for C

), depending upon

TOP

the load transient requirements.

−=

OUTVALLEY

)MIN(VBAT_RIPP LE

The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.

•

4.1R

()

VALLEYILIM

••=

2.1IR

)ON(DS

Ohm s

−

•

1010

For our example:

= 5.13A, R

VALLEY

= 9mΩ and R

DS(ON)

= 7.76kΩ

ILIM

We select the next lowest 1% resistor value: 7.68kΩ

Thermal Considerations

The junction temperature of the device may be calculated as follows:

CPTT

°θ•+=

JADAJ

Where:

Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage:

()

VVVI •−•=

OUT)MI N(BATOUT)RMS(IN

OUT

RMS

MIN_BAT

For our example:

IN(RMS)

= 2.14A

RMS

Input capacitors should be selected with sufﬁ cient ripple current rating for this RMS current, for example a 10μF, 1210 size, 25V ceramic capacitor can handle approximately 3A

. Refer to manufacturer’s data sheets and

RMS

derate appropriately.

T P

= ambient temperature (°C)

= power dissipation in (W)

θJA = thermal impedance junction to ambient

from absolute maximum ratings (°C/W)

The power dissipation may be calculated as follows:

IVDDPIVCCAP

•+•=

VDDPVCCAD

WDmA1VBSTfQV

••+••+

Where:

VCCA = chip supply voltage (V) I

= operating current (A)

VCCA

VDDP = gate drive supply voltage (V)

Page 16

POWER MANAGEMENT

Application Information (Cont.)

= gate drive operating current (A)

VDDP

Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) VBST = boost pin voltage during tON (V) D = duty cycle Inserting the following values for VBAT this is the worst case condition for power dissipation in the controller) as an example (VOUT = 1.2V),

TA = 85°C

θJA = 100°C/W

VCCA = VDDP = 5V I

VCCA

VDDP

= 1100μA (data sheet maximum)

= 150μA (data sheet maximum) Vg = 5V Qg = 60nC f = 266kHz VBAT VBST D

(MIN)

= 8V

(MIN)

= VBAT

+VDDP = 13V

(MIN)

= 1.2/8 = 0.15

condition (since

(MIN)

SC411

gives us,

−−

1015051011005P

W088.0

••+••=

339

−−

15.0101131026610605

•••+••••+

and,

C8.93100088.085T

°=•+=

As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special thermal consideration during layout.

The Reference Design is shown in Figure on Page 17.

An additional design optimized for efﬁ ciency and capable of a higher load current of 10A is shown in Figure 11 on Page 21.

Page 17

POWER MANAGEMENT

Layout Guidelines

SC411

VBAT

R1 1M

0402

PGOOD

1nF

0402

VBAT = 8V to 20V VOUT = 1.2V @ 6A

56p

0402

VOUT

R3 20k0

0402

R5 14k3

0402

R2 10R

0402

5VSUS

1uF

0603

SOD323

C1 0u1

R4 7k 87

0402

C10

1uF

0603

TPAD

BST

ILIM

VDDP

VOUT

VCCA

PGD

TON

EN/PSV

SC411

NC5VSSA6PGND7DL

IRF 7811AV

FDS6676S

VBAT5VSUS

2n2/50V

0u1/25V

0603

10u/25V

1210

220u/25m

7343 7343

220u/25m

VOUT

0402

L1 2u2

Figure 4: Reference Design

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, and the power ground pin, PGND, should both connect directly to the device thermal pad. The thermal pad should connect to the ground plane(s) using multiple vias.

The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace in a quiet layer (if possible) from the output capacitor back to the chip. All components should be located adjacent to their respective pins with an emphasis on the chip decoupling capacitors (VCCA and VDDP) and the components that are shown connecting to VSSA in the above schematic. Make any ground connections simply to the ground plane.

Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper ﬁ lled areas if possible. Do not use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirements (and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.

We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in more detail.

Page 18

SC411

POWER MANAGEMENT

The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at the control section ﬁ rst, locate all components referenced to VSSA on the schematic and place these components at the chip. Drop vias to the ground plane as needed.

VBAT

1M 0402

1nF 0402

56p 0402

VOUT

20k0 0402

14k3 0402

10R 0402

5VSUS

1uF 0603

TON

VOUT

VCCA

PGD

NC5VSSA6PGND7DL

EN/PSV

SC411

TPAD

BST

ILIM

VDDP

Figure 5: Components Connected to VSSA

5VSUS

C10

1uF 0603

Figure 6: Control Section Example

In Figure 6 above, all components referenced to VSSA have been placed and connected to the ground plane with

Decoupling capacitors C9 and C10 are as close as possible to their pins and connected to the ground plane

vias. with vias. Note how the VSSA and PGND pins are connected directly to the thermal pad, which has 4 vias to the ground plane (not shown).

Page 19

SC411

POWER MANAGEMENT

As shown below, VOUT should be routed away from noisy traces (such as BST, DH, DL and LX) and in a quiet layer (if possible) to the output capacitor(s).

TPAD

BST

ILIM

VDDP

220u/25m 7343 7343

220u/25m

VOUT

56p 0402

VOUT

R3 20k0 0402

R5 14k3 0402

VOUT

VCCA

PGD

TON

EN/PSV

SC411

NC5VSSA6PGND7DL

Figure 7: VOUT Sense Trace Routing

Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible.

VBAT

IRF7811AV

2n2/50V

0u1/25V

0402 0603

10u/25V 1210

L1 2u2

VOUT

FD S6676S

220u/25m

7343 7343

Figure 8: Power Section and Input Loop

The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. See Figure 9 for an example.

Page 20

POWER MANAGEMENT

SC411

Figure 9: Power Component Placement and Copper Pours

Key points for the power section:

1) There should be a very small input loop, well decoupled.

2) The phase node should be a large copper pour, but compact since this is the noisiest node.

3) Input power ground and output power ground should not connect directly, but through the ground planes instead.

4) The current limit resistor should be placed as close as possible to the ILIM and LX pins.

Connecting the control and power sections should be accomplished as follows (see Figure 10 on the following page):

1) Route VOUT in a “quiet” layer away from noise sources.

2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path.

3) BST is also a noisy node and should be kept as short as possible.

4) Connect PGND and VSSA directly to the thermal pad, and connect the thermal pad to the ground plane using multiple vias.

Page 21

POWER MANAGEMENT

SC411

TON

VOUT

VCCA

EN/PSV

SC411

BST

IRF7811AV

L1 2u2

R4 7k87

ILIM

0402

PGD

TPAD

PGND

VSSA

VDDP

FDS6676S

Figure 10: Connecting the Control and Power Sections

Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.

VOUT

R3 28kR328k

0402

R5 20kR520k

0402

R2 10RR210R

0402

5VSUS

1uFC91uF

0603

5VSUS VBAT

D1D1

SOD323

TON

VOUT

VCCA

PGD

EN/PSV

SC411

NC5VSSA6PGND7DL

TPAD

BST

ILIM

VDDP

R4 7k15R4 7k15

0402

C10

1uF

0603

0u1C10u1

0603

IRF7821Q1IRF7821

IRF7832Q2IRF7832

L1 = 1.5uH Vishay IHLP 5050CE

C6, C7 = 470uF / 15milli ohm Sanyo POS Cap 2R5TPE470MF

10u/25VC410u/25V

0u1/25VC30u1/25V

2n2/50VC22n2/50V

0402 0603 1210

L1 1u5L11u5

470u/15m

7343 7343

470u/15m

VOUT

VBAT

R1 806kR1806k

0402

220pC5220p

0402

PGOOD

1nFC81nF

0402

VBAT = 8V to 20V VOUT = 1.2V @ 10A

Figure 11: High Efﬁ ciency Design

Page 22

POWER MANAGEMENT

Typical Characteristics

For efﬁ ciency charts, refer to High Efﬁ ciency Design, Figure 11 on page 21.

For all other data, refer to the Reference Design, Figure 4 on Page 17.

SC411

1.2V Efﬁ ciency (Power Save Mode) (High Efﬁ ciency Design, Page 21)

100

= 8V

BAT

= 20V

BAT

Efficiency (%)

012345678910

OUT

(A)

1.2V Output Voltage (Power Save Mode) vs. Output Current vs. Input Voltage

1.220

1.216

1.212

1.208

1.204

(V)

1.200

OUT

1.196

1.192

1.188

1.184

1.180 0123456

= 20V

BAT

= 8V

BAT

(A)

OUT

1.2V Efﬁ ciency (Continuous Conduction Mode) (High Efﬁ ciency Design, Page 21)

100

= 8V

BAT

= 20V

BAT

Efficiency (%)

012345678910

OUT

(A)

1.2V Output Voltage (Continuous Conduction Mode) vs. Output Current vs. Input Voltage

1.220

1.216

1.212

1.208

1.204

(V)

1.200

OUT

1.196

1.192

1.188

1.184

1.180 0123456

= 20V

BAT

= 8V

BAT

(A)

OUT

1.2V Switching Frequency (Power Save Mode) vs. Output Current vs. Input Voltage

400

350

300

250

200

150

Frequency (kHz)

100

0123456

= 8V

BAT

= 20V

BAT

(A)

OUT

1.2V Switching Frequency (Continuous Conduction Mode) vs. Output Current vs. Input Voltage

400

350

300

250

200

150

Frequency (kHz)

100

0123456

= 8V

BAT

= 20V

BAT

(A)

OUT

Page 23

POWER MANAGEMENT

Typical Characteristics

Load Transient Response,

Continuous Conduction Mode, 0A to 6A to 0A

Load Transient Response,

Continuous Conduction Mode, 0A to 6A Zoomed

SC411

Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40μs/div.

Load Transient Response,

Continuous Conduction Mode, 6A to 0A Zoomed

Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10μs/div.

Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10μs/div.

Please refer to Figure 4 on Page 17 for test schematic

Page 24

POWER MANAGEMENT

Typical Characteristics

Load Transient Response,

Power Save Mode, 0A to 6A to 0A

SC411

Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 20V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 40μs/div.

Startup (CCM), EN/PSV 0V to Floating

Load Transient Response,

Power Save Mode, 6A to 0A Zoomed

Trace 1: 1.2V, 20mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10μs/div.

Trace 1: 1.2V, 50mV/div., AC coupled Trace 2: LX, 10V/div Trace 3: not connected Trace 4: load current, 5A/div Timebase: 10μs/div.

Please refer to Figure 4 on Page 17 for test schematic

Page 25

POWER MANAGEMENT

Typical Characteristics

Startup (PSV), EN/PSV Going High

SC411

Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.

Startup (CCM), EN/PSV 0V to Floating

Trace 1: 1.2V, 0.5V/div. Trace 2: LX, 10V/div Trace 3: EN/PSV, 5V/div Trace 4: PGD, 5V/div. Timebase: 1ms/div.

Please refer to Figure 4 on Page 17 for test schematic

Page 26

POWER MANAGEMENT

Outline Drawing - MLPQ-16

SC411

PIN 1

INDICATOR

(LASER MARK)

aaa

D/2

e/2

LxN

bxN

bbb C A B

E/2

DIMENSIONS

DIM

SEATING PLANE

INCHES

MIN MAX

NOM

.031

.000

.010

.153 .157 .161 3.90 4.00 4.10

.079

.153 .157 .161 3.90 4.00 4.10

e L N

aaa bbb

.040

.002-0.00

(.008)

.012

.014

.085

.089

.089.085.079

16 .003 .004 0.10

MILLIMETERS

MINMAX NOM

0.80

0.25

2.00

2.00 2.15 2.25

0.30.012 .020.016 0.40 0.50

0.65 BSC.026 BSC

(0.20)

0.30

2.15

0.08

1.00

0.05

0.35

2.25

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

Marking Information

Top Marking

SC411

yyww xxxxx

xxxxx

yyww = Date Code (Example: 0552)

xxxxx = Semtech Lot Number (Example: E9010)

xxxxx = (Example: 1-100)

Page 27

POWER MANAGEMENT

Land Pattern - MLPQ-16

2x (C)

SC411

DIMENSIONS

DIM

2x Z

2x G

H K P X Y Z

INCHES

(.152)

.114 .091 .091 .026 .016 .037 .189

MILLIMETERS

(3.85)

2.90

2.30

0.65

0.40

0.95

4.80

NOTES:

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

Semtech SC411 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual