SEMTECH SC338A Technical data

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SC338(A)
Ultra Low Output Voltage
Dual Linear FET Controller
POWER MANAGEMENT
Revision: November 12, 2004
Description Features
The SC338(A) is an ultra low output voltage dual power supply controller designed to simplify power management for notebook PCs. It is part of Semtech’s Smart LDO
TM
family of products. The SC338(A) has two user adjustable outputs that can be set anywhere between
0.5V and 3.3V (VIN = 12V, anywhere between 0.5V and
1.8V for VIN = 5V) using two external resistors per output.
SC338(A) features for each output include tight output voltage regulation (±2.5% over -40°C to +85°C for SC338, ±1.5% over 0°C to +85°C for SC338A), enable controls, open drain power good signals, under-voltage protection and soft start. The enable pins allow the part to enter a very low power standby mode. Pulling them high enables the outputs. The power good pins are open drain and assert low when the voltage at their respective adjust pins is below 88% (typ.) of nominal. If the voltage at the adjust pin is below 50% (typ.) of nominal, the under voltage protection circuitry will shut down that output. The SC338(A) is available in an MSOP-10 surface mount package.
±1.5% and ±2.5% reference voltage options
available
Two independant and fully adjustable outputsWide supply voltage range permits operation from
5V or 12V rails
Very low quiescent current (500µA typical with both
outputs enabled and 5V input)
Indivdual Enable control for each outputIndividual Power Good monitoring and signalling for
each output
Gate drives from input supply enable use of
N-channel MOSFETs
User selectable dropout voltageIndividual under-voltage protection for each outputMSOP-10 surface mount package
Notebook PCsSimple dual power supplies
Typical Application Circuit
Applications
1.05V Enable
R3
20.0k
1.05V Power Good
U1 SC338(A)
1
2
3
4
5
6
7
8
9
10
DRV1
ADJ1
EN1
PGD1
GND PGD2
EN2
ADJ2
DRV2
IN
C1
0.1uF (1)
1.8V +/-5% IN
R4
10.0k
R6 2k (2)
C5
10nF (2)
1.5V Enable
1.05V @ 3A
1.2V +/-5% IN
Notes: (1) Additional capacitance may be required if far from supply (2) Optional soft-start components
C6
0.1uF
Q1
IRF7311
4
1
2
3
56
7
8
1.5V @ 1.5A
or similar
1.5V Power Good
C7
10nF (2)
C3
100uF, 25mOhm POSCAP
C4
100uF, 25mOhm POSCAP
R1
11.0k
5V or 12V IN
R5 2k (2)
C2
0.1uF (1)
R2
10.0k
 
 
+=
2R
1R
15.0V
1OUT
 
 
+=
4R
3R
15.0V
2OUT
查询SC338供应商
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SC338(A)
PRELIMINARYPOWER MANAGEMENT
Absolute Maximum Ratings
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Electrical Characteristics
Unless specified: TA = 25°C, VIN = VEN = 5V ±
5%, V
PWR
(1)
= 1.5V ± 5%, 0A ≤ I
OUT
3A.
Values in bold apply over full operating ambient temperature range.
Note: (1) Or VIN, if VIN = 5V.
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
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SC338(A)
POWER MANAGEMENT
Notes:
(1) V
PWR
= input voltage to pass device drains (or sources depending upon orientation of FETs).
(2) If V
TH(UV)
is exceeded for longer than 50µs (nom.) the protection circuitry will shut down that output.
(3) During startup only, V
TH(PGD)
is -6% (typ.), then switches to -12% (typ.).
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V
NE
V0=0Aµ
V
NI
V=
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JDA
V
JDA
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A
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)DGP(HT
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VRD
V,Am0=
NI
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VRD
V,Am0=
NI
V5= 07.4 58.4
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)VU(HT
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)DGP(HT
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JDA
I,V4.0=
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tnerruC
I
DGP
V
JDA
V0,V5.0= V
DGP
V
NI
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emiTesiRtuptuO
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TUO
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TUO
,
V
TUO
V50.1=
t
r
C
DNG-VRD
decalpton=051sµ
C
DNG-VRD
Fn01=058
Electrical Characteristics (Cont.)
Unless specified: TA = 25°C, VIN = VEN = 5V ±
5%, V
PWR
(1)
= 1.5V ± 5%, 0A ≤ I
OUT
3A.
Values in bold apply over full operating ambient temperature range.
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SC338(A)
PRELIMINARYPOWER MANAGEMENT
Pin Descriptions
Top View
(MSOP-10)
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)1(
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)2(
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RTSMI833CS
)3(
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01-POSM
TRTSMI833CS
)5()3(
RTSMIA833CS
)4(
TRTSMIA833CS
)5()4(
Notes:
(1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) VIN = 12V (0.5V to 1.8V for V
IN
= 5V).
(3) V
ADJ
is ±2.5% over -40°C ≤ TA +85°C.
(4) V
ADJ
is ±1.5% over 0°C ≤ TA +85°C.
(5) Lead free product. This product is fully WEEE and RoHS compliant.
Pin Configuration
Ordering Information
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)XAM(TUO
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NI
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 
 
+=
2R
1R
15.0V
1OUT
 
 
+=
4R
3R
15.0V
2OUT
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SC338(A)
POWER MANAGEMENT
Block Diagram
(0.95 VBG
at start-up)
(0.95 VBG at start-up)
Marking Information
AK00: Identifier for SC338 yyww: Date code (Example: 0012) xxxx: Semtech Lot # (Example: E901 xxxx: 01-1)
SC338
Bottom Mark
xxxx xxxx
yyww
AK00
Top Mark
338A: Identifier for SC338A yyww: Date code (Example: 0012) xxxx: Semtech Lot # (Example: E901 xxxx: 01-1)
SC338A
Bottom Mark
xxxx xxxx
Top Mark
AK0A yyww
338A
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SC338(A)
PRELIMINARYPOWER MANAGEMENT
Theory Of Operation
The SC338(A) dual linear FET controller provides a simple way to drive two N-channel MOSFETs to produce tightly regulated output voltages from one or two available, higher, supply voltages. It takes its power from either a 5V or 12V supply, drawing typically 500µA while operating.
It contains an internal bandgap reference which is compared to the output voltages via resistor dividers. These resistor dividers are external and user selectable . Depending upon the input voltage used for the device, the drive pin (DRV1, DRV2) can pull up to a guaranteed minimum of 6.6V (from 12V supply) or 4.7V (from 5V supply). Thus the device can be used to regulate a large range of output voltages by careful selection of the external MOSFETs (see component selection, below).
The SC338(A) includes an active high enable control (EN1, EN2) for each output. If this pin is pulled low, the related drive pin is pulled low, turning off the N-channel MOSFET.
If the pin is pulled up to 1.8V ≤ V
EN
V
IN
, the drive pin will
be enabled. This pin should not be allowed to float.
Each output has a power good output (PGD1, PGD2) which are open drain outputs that pull low if the related output is below the power good threshold (-12% of the programmed output voltage typical, -6% typical at start­up). The power good circuitry is active if the device is enabled, regardless of the state of the over current latch. The power good circuitry is not active if that particular output is disabled.
Also included for each output is an overcurrent protection circuit that monitors the output voltage. If the output voltage drops below 50% (typ.) of nominal, as would occur during an overcurrent or short condition, the device will pull the drive pin low and latch off. The device will need to have the power supply or enable pin toggled to reset the latch condition. Each output latches independently (i.e. if one output latches off, the other output will function normally).
Drive Outputs and Soft Start
The drive outputs for each output are source and sink capable. The sink current is typically 0.8mA at 5V in (1mA at 12V in). The source current is typically 2mA at 5V in
Applications Infomation
and 3.75mA at 12V in during normal operation. The high side drive voltage is generated from V
IN
by a 7V (nominal) low dropout regulator, thus at 12V in, 6.9V is available and at 5V in, 4.85V is available (since the LDO will be in dropout).
At start-up, the source current available from the drive pins is limited to 10µA (typical) until the power good threshold is reached, at approximately 6% below nominal output voltage. At this point the full drive capability is enabled. With this constant current source at start-up, it is a simple matter to use a small capacitor on the drive pin to slow this rate of rise. The rate of rise of the drive pin voltage will be:
s/V
C
I
dt
dV
SS
DRVDRV
=
A 10nF soft start capacitor will give a 1ms output rise time for VIN = 12V and V
OUT
= 1.05V, for example. The output rise time will of course depend upon the gate threshold of the MOSFET being used. Please refer to the Output Rise Time chart on Page 13 showing typical output rise times. For very low ESR output capacitors
(<5m) and very high soft start capacitance (>100nF),
it may be necessary to add a resistor in series with the soft start capacitor to ensure stability. Generally, however, this resistor is not required, as this is a very unlikely situation.
The soft start capacitance does not adversely affect transient response since the drive current capability is 200 times higher once the device has started.
OCP and Power Supply Sequencing
The SC338(A) has output undervoltage protection that looks at a particular output to see if it is a) less than 50% (typical) of it’s nominal value and b) V
DRV
for that output is within 350mV (typical) of maximum. If both of these criteria are met, there is a 50µs (typical) delay and then the output is shut down. This provides inherent immunity to UV shutdown at start-up (which may occur while the output capacitors are being charged) since V
DRV
has a very slow rate of rise with I
DRV
limited to 10µA.
At start-up, it is necessary to ensure that the power supplies and enables are sequenced correctly to avoid erroneous latch-off. For UV latch-off not to occur at start­up due to sequencing issues, the key is that the voltage
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SC338(A)
POWER MANAGEMENT
Applications Infomation (Cont.)
SC338(A) Supply Comes Up Before MOSFET Drain Supply
MOSFET Drain Supply Comes Up Before SC338(A) Supply
Figure 1: Power Supply Sequencing
supplied to the MOSFET drain should be greater than the output undervoltage threshold when that output is enabled. This assumes that the drop through the pass MOSFET is negligible. If not, then this drop needs to be taken into account also since: V
OUT
= V
DRAIN
- (I
OUT
x R
DS(ON)
).
If the supply to the SC338(A) IN pin comes up before the supply to the MOSFET drain, then that output should be enabled as the supply to the MOSFET drain is applied
- the Power Good signal for this rail would be ideal. If the power supply to the MOSFET drain comes up before the power supply to the SC338(A) IN pin, then the output can either be enabled with the supply to the IN pin or afterwards. Please see the example below.
Example: SC338(A) powered from 5V, output 1 powered
from 1.8V set for 1.5V out, output 2 not shown for simplicity. Worst case undervoltage threshold is 60% (over temperature) of 1.5V, or 0.9V. The typical enable threshold is ~1V. See Figure 1 below.
Component Selection
Output Capacitors: low ESR capacitors such as Sanyo
POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: placement of low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps at the input to the MOSFET (V
DRAIN
) will help to hold up the power supply during fast load changes, thus improving overall transient response. If V
DRAIN
is located at the bulk capacitors for
the upstream voltage regulator, additional capacitance
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SC338(A)
PRELIMINARYPOWER MANAGEMENT
may not be required. In this case a 0.1µF ceramic capacitor will suffice. The input supply to the SC338(A) should be bypassed with a 0.1µF ceramic capacitor.
MOSFETs: very low or low threshold N-channel MOSFETs are required. Selecting FETs rated for VGS of 2.7V or 4.5V will depend upon the available drive voltage (6.9V from 12V in or 4.85V from 5V in), the output voltage and output current. For the device to work under all operating conditions, a maximum R
DS(ON)
must be met to
ensure that the output will never go into dropout:
=
)MAX(OUT
)MAX(OUT)MIN(IN
)MAX)(ON(DS
I
VV
R
Note that R
DS(ON)
must be met at all temperatures and at
the minimum VGS condition.
Setting The Output Voltage: the adjust pins connect directly to the inverting input of the error amplifiers, and the output voltage is set using external resistors (please refer to the Typical Application Circuit on page 1).
Using output 1 as an example, the output voltage can be calculated as follows:
 
 
+=
2R
1R
15.0V
OUT
The input bias current for the adjust pin is so low that it can be safely ignored. To avoid picking up noise, it is recommended that the total resistance of the feedback
chain be less than 100kΩ.
Please see Table 1 on this page for recommended resistor values for some standard output voltages. All resistors are 1%, 1/10W.
The maximum output voltage that can be obtained from each output is determined by the input supply voltage and the R
DS(ON)
and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and the worst-case drive voltage, V
OUT(MAX)
is given by:
)MAX)(ON(DS)MAX(OUT)MIN(DRAIN)MAX(OUT
RIVV =
Applications Infomation (Cont.)
)V(TUOVk(3Rro1R ΩΩΩΩΩ)k(4Rro2R ΩΩΩΩΩ)
50.10.110.01
2.10.410.01
5.10.020.01
5.23.543.11
3.34.363.11
Table 1: Recommended Resistor Values For SC338(A)
Design Example
Goal: 1.05V±5% @ up to 2.5A from 1.2V±5% and 5V±5%
Solution 1: no passive droop.
Total window for DC error, ripple and transient is ±52.5mV
Since this device is linear, and assuming that it has been designed to not ever enter dropout, we do not have ripple on the output.
The DC error for this output is the sum of:
V
REF
accuracy = ±2.5% = ±26.3mV
Feedback chain tolerance = ±1% = ±10.5mV
Load regulation = ±0.25% = ±2.6mV
Set resistors per Table 1 should be 11.0k (top) and
10.0k (bottom).
Total DC error = ±3.75% = 39.4mV
This leaves ±1.25% = 13.1mV for the load transient ESR spike, therefore:
== m2.5
A5.2
mV1.13
R
)MAX(ESR
Bulk capacitance required is given by:
F
dV
tdI
C
)MIN(BULK
µ
=
Where dI is the maximum load current step, t is the maximum regulator response time and dV is the
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SC338(A)
POWER MANAGEMENT
allowable voltage droop. Therefore with dI = 2.5A, t = 1µs, and dV = 13.1mV:
F191
101.13
1015.2
C
3
6
)MIN(BULK
µ=
=
So if we use 1% V
OUT
set resistors we would select 2 x
>100µF, 12m POSCAPs for output capacitance (which
assumes that local ceramic bypass capacitors will
absorb the balance of the (6 - 5.3)m ESR requirement - otherwise 10m capacitors should be
used).
If we use 0.1% set resistors, then the total DC error becomes ±2.85% = ±29.9mV, leaving ±2.15% = 22.6mV for the ESR spike. In this case:
== m0.9
A5.2
mV6.22
R
)MAX(ESR
and
F111
106.22
1015.2
C
3
6
)MIN(BULK
µ=
=
So for 0.1% resistors we could use 2 x 100µF, 18m POSCAPs for output capacitance, or 1 x >100µF, 10m
POSCAP.
Obviously this is a very severe example, since the output voltage is so low and therefore the allowable window is very small. See solution 2 below for an alternate solution. For higher output voltages the components required will be less stringent.
The input capacitance needs to be large enough to stop the input supply from collapsing below -5% (i.e. the design minimum) during output load steps. If the input to the pass MOSFET is not local to the supply bulk capacitance then additional bulk capacitance may be required.
MOSFET selection: since the input voltage to the SC338(A) is 5V±5%, the minimum available gate drive is:
V3.3)1025.14.4(V
GS
==
So a MOSFET rated for VGS = 2.7V will be required, with an R
DS(ON)(MAX)
(over temp.) given by:
=
=
=
m36
5.2
)05.114.1(
I
)VV(
R
)MAX(OUT
OUT)MIN(IN
)MAX)ON(DS
Obviously, if a 12V rail is available to power the SC338(A), the number of FET options increases dramatically.
Applications Infomation (Cont.)
Solution 2: using passive droop.
or similar
1.075V
1.2V +/-5% IN
1.05V @ 2.5A
C1
0.1uF
R1
11.0k
C3
100uF, 25mOhm POSCAP
U1
SC338(A)
1
2
3
4
5
6
7
8
9
10
DRV1
ADJ1
EN1
PGD1
GND PGD2
EN2
ADJ2
DRV2
IN
R2
10.0k
RDROOP
20mOhm
Q1
IRF7311
4
1
2
3
5
6
78
Passive droop allows us to use almost the full output tolerance window for transients, hence making the output capacitor selection simpler and (hopefully) cheaper. The trade-offs are the cost of the droop resistor versus the reduction in output capacitor cost, and the reduction in headroom which impacts MOSFET selection. The top of the feedback chain connects to the “input” side of R
DROOP
, and the output is set for 1.075V.
Thus at no load, V
OUT
will be 1.075V (or 1.05V + 2.4%)
and at I
OUT
= 2.5A, V
OUT
will be 1.025V (or 1.05V - 2.4%).
If 1% set resistors are used, the total DC error will be ±3.75% = 39mV. Thus at no load, the minimum output voltage will be given by:
V036.1039.0075.1V
)LOAD_NO_MIN(OUT
==
This leaves 38.5mV for transient response, giving:
==
m4.15
A5.2
mV5.38
R
)MAX(ESR
and
F65
105.38
1015.2
C
3
6
)MIN(BULK
µ=
=
Instead of 2 x 100µF, 12m capacitors, we can use 1 x 100µF, 15m capacitor.
Layout Guidelines
The advantages of using the SC338(A) to drive external MOSFETs are a) that the bandgap reference and control circuitry are in a die that does not contain high power dissipating devices and b) that the device itself does not
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SC338(A)
PRELIMINARYPOWER MANAGEMENT
Applications Infomation (Cont.)
The 0.1µF bypass capacitor should be located close to the supply (IN) and GND pins, and connected directly to the ground plane.
The feedback resistors should be located at the device, with the sense line from the output routed from the load (or top end of the droop resistor if passive droop is being used) directly to the feedback chain. If passive droop is being used, the droop resistor should be located right at the load to avoid adding additional unplanned droop.
Sense and drive lines should be routed away from noisy traces or components.
For very low input to output voltage differentials, the input to output / load path should be as wide and short as possible. Where greater headroom is available, wide traces may suffice.
Power dissipation within the device is practically negligible, thus requiring no special consideration during layout. The MOSFET pass devices should be laid out according to the manufacturer’s guidelines for the power being dissipated within them.
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SC338(A)
POWER MANAGEMENT
Quiescent Current vs. Junction Temperature
vs. Input Voltage
Standby Current vs. Junction Temperature
vs. Input Voltage
Start Threshold vs.
Junction Temperature
Enable Input Threshold Voltage
vs. Junction Temperature
Reference Voltage vs.
Junction Temperature
Drive Pin Output Current (Sourcing) at Startup
vs. Junction Temperature vs. Input Voltage
Typical Characteristics
0
100
200
300
400
500
600
700
800
900
-50 -25 0 25 50 75 100 125
T
J
(°C)
I
Q
(µA)
Both VEN = 5V Both V
ADJ
< V
BG
VIN = 5V
V
IN
= 12V
0.01
0.1
1
10
100
-50 -25 0 25 50 75 100 125
T
J
(°C)
I
Q(OFF)
(µA)
VIN = 12V
VIN = 5V
Both V
EN
= 0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
UVLO
(V)
VIN rising
V
IN
falling
0.490
0.492
0.494
0.496
0.498
0.500
0.502
0.504
0.506
0.508
0.510
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
ADJ
(mV)
VIN = VEN = 5V
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
IH/L
(V)
VIN = 5V
V
IH
V
IL
0
2
4
6
8
10
12
14
16
18
20
-50 -25 0 25 50 75 100 125
T
J
(°C)
I
DRV
(µA)
VIN = 12V
VEN = 5V V
ADJ
< V
TH(PGD)
VIN = 5V
12 2004 Semtech Corp. www.semtech.com
SC338(A)
PRELIMINARYPOWER MANAGEMENT
Drive Pin Output Current (Sourcing) vs.
Junction Temperature vs. Input Voltage
Drive Pin Output Current (Sinking) vs.
Junction Temperature vs. Input Voltage
Typical Characteristics (Cont.)
Drive Pin Output Voltage (Full On) vs.
Junction Temperature vs. Input Voltage
Under Voltage Trip Threshold
vs. Junction Temperature
Power Good Threshold vs.
Junction Temperature
Power Good Logic Low Output Voltage
vs. Junction Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125
T
J
(°C)
I
DRV
(mA)
VEN = 5V V
ADJ
< V
BG
VIN = 12V
V
IN
= 5V
0
200
400
600
800
1000
1200
-50 -25 0 25 50 75 100 125
T
J
(°C)
I
DRV
(µA)
VEN = 5V V
ADJ
> V
BG
VIN = 5V
V
IN
= 12V
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
DRV
(V)
VEN = 5V I
DRV
= 0mA
V
ADJ
< V
BG
VIN = 12V
V
IN
= 5V
-60
-58
-56
-54
-52
-50
-48
-46
-44
-42
-40
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
TH(UV)
(%V
ADJ
)
VIN = VEN = 5V
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0.0
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
TH(PGD)
(%V
ADJ
)
VIN = VEN = 5V
Startup only
Normal operation
0
25
50
75
100
125
150
175
200
-50 -25 0 25 50 75 100 125
T
J
(°C)
V
PGD
(mV)
VIN = VEN = 5V V
ADJ
= 0.4V
I
PGD
= -1mA
13 2004 Semtech Corp. www.semtech.com
SC338(A)
POWER MANAGEMENT
Output Rise Time At Startup vs. Soft Start
Capacitance vs. Input Voltage
Typical Characteristics (Cont.)
0.1
1
10
100
0.1 1 10 100
C
DRV
(nF)
t
r(OUT)
(ms)
VEN = 5V T
J
= 25°C
V
OUT
= 1.05V
C
OUT
= 100µF, 25m
I
OUT
= 0A
MOSFET = IRF7311
V
IN
= 5V
V
IN
= 12V
VIN = 5V, 1.2V in to 1.05V out I
OUT
= 0.01A to 2.51A to 0.01A
C
OUT
= 2 x 100µF, 25m
Trace 1: V
OUT
, 20mV/div., offset 1V
Trace 2: V
DRV
, 2V/div. Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20µs/div.
Load rise/fall times 35A/µs
Load Transient Response, No Passive Droop
VIN = 5V, 1.2V in to 1.05V out I
OUT
= 0.01A to 2.51A to 0.01A
C
OUT
= 1 x 100µF, 25m
R
DROOP
= 20m
Trace 1: V
OUT
, 20mV/div., offset 1V Trace 2: not connected Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20µs/div.
Load rise/fall times 35A/µs
Load Transient Response, With Passive Droop
14 2004 Semtech Corp. www.semtech.com
SC338(A)
PRELIMINARYPOWER MANAGEMENT
Outline Drawing - MSOP-10
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
Contact Information
bbb C A-B D
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
3. OR GATE BURRS.
DATUMS AND TO BE DETERMINED AT DATUM PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
-B-
NOTES:
1.
2. -A- -H-
SIDE VIEW
A
B
C
D
H
PLANE
.010
.004
-
.016
.003
.024
(.037)
-
.000 .030
---
-
0.25
0.10
-
0.60 (.95)
.032
.009
0.40
0.08
.043 .006 .037 0.75
0.00
-
0.80
0.23
-
0.95
1.10
0.15
-
-
-
e
.193 BSC .020 BSC
DETAIL
aaa C
SEATING
INDICATOR
ccc
C
2X N/2 TIPS
PIN 1
2X
E/2
10
SEE DETAIL
A1
A
A2
bxN
D
0.25
A
PLANE
GAGE
.003
E1
12
N
.114
.114
.118
.118
.007
-
10
01
c
(L1)
L
A
0.08
3.00
3.00
4.90 BSC
0.50 BSC
.122
.122
2.90
2.90
.011 0.17
3.10
3.10
0.27
-
REFERENCE JEDEC STD MO-187, VARIATION BA.4.
DIM
ccc
A1
e
bbb
aaa
01
L1
N
L
D
E1
E
A2
b c
A
MILLIMETERS
NOM
INCHES
DIMENSIONS
MIN NOM MAX MIN MAX
E
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
P
(C)
X
Z
G
Y
.063 .224
.011
.020
.098
(.161)
5.70
1.60
0.30
0.50
2.50
(4.10)
MILLIMETERS
DIMENSIONS
DIM INCHES
Y Z
G P X
C
Land Pattern - MSOP-10
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