Datasheet SC1189 Datasheet (SEMTECH)

查询SC1189供应商

3

 2004 Semtech Corp.

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SC1189

Electrical Characteristics (Cont.)

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noitalugeReniL 3.0%

ecnadepmItuptuOV5.6=ETAGV15.1kΩ

tuokcoLegatlovrednUVODL 5.60.801V

dlohserhTNEODL 3.19.1V

tnerruCkniSNEODLV3.3=NEODL

V0=NEODL

10.0
002-

0.1
003-

Aµ
Aµ

egatloVpirTtnerrucrevOtnioptesoVfo%020406%

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V0=TSB+CCV

08003057kΩ

ecnadepmIESNESOV 01kΩ

Unless specified: VCC = 4.75V to 5.25V; GND = P

GND

= 0V; V

OSENSE

= VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C

Notes:

(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) See Gate Resistor Selection recommendations.

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SC1189

Pin Configuration

Ordering Information

Pin Descriptions

Note:

(1) Only available in tape and reel packaging. A reel
contains 1000 devices.

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42SODL2ODLroftupnIesneS

5CCVegatloVtupnI

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7NEODL.rotinoMylppuSODL

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9+SC)evitisop(tupnIesneStnerruC

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41LTSBrevirDediSwoLrofylppuS

51HTSBrevirDediShgiHrofylppuS

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)1(

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71ESNESOV.niahckcabdeeflanretnifodnepoT

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)1(

)BSM(tupnIgnimmargorP

912DIV

)1(

tupnIgnimmargorP

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)1(

tupnIgnimmargorP

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)1(

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422ETAG2ODLtuptuOevirDetaG

1

2

3

4

5

6

7

8

GATE2AGND

TOP VIEW

(24 Pin SOIC)

13

14

15

16

LDOVGATE1

VID0

LDOS1

VID1

LDOS2

VID2

VCC

VID3

PWRGD

VID25MV

LDOEN

VOSENSECS-

9

10

22

ENCS+

BSTHPGNDH

21

18

17

19

20

11

12

24

BSTLDH

DLPGNDL

23

Note:

(1) All logic level inputs and outputs are open collector TTL compatible.

5

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SC1189

Block Diagram

ERROR
AMP

1.25V FET
CONTROLLER

+

-

CURRENT
LIMIT

OSCILLATOR

70mV

REF

GATE1

VOSENSE

VID2

REF

LDOEN

PWRGD

VID3

VID1

LEVEL SHIFT AND
HIGH SIDE DRIVE

OPEN
COLLECTORS

VID25MV

R

S

Q

+

-

VID0

+

-

+

-

SHOOT-THRU
CONTROL

AGND

2.5V FET
CONTROLLER

D/A

SYNCHRONOUS
MOSFET DRIVE

+

-

LDOS1

CS+ ENCS-VCC

LDOS2GATE2LDOV AGND

PGNDH

BSTH

DL

PGNDL

BSTL

DH

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SC1189

Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C

Applications Information - Output Voltage Table

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10010950.1570.1190.1

01100480.1001.1711.1

11100801.1521.1241.1

00100331.1051.1761.1

10100751.1571.1391.1

01000281.1002.1812.1

11000702.1522.1342.1

00000132.1052.1962.1

10000652.1572.1492.1

01111182.1003.1023.1

11111503.1523.1543.1

00111033.1053.1073.1

10111453.1573.1693.1

01011973.1004.1124.1

11011404.1524.1644.1

00011824.1054.1274.1

10011354.1574.1794.1

01101874.1005.1325.1

11101205.1525.1845.1

00101725.1055.1375.1

10101155.1575.1995.1

01001485.1006.1616.1

11001906.1526.1146.1

00001436.1056.1766.1

10001856.1576.1296.1

01110386.1007.1717.1

11110807.1527.1247.1

00110337.1057.1867.1

10110757.1577.1397.1

01010287.1008.1818.1

11010897.1528.1258.1

Note 1: VID[3:0] correspond to legacy VRM8.4 voltage levels for 1.3V to 1.8V

7

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SC1189

Careful attention to layout requirements are necessary for
successful implementation of the SC1189 PWM control­ler. High currents switching at 200kHz are present in the
application and their effect on ground plane voltage differ­entials must be understood and minimized.

1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot­tom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast

Layout Guidelines

transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini­mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.

3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re­gion. It should be as short as practical. Since this connec­tion has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the out­put inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transi­tions in this connection and length is not so important,
however adding unnecessary impedance will reduce effi­ciency.

Vout

12V IN

3.3V Vo Lin1

Vo Lin2

5V

L

5mOhm

+

Cout

+

Cin

10

Q2

0.1uF

Q3

+

Cout Lin1

2.32k

Q4

+

Cout Lin2

1.00k

+

Cin Lin

SC1189

AGND

1

VCC

5

PWRGD

6

LDOEN

7

CS-

8

CS+

9

PGNDH

10

DH

11

BSTH

15

EN

16

VOSENSE

17

VID25MV

18

VID3

19

VID2

20

VID1

21

VID0

22

DL

13

PGNDL

12

BSTL

14

GATE2

24

GATE1

2

LDOV

23

LDOS1

3

LDOS2

4 Q1

0.1uF

Heavy lines indicate

high current paths.

Layout Diagram
SC1189

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SC1189

Layout Guidelines (Cont.)

4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between Cout
and the load must be short, wide copper areas to mini­mize inductance and resistance.

5) The SC1189 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. PGNDH and PGNDL should be returned to
the ground plane close to the package. The AGND pin
should be connected to the ground side of (one of) the
output capacitor(s). If this is not possible, the AGND pin
may be connected to the ground path between the Output
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum­stances should AGND be returned to a ground inside the

Cin, Q1, Q2 loop.

6) Vcc for the SC1189 should be supplied from the 5V

supply through a 10Ω resistor, the Vcc pin should be
decoupled directly to AGND by a 0.1µF ceramic capacitor,

trace lengths should be as short as possible.

7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces run­ning back to CS+ and CS- on the SC1189 should run par-

allel and close to each other. The 0.1µF capacitor should

be mounted as close to the CS+ and CS- pins as possible.

8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).

Vout

5V

+

+

Currents in Power Section

9

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SC1189

Component Selection

SS

SS

S

WITWIT

WITWIT

WIT

CHING SECTIONCHING SECTION

CHING SECTIONCHING SECTION

CHING SECTION

OUTPUT CAPOUTPUT CAP

OUTPUT CAPOUTPUT CAP

OUTPUT CAP

AA

AA

A

CITCIT

CITCIT

CIT

ORSORS

ORSORS

ORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:

step current Transient I

excursion voltage transient MaximumV

Where

I

V

R

t

t

t

t

ESR

=

=

≤

For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than

10mΩ. To meet this kind of ESR level, there are three

available capacitor technologies.

ygolonhceT

.paChcaE

.ytQ

.dqR

latoT

C

(µ )F

RSE

m( Ω)

C

(µ )F

RSE

m( Ω)

mulatnaTRSEwoL033066000201

NOC-SO0335230993.8

munimulARSEwoL005144500573.8

The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.

INDUCTORINDUCTOR

INDUCTORINDUCTOR

INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in­ductor can be calculated. Too large an inductor will pro­duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current
for longer - leading to an output voltage sag below the
ESR excursion calculated above.
The maximum inductor value may be calculated from:

()

OINOA

A

t

ESR

VV or V of lesser the is V where

V

I

CR

L

−

⋅≤

The calculated maximum inductor value assumes 100%

and 0% duty cycle capability, so some allowance must be
made. Choosing an inductor value of 50 to 75% of the
calculated maximum will guarantee that the inductor cur­rent will ramp fast enough to reduce the voltage dropped
across the ESR at a faster rate than the capacitor sags,
hence ensuring a good recovery from transient with no
additional excursions.
We must also be concerned with ripple current in the out­put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:

OSC

IN

L

fL4

V

I

RIPPLE

⋅⋅

=

Ripple current allowance will define the minimum permit­ted inductor value.

POPO

POPO

PO

WER FETSWER FETS

WER FETSWER FETS

WER FETS - The FETs are chosen based on several
criteria, with probably the most important being power
dissipation and power handling capability.
TT

TT

T

OP FETOP FET

OP FETOP FET

OP FET - The power dissipation in the top FET is a combi­nation of conduction losses, switching losses and bottom
FET body diode recovery losses.

a) Conduction losses are simply calculated as:

IN

O

)on(DS

2
OCOND

V

V

cycle duty =

where

RIP

≈δ

δ⋅⋅=

b) Switching losses can be estimated by assuming a switch­ing time, if we assume 100ns then:

2

INOSW

10VIP

−

⋅⋅=

or more generally,

4

f)tt(VI

P

OSCfrINO

SW

⋅+⋅⋅

=

c) Body diode recovery losses are more difficult to esti­mate, but to a first approximation, it is reasonable to as­sume that the stored charge on the bottom FET body di­ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:

OSCINRRRR

fVQP ⋅⋅=

To a first order approximation, it is convenient to only con-

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SC1189

Component Selection (Cont.)

sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp R

DS(ON)

to allow for temperature rise.

epytTEFR

)no(SD

m( Ω)P

D

)W(egakcaP

52043LRI5196.1D

2

kaP

3022LRI5.0191.1D

2

kaP

0144iS0262.28-0S

BOBO

BOBO

BO

TTTT

TTTT

TT

OM FETOM FET

OM FETOM FET

OM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:

)1(RIP

)on(DS

2
OCOND

δ−⋅⋅=

For the example above:

epytTEFR

)no(SD

m( Ω)P

D

)W(egakcaP

52043LRI5133.1D

2

kaP

3022LRI5.0139.0D

2

kaP

0144iS0277.18-0S

Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40oC/W for the D2PAK and 80oC/W for the
SO-8 are readily achievable. The corresponding tempera­ture rise is detailed below:

(esiRerutarepmeT

O

)C

epytTEFTEFpoTTEFmottoB

52043LRI6.762.35

3022LRI6.742.73

0144iS8.0816.141

It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.

INPUT CAPINPUT CAP

INPUT CAPINPUT CAP

INPUT CAP

AA

AA

A

CITCIT

CITCIT

CIT

ORSORS

ORSORS

ORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra
output capacitance or, more usually, additional input ca­pacitors. Choosing low ESR input capacitors will help maxi­mize ripple rating for a given size.

GG

GG

G

AA

AA

A

TE RESISTE RESIS

TE RESISTE RESIS

TE RESIS

TT

TT

T

OR SELECTIONOR SELECTION

OR SELECTIONOR SELECTION

OR SELECTION - The gate resistors for the
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be deter­mined in the application, with the final layout and FETs.

CURRENT SENSE, LIMITCURRENT SENSE, LIMIT

CURRENT SENSE, LIMITCURRENT SENSE, LIMIT

CURRENT SENSE, LIMIT

, DR, DR

, DR, DR

, DR

OOP AND OFFSETOOP AND OFFSET

OOP AND OFFSETOOP AND OFFSET

OOP AND OFFSET
The converter is protected and it’s loadline shaped by the
signals generated from the sense resistor and associated
components.

















INDUCTOR

Ra Rb

Rload

Rc

+

VOSENSE

Io

Vo

V

CS

DROOP
AND
OFFSET
CIRCUIT

CURRENT LIMIT CIRCUIT

R

S

R

D

R

F

Current Limit, Droop and Offset circuit

Current Limit is given by
I

OLIM

= VCS.(RD+RF)/(RS.RF)

At no load the output voltage is given by:
VO=V

O(nom)

*(1+(Ra.Rb)/(Rc*(Ra+Rb))
so the offset is:
VOS=V

O(nom)

*1000*(Ra.Rb)/(Rc*(Ra+Rb))
and the droop is calculated as:
VD=Io*RS*Rb/(Ra+Rb)
where R

S

is in mΩ, V

OS

and VD in mV
For a full design procedure for droop and offset, see Appli­cation Note AN97-9, “Using Droop and Vout Offset for im­proved transient response”.

11

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SC1189

FOLDBACK CURRENT LIMITING

The SC1189 implements a “Hard Current Limit”
overcurrent protection for the switching supply output. In
a short circuit condition, this will lead to higher than nor­mal power dissipation in the bottom side FETs. If this is
problematic, foldback current limiting can be easily and
inexpensively implemented to drastically reduce dissipa­tion during output short circuit

Output Current Path

D1

1N4148

To CS+

To CS-

L1

V

CS

V

O

V

IN

R

A

R

B

R

C

R

D R

F

R

S

Foldback current limit components

0

1

01

V

OUT

Breakpoi nt

I

OLIM

I

OS

V

B

Foldback current limit characteristics

For a complete design procedure for foldback current lim­iting see Application Note AN01-2, “Foldback Current
Limit”. An abbreviated procedure is given below.

1) Choose values for I

OLIM

and RS and calculate the ratio

SO

CS

FD

F

RI

V

RR

R

LIM

⋅

=

+

If this ratio > 1, the value of RS or I

OLIM

must be increased.

Then let RF=1kW and calculate RD.

2) Choose a short circuit current (IOS) and calculate M, do
not be too agressive with M, a value between 2 and 3
should be sufficient. Choosing too low a value for IOS will
result in a high value for M and may cause startup prob­lems due to insufficient current.

OS

OLIM

I

I

M =

3) Choose VB and calculate R

B

)RR(V)1M(

RRVM

R

FDCS

FDB

B

+−

⋅⋅⋅

=

4) Calculate the ratio of the input divider

0.6V)( diode of drop Voltage ForwardV where

V

VVV

)RR(

R

F

IN

FCSB

CA

C

≈=

++

=

+

Choose RC<RB/10 and calculate R

A

SHORSHOR

SHORSHOR

SHOR

T CIRT CIR

T CIRT CIR

T CIR

CUIT PRCUIT PR

CUIT PRCUIT PR

CUIT PR

OO

OO

O

TECTION - LINEARSTECTION - LINEARS

TECTION - LINEARSTECTION - LINEARS

TECTION - LINEARS
The Short circuit feature on the linear controllers is imple­mented by using the Rds(on) of the FETs. As output cur­rent increases, the regulation loop maintains the output
voltage by turning the FET on more and more. Eventually,
as the Rds(on) limit is reached, the FET will be unably to
turn on more fully, and output voltage will start to fall.
When the output voltage falls to approximately 50% of
nominal, the LDO controller is latched off, setting output
voltage to 0. Power must be cycled to reset the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially dis­abled. It is enabled at a preset time (nominally 2mS) after
both the LDOV and LDOEN rails rise above their lockout
points.
To be most effective, the linear FET Rds(on) should not be
selected artificially low, the FET should be chosen so that,
at maximum required current, it is almost fully turned on.
If, for example, a linear supply of 1.5V at 4A is required
from a 3.3V ± 5% rail, max allowable Rds(on) would be.

Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ
To allow for temperature effects 200mΩ would be a suit-

able room temperature maximum, allowing a peak short
circuit current of approximately 15A for a short time be­fore shutdown.

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SC1189

Theory of Operation (Linear OCP)

The Linear controllers in the SC1189 have built in
Overcurrent Protection (OCP). An overcurrent is assumed
to have occured when the external FET is turned fully on
and the output currrent is R

DS(ON)

limited, this is detected
by the gate voltage going very high while the output volt­age is below approximately 40% of it’s setpoint. To allow
for capacitor charging and very short overcurrent dura­tions, the gate voltage is ramped very slowly upwards when­ever the output voltage is below the OCP threshold. To
guarantee that the LDO output voltage is capable of reach­ing it’s setpoint, the gate drive is disabled until both LDOV
Undervoltage Lockout (UVLO) and LDOEN Threshold val­ues are exceeded, ensuring that there is sufficient gate
drive capability and sufficient LDO input voltage capabil­ity. A block diagram of one LDO controller is shown below.

+

­gm

+

-

LDOV

1.3V

LDOV-0.7V

10nA

LDOSx

+

-

12V

RESET BY
LDOV LOW

VREF

10pF

R

S

Q

14uA

1.26V

+

-

GATEx

R

+

-

R1

R

+

AGND

LDOEN

LDOV

Vout

3.3V

R2

SWITCH CLOSED
ON LOW

C

RAMP

S1

During a normal start-up, once LDOV and LDOEN have
reached their thresholds, the GATEx pin is released and
C

RAMP

is charged by 10nA causing the GATEx voltage to
ramp at 10nA/10pF = 1V/ms. Once the GATEx output has
ramped to the external FET threshold, Vout starts to ramp
up, following GATEx. When Vout reaches the OCP thresh­old, approximately 40% of setpoint, switch S1 is closed
and GATEx ramps up at a much faster rate, followed by
Vout, until Vout reaches setpoint and the loop settles into
steady state regulation.

1V/ms

Gate

Vout

Vout/2

1.4V/us

Time

Startup with no short circuit

If at some later time, a short circuit is applied to the out­put, the GATEx voltage will ramp up quickly as Vout falls to
try and maintain regulation. Once Vout has fallen to the
OCP threshold, switch S1 will open and the gate will con­tinue ramping at the 1V/ms rate. If the short is not re­moved before the GATEx output reaches approximately
LDOV - 0.7V, the GATEx pin will be latched low, disabling
the LDO

1V/ms

Gate

LDOV-0.7V

Vout/2

Vout

Short

applied

Time

Short circuit after startup

If the LDO tries to start into a short, the gate ramps at the
1V/ms rate to LDOV - 0.7V, where the GATEx pin will be
latched low.

1V/ms

Gate

LDOV-0.7V

Time

Startup into short circuit

13

 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

PIN Descriptions

Typical Characteristics

Typical Efficiency (Switching section)

Typical Ripple, Vo=1.75V, Io=10A

2.5V Linear Short circuit output response

Transient Response Vo=1.75V, Io=0A to 28A

Vo=1.25 V

1.50V

1.75V

70%

80%

90%

100%

0 5 10 15 20 25 30

Output Current (A)

Efficiency

14 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

Typical Application Circuit

+

C19

1500uF

R9 2R2

+

C22

1500uF

R1

10

R24

1k

C27

OPEN

VTT

5V

5VSTBY

VID1

1.8V

C46

0.1uF

R6 2R2

J31

+

C32

330uF

R11

See Table 2

C43

22nF

+

C44

330uF

Q8

IRFR120N

J17

CON4

123

4

R15

(Ohm)

EMPTY

5.0

2.5

+

C35

330uF

VOUT

1.050

1.075

1.100

1.125

1.150

C10

0.1uF

AGP

R26

100k

R20

1k

1.25V/1.5V VTT

J26

S2

VOUT

1.450

1.475

1.500

1.525

1.550

+

C11

330uF

D2

1N4148

J18

SCOPE TP

R10 2R2

TABLE VALID FOR 2x5mOhm SENSE

RESISTOR

5VSTBY

+

C18

1500uF

VID

3210

0100

0100

0011

0011

0010

C33

0.1uF

C28

0.1uF

R12

1k

12V

+

C38

330uF

C4

0.1uF

J28

R28

4.99k

+

C16

330uF

J24

+

C20

1500uF

OFFSET

mV/V02

2

VID

25MV0101

0

+

C14

330uF

Q3

IRL2203

VCC_CORE

C40

0.1uF

R29

10k

+

C3

1500uF

R22

390

J14

Clock

R8 5mOhm

R19 5mOhm

L1 1.2uH

VTTSEL

J33

+

C30

330uF

+

C34

330uF

+

C7

1500uF

Q2

IRL3103S

+

C6

1500uF

VID

25MV0101

0

5V

VID

3210

1100

1100

1011

1011

1010

1.175 1.5750010 11 1010

1.200 1.6000001 00 1001

1.225 1.6250001 11 1001

1.250 1.6500000 00 1000

1.275 1.6750000 11 1000

1.300 1.7001111 00 0111

1.325 1.7251111 11 0111

1.350 1.7501110 00 0110

1.375 1.7751110 11 0110

1.400 1.8001101 00 0101

1.425 1.8251101 11 0101

J30

3.3V STBY

C5

0.1uF

+

C36

330uF

Q9

IRFR120N

VTTSEL = 1, VTT = 1.5 V

VTTSEL = 0, VTT = 1.25 V

AGPSEL = 1, AGP=3.3V

AGPSEL = 0, AGP=1.5V

VID3

R25

100k

U2

SC1112CS

3

6

15

12913

14

4

7

2

1

1158

1016

DELAY

ADJGATE

VTTIN

AGPGATE

CAP+

VTTSEN

VTTGATE

VTTSEL

ADJSEN

PWRGD

5VSTBY

AGPSEN

AGPSEL

CAP-

FCGND

+

C21

1500uF

VID0

R5 OPEN

Q1

IRL3103S

+

C15

330uF

R2 10k

U1

SC1189CS

1

567 8

9

10

11

151617

18

19

20

21

22

131214

24 2

23

34

AGND

VCC

PWRGD

LDOEN CS-

CS+

PGNDH

DH

BSTH

EN

VOSENSE

VID4

VID3

VID2

VID1

VID0

DL

PGNDL

BSTL

GATE2 GATE1

LDOV

LDOS1LDOS2

+

C12

330uF

C29

10uF

C1

0.1uF

Q5 IRLR024N

R3

EMPTY

C41

0.1uF

J15

R21

18k

AGPSEL

J32

+

C37

330uF

ON/OFF

1.8V STBY

Q4

IRL2203

C31

0.1uF

R27 1.00k

J13

CHIPSET

R15

See Table 2

VID2

Q10

IRFR120N

C39

0.1uF

C45

1uF

3.3V STBY

VID25MV

+

C9

1500uF

+

C26

47uF

+

C17

330uF

R11

(Ohm)03.3

10

J2

TX M/B MOLEX 39-29-9202

12345678910111213141516171819

20

3.3V

3.3V
COM5VCOM5VCOM

PWR_OK

5VSB

12V

3.3V

-12V
COM

PS_ON

COM

COM

COM

-5V

5V

5V

DROOP

mV/A01

2

2.02 EMPTY5

12.55 8.31

6.35252

55 EMPTY5

25.010 16.71

12.510 502

10.010 EMPTY5

+

C2

1500uF

R23 442

CHIPSET

J27

+

C8

1500uF

+

C23

1500uF

R7 2R2

1.5V/3.3V AGP (2X/4X)

J29

EN

Q6

IRLR024N

D1

1N4148

C42

0.1uF

2.5V

R4 1.00k

VCC_CORE PWRGD

15

 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

Evaluation Board Bill of Materials

metI.ytQecnerefeReulaVsetoN

121

,14C,04C,93C,33C,13C,82C,01C,5C,4C,1C

64C,24C

Fu1.0

221

,12C,02C,91C,81C,9C,8C,7C,6C,3C,2C

32C,22C

Fu0051

roXG-VMoynaSRSEwoL

tnelaviuqe

341

,43C,23C,03C,71C,61C,51C,41C,21C,11C

44C,83C,73C,63C,53C

Fu033

41 62CFu74

61 92CFu01

71 34CFn22

81 54CFu1

92 2D,1D8414N1

011 2JB/MXTA2029-92-93XELOM

61 1LHu2.11S-CCPcinosanaP

72 2Q,1QS3013RLRI

82 4Q,3Q3022LRI

92 6Q,5QN420RLRI

523 01Q,9Q,8QN021RFRI

011 1R01

112 92R,2Rk01

922 72R,4Rk00.1

314 01R,9R,7R,6R2R2

412 91R,8RmhOm51RAOCRI

512 51R,11RelbaTeeS

213 42R,02R,21Rk1

611 12Rk81

711 22R093

631 32R244

732 52R,62Rk001

831 82Rk99.4

811 1USC9811CSHCETMES

141 2USC2111CSHCETMES

16 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1189

Outline Drawing - SO-24

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012-8790

Phone: [phone] FAX [phone]

Contact Information