SEMTECH SC1157 Technical data

查询SC1157供应商

PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

DESCRIPTION

The SC1157 is a low-cost, full featured, synchronous voltage-mode controller designed for use in single ended power supply applications where efficiency is of primary concern. Synchronous operation allows for the elimination of heat sinks in many applications. The SC1157 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium cessor configurations. Internal level-shift, high-side drive circuitry, and preset shoot-thru control, allows for use of inexpensive n-channel power switches.

SC1157 features include an integrated 4-bit V temperature compensated voltage reference, triangle wave oscillator, current limit comparator, frequency shift over-current protection, and an internally compensated error amplifier.

The SC1157 operates at a fixed 140KHz, providing an optimum compromise between efficiency, external component size, and cost.

®

ll (Klamath), in both single and multiple pro-

DAC,

ID

SC1157

FEATURES

•= Low cost / full featured

•= Synchronous operation

•= 4 Bit V

(1% tolerance)

•= Designed to meet Intel VRM8.2 (Pentium

•= 1.5% Reference

APPLICATIONS

•= Pentium® II Core Supply

•= Multiple Microprocessor Supplies

•= Voltage Regulator Modules (VRM)

•= Programmable Power Supplies

•= High Efficiency DC/DC Conversion

ORDERING INFORMATION

DEVICE

SC1157CS.TR SO-16NB 0 - 125°C

DAC programmable output

ID

(1)

PACKAGE

(2)

TEMP. RANGE (TJ)

®

II)

PIN CONFIGURATION

Top View

(16-Pin SOIC)

REF

VID3 VID2

VID1 VID0

VOSENSE

GND

Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) “NB” indicates 150 MIL body.

BLOCK DIAGRAM

VCC CS-

CURRENT

REF

D/A

+

-

ERROR AMP

OSCILLATOR

70mV

LIMIT

+

-

+

SHUTDOWNCS+

BSTH

LEVEL SHIFT AND HIGH SIDE DRIVE

R

Q

S

SHOOT-THRU CONTROL

SYNCHRONOUS MOSFET DRIVE

DH

BSTL

DL

PGND

Pentium is a registered trademark of Intel Corporation

1

PROGRAMMABLE SYNCHRONOUS DC/DC

SC1157

CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

to GND V

V

CC

IN

-0.3 to 7 V PGND to GND ± 1 V BST to GND -0.3 to 15 V Thermal Resistance Junction to Case

Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range

Lead Temperature (Soldering) 10 sec ESD Rating (Human Body Model)

θ

JC

θ

JA

T

A

T

STG

T

LEAD

ESD 1.5 kV

30 °C/W

130 °C/W

0 to 70 °C

-65 to +150 °C 300 °C

ELECTRICAL CHARACTERISTICS

Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage See Table 1. Supply Voltage V Supply Current V Load Regulation I

CC

= 5.0 8 15 mA

CC

= 0.3A to 15A

O

Line Regulation All VID codes Gain (A

)V

OL

OSENSE

to V

(1)

O

4.5 7 V

1%

+ 0.15 %

35 dB Current Limit Voltage 60 70 80 mV Oscillator Frequency 125 140 155 kHz Buffered Reference Voltage

I

REF

≤=1mA

1.25 V Oscillator Max Duty Cycle 90 95 % DH Sink/Source Current BST DL Sink/Source Current BST

- DH = 4.5V, DH - PGNDH = 3V 1 A

H

- DL = 4.5V, DL - PGNDL = 3V 1 A

L

Dead Time 50 100 ns VID Pin Source current VIDx <

2.4V 30 100 uA

NOTE:

(1) Specification refers to application circuit (Figure 1.). (2) This device is ESD sensitive. Use of standard ESD handling precautions is required.

2

PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

PIN DESCRIPTION

Pin # Pin Name Pin Function

1 GND Small Signal Analog and Digital Ground 2 REF Buffered Reference output

SC1157

3V

CC

Chip Supply Voltage 4 CS(-) Current Sense Input (negative) 5 CS(+) Current Sense Input (positive) 6 PGND Power Ground for High and Low Side Drivers

7 DH High Side Driver Output 8 DL Low Side Driver Output 9 BSTL Vcc for Low Side Driver (Boost)

10 BSTH Vcc for High Side Driver (Boost) 11 SHUTDOWN Logic Low shuts down the converter; High or open for normal operation. 12 VOSENSE Top end of internal feedback chain 13 VID3 14 VID2 15 VID1 16 VID0

(1)

Programming Input (MSB)

Programming Input

Programming Input (LSB)

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

PIN CONFIGURATION

3

PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

OUTPUT VOLTAGE TABLE

Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV;

= 0°C to 85°C

T

J

PARAMETER CONDITIONS VID

3210

1101 1.386 1.400 1.414 1100 1.436 1.450 1.465 1011 1.485 1.500 1.515 1010 1.535 1.550 1.566 1001 1.584 1.600 1.616 1000 1.634 1.650 1.667 0111 1.683 1.700 1.717 0110 1.733 1.750 1.768 0101 1.782 1.800 1.818 0100 1.832 1.850 1.869 0011 1.881 1.900 1.919 0010 1.931 1.950 1.970 0001 1.980 2.000 2.020 0000 2.030 2.050 2.070

Output Voltage

(1)

IO = 2A in Application Circuit 1111 1.287 1.300 1.313 V (Figure 1) 1110 1.337 1.350 1.364

MIN TYP MAX UNITS

SC1157

NOTE:

(1) All VID codes not specifically listed are invalid and cause shutdown exactly as if the shutdown pin had been asserted.

THEORY OF OPERATION

The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 100 kHz. The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has turned off, and visa-versa. The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an overcurrent condition. The latch is reset at the start of each oscillator period.

4

Preliminary - August 7, 2000

OUTLINE DRAWING SO-16

PROGRAMMABLE SYNCHRONOUS DC/DC CONTROLLER FOR ADVANCED PROCESSORS

Jedec MS-012AC

SC1157

LAND PATTERN SO-16

ECN00-1243

5

SEMTECH SC1157 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual