查询SC1155供应商
PRELIMINARY - August 7, 2000
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
DESCRIPTION
The SC1155 is a synchronous-buck switch-mode controller designed for use in single ended power supply
applications where efficiency is the primary concern.
The controller is a hysteretic type, with a user selectable hysteresis. The SC1155 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium
®
llI and Athlon®, in both
single and multiple processor configurations. Inhibit,
under-voltage lockout and soft-start functions are included for controlled power-up.
SC1155 features include an integrated 5 bit D/A converter, temperature compensated voltage reference,
current limit comparator, over-current protection, and
an adaptive deadtime circuit to prevent shoot-through
of the power MOSFET during switching transitions.
Power good signaling, logic compatible shutdown, and
over-voltage protection are also provided. The integrated D/A converter provides pr ogrammability of output voltage from 1.1V to 1.85V in 25mV increments.
The SC1155 high side driver can be configured as
either a grounded reference or as a floating bootstrap
driver. The high and low side MOSF ET drivers have a
peak current rating of 2 amps.
TYPICAL APPLICATION CIRCUIT
FEATURES
•= Programmable hysteresis
•= 5 bit DAC programmable output (1.1V-1.85V)
•= On-chip power good and OVP functions
•= Designed to meet latest Intel specifications
•= Up to 95% efficiency
•= + 1% voltage tolerance over temperature
APPLICATIONS
•= Server Systems and Workstations
•= Intel Pentium
•= AMD Athlon
®
III Core Supplies
®
Core Supplies
•= Multiple Microprocessor Supplies
•= Voltage Regulator Modules
ORDERING INFORMATION
DEVICE
SC1155CSW.TR SO-28 0 - 125°C
SC1155EVB Evaluation Board
Note:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices.
(1)
PACKAGE TEMP. RANGE (TJ)
U1
SC1155CSW
1
IOUT
R3
2.7kR12k
C3
R41kR2
0.01
1k
C2
0.01
C4
0.01
R5
100
R6
20k
C5
0.001
C7
0.1
C8
0.01
R8
10k
2
DROOP
3
OCP
4
VHYST
5
VREFB
C6
0.1
6
VSENSE
7
AGND
8
SOFTST
9
+5V
N/C
10
LODRV
11
LOHIB
12
DRVGND
13
LOWDR
14
DRV
C8
2.2uF
R7
150
PWRGD
VID0
VID1
VID2
VID3
VID4
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
VIN12V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+12V
C9
2.2uF
R9
10k
+5V
R10
10k
C12
0.33
Q1
R11
IRL3103S
2.2
C13
0.33
Q2
IRL2203S
R12
3.9
PWRGD
C16
0.1
INHIB
L2
1.5uH
C17-C19
150uF/16V
L1
1uH
C21-C26
150uF/4V
Vin
C20
0.1
Vin +5 to +12V
GND
Vout
C27
0.1
Vout = 1.1 to 1.85V
GND
Athlon is a registered trademark of AMD Corporation
Pentium is a registered trademark of Intel Corporation
1
© 2000 SEMTECH CORP.
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Maximum Units
VIN12V VIN
MAX
14 V
BOOT to DRVGND 25 V
BOOT to BOOTLO 15 V
Digital Inputs -0.3 to +7.3 V
AGND to DRVGND +
0.5V V
LOHIB to AGND 14 V
LOSENSE to AGND 14 V
IOUTLO to AGND 14 V
HISENSE to AGND 14 V
VSENSE to AGND 5V
Continuous Power Dissipation, T
Continuous Power Dissipation, T
Operating Junction Temperature T
Lead Temperature (Soldering) 10 seconds T
Storage Temperature T
PIN CONFIGURATION
= 25°C P
A
= 25°C P
C
SIMPLIFIED BLOCK DIAGRAM
D
D
J
L
STG
1.2 W
6.25 W
0 to +125 °C
300 °C
-65 to 150 °C
Top View
(28-Pin SOIC)
2
© 2000 SEMTECH CORP.
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
PIN DESCRIPTION
Pin Pin Name Pin Function
1 IOUT Current Out. The output voltage on this pin is proportional to the load current as measured
x I
across the high side MOSFET, and is approximately equal to 2 x R
DS(ON)
2 DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a
function of load current. The voltage is set by a resistor divider between IOUT and AGND.
3 OCP Over Current Protection. This pin is used to set the trip point for over current protection by a
resistor divider between IOUT and AGND.
4 VHYST Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor
divider between VREFB and AGND.
5 VREFB Buffered Reference Voltage (from VID circuitry).
6 VSENSE Output Voltage Sense.
7 AGND Small Signal Analog and Digital Ground.
8 SOFTST Soft Start. Connecting a capacitor from this pin to AGND sets the time delay.
LOAD
.
9 NC Not connected
10 LODRV Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is
grounded, this pin can be used to control LOWDR.
11 LOHIB Low Side Inhibit. This pin is used to eliminate shoot-thru current.
12 DRVGND Power Ground. Insure output capacitor ground is connected to this pin.
13 LOWDR Low Side Driver Output. Connect to gate of low side MOSFET.
14 DRV Drive Regulator for the MOSFET Drivers.
15 VIN12V 12V Supply. Connect to 12V power rail.
16 BOOT Bootstrap. This pin is used to generate a floating drive for the high side FET driver.
17 HIGHDR High Side Driver Output. Connect to gate of high side MOSFET.
18 BOOTLO Bootstrap Low. In desktop applications, this pin connects to DRVGND.
19 HISENSE High Current Sense. Connected to the drain of the high side FET, or the input side of a current
sense resistor between the input and the high side FET.
20 LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current
sense resistor between the input and the high side FET.
21 IOUTLO This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin
when the high side FET is on.
22 INHIBIT Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V
through a pull-up resistor.
23 VID4
24 VID3
25 VID2
26 VID1
27 VID0
28 PWRGD
(1)
Programming Input (MSB).
(1)
Programming Input.
(1)
Programming Input.
(1)
Programming Input.
(1)
Programming Input (LSB).
(1)
Power Good. This open collector logic output is high if the output voltage is within 5% of the set
point.
© 2000 SEMTECH CORP.
3
PRELIMINARY - August 7, 2000
ELECTRICAL CHARACTERISTICS
Unless specified: 0 < TJ < 125°C, VIN = 12V
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
PARAMETER SYMBO
CONDITIONS MIN TYP MAX UNITS
L
Supply Voltage Range VIN12V 11.4 12 13 V
Supply Current (Quiescent) I
q INH = 5V, VID not 11111,
IN
15 mA
VIN above UVLO threshold during start-up,
= 200kHz, BOOTLO = 0V,
f
SW
= CDL = 50pF
C
DH
High Side Driver Supply
Current (Quiescent)
q INH = 0V or VID = 11111 or VIN below
I
BOOT
UVLO threshold during start-up,
10 µA
BOOT = 13V, BOOTLO = 0V
INH = 5V, VID not 11111, VIN
5mA
above UVLO threshold during start-up,
= 200kHz, BOOT = 13V, BOOTLO = 0V,
f
SW
= 50pF
C
DH
REFERENCE/VOLTAGE IDENTIFICATION
Reference Voltage Accuracy V
REF
11.4V < VIN12V < 12.6V, over full VID
-1 1 %
range (see Output Voltage Table)
VID0 - VID4 High Threshold
V
TH(H)
2.25 V
Voltage
VID0 - VID4 Low Threshold
V
TH(L)
1V
Voltage
POWER GOOD
Undervoltage Threshold V
Output Saturation Voltage V
Hysteresis V
TH(PWRGD)
SAT
HYS(PWRG
D)
OVER VOLTAGE PROTECTION
OVP Trip Point V
Hysteresis
(1)
V
HYS(OVP)
OVP
SOFT START
Charge Current I
CHG
Discharge Current Idischg V
INHIBIT COMPARATOR
Start Threshold Vstart
INH
VIN12V UVLO
Start Threshold Vstart
Hysteresis Vhys
UVLO
UVLO
90 95 % V
IO = 5mA 0.5 V
10 mV
38 42 46 %V
10 mV
VSS = 0.5V, resistance from VREFB pin to
AGND = 20kΩ, V
Note: I
(S/S)
= (I
CHG
VREFB
= 1V 1 mA
REFB
/ 5)
= 1.3V
10.4 13 15.6 µA
12.02.4 V
9.25 10 10.75 V
1.8 2 2.2 V
REF
OUT
© 2000 SEMTECH CORP.
4
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125°C, VIN = 12V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HYSTERETIC COMPARATOR
Input Offset Voltage Vos
Input Bias Current Ibias
Hysteresis Accuracy V
HYS_ACC
Hysteresis Setting V
HYSCMPVDROOP
HYSCMP
HYS_SET
pin grounded 5 mV
1µA
7mV
60 mV
DROOP COMPENSATION
Initial Accuracy V
DROOP_ACCVDROOP
= 50mV 5 mV
OVERCURRENT PROTECTION
OCP Trip Point V
Input Bias Current Ibias
OCP
OCP
0.09 0.1 0.11 V
100 nA
HIGH-SIDE VDS SENSING
Gain 2V/V
Initial Accuracy V
IOUT_ACC
IOUT Source Isource
IOUT Sink Current Isink
IOUT Voltage Swing V
VIOUT Voltage Swing V
VIOUT Voltage Swing V
LOSENSE High Level Input Voltage Vih
LOSENSE Low Level Input Voltage Vil
Sample/Hold Resistance R
IOUT (IN)
IOUT(4,5V)VHISENSE
IOUT(3V)
LOSENSEVHISENSE
LOSENSEVHISENSE
S/H
V
IOUTVIOUT
V
V
IOUT
V
V
R
R
V
4.5V ≤ = 13V
= 12V, V
HISENSE
= 0.5V, V
= 11.5V
IOUTLO
= 0.05V, V
IOUT
= 12V
IOUTLO
HISENSE
= 10k0hm
IOUT
= 10kOhm
IOUT
= 3V, R
HISENSE
HISENSE
= 11V,
= 4.5V,
= 11.9V 6 mV
IOUTLO
500 µA
40 50 µA
HISENSE
= 12V,
= 12V,
03.75V
02.0V
= 10kOhm 0 1.0 V
IOUT
= 4.5V (Note 1) 2.85 V
= 4.5V (Note 1) 1.8 V
50 65 80
Ω
BUFFERED REFERENCE
VREFB Load Regulation Vldreg
DEADTIME CIRCUIT
LOHIB High Level Voltage Vih
LOHIB Low Level Input Voltage Vil
LOWDR High Level Input Voltage Vih
LOWDR Low Level Input Voltage Vil
LOHIB
LOHIB
LOWDR
LOWDR
© 2000 SEMTECH CORP.
REFB
10µA < I
< 500µA 2 mV
REFB
2V
(Note 1) 2 V
(Note 1) 1.0 V
1.0 V
5
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125°C, VIN12V = 12V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRIVE REGULATOR
DRV Voltage V
DRV
Load Regulation Vldreg
Short Circuit Current Ishort
HIGH-SIDE OUTPUT DRIVER
Peak Output Current Isrc
Output Resistance Rsrc
Isink
HIGHDR’
HIGHDR
HIGHDR’
Rsink
LOW-SIDE OUTPUT DRIVER
Peak Output Current Isrc
Output Resistance Rsrc
Isink
LOWDR’
LOWDR
LOWDR’
Rsink
DRV
DRV
HIGHDR
LOWDR
11.4 < VIN12V < 12.6V,
= 50mA
I
DRV
1mA < I
< 50mA 100 mV
DRV
duty cycle < 2%, tpw < 100us,
T
= 125°C
J
- V
V
BOOT
1.5V (src), or V
BOOTLO
= 6.5V, V
= 5V (sink)
HIGHDR
HIGHDR
(Note 1)
TJ = 125°C
V
BOOT
V
HIGHDR
- V
= 6V
BOOTLO
= 6.5V,
TJ = 125°C
V
BOOT
V
HIGHDR
- V
= 0.5V
BOOTLO
= 6.5V,
duty cycle < 2%, tpw < 100us,
= 125°C
T
J
V
DRV
or V
= 6.5V, V
= 5V (sink) (Note 1)
LOWDR
= 1.5V (src),
LOWDR
TJ = 125°C
V
DRV
= 6.5V, V
LOWDR
= 6V
TJ = 125°C
V
DRV
= 6.5V, V
LOWDR
= 0.5V
=
79V
100 mA
2
A
45
Ω
5
2
A
45
Ω
5
© 2000 SEMTECH CORP.
6
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
DYNAMIC ELECTRICAL CHARACTERISTICS
Unless specified: 0 < T
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HYSTERETIC COMPARATORS
125°C, VIN12V = 12V
J <
(1)
Propagation Delay Time
from
VSENSE to HIGHDR or
LOWDR (excluding
deadtime)
OUTPUT DRIVERS
(2)
HIGHDR rise/fall time tr
LOWDR rise/fall time tr
OVERCURRENT PROTECTION
Comparator Propagation
Delay Time
Deglitch Time (Includes
comparator propagation
delay time)
OVERVOLTAGE PROTECTION
(1)
Comparator Propagation
Delay Time
Deglitch Time (Includes
comparator propagation
delay time)
HIGH-SIDE Vds SENSING
(1)
t
HCPROP
HIGHDR
,tfHIGHDR
LOWDR ,
tf
LOWDR
(1)
t
OCPROP
t
OCDGL
t
OVPROP
t
OVDGL
10mV overdrive,
Vref < 3.5V
1.3V <
Cl = 9nF, V
V
BOOTLO
= 125 °C
T
J
Cl = 9nF, V
= 125 °C
T
J
BOOT
= grounded,
DRV
= 6.5v,
= 6.5v,
150 250 ns
60 ns
60 ns
1µs
25µs
1µs
25µs
Response Time t
Short Circuit Protection
Rising Edge Delay
Sample/Hold Switch turnon/turn-off Delay
© 2000 SEMTECH CORP.
VDSRESP
t
VDSRED
t
SWXDLY
V
HISENSE
= 12v, V
IOUTLO
pulsed
2µs
from 12v to 11.9v, 100ns rise
and fall times
V
HISENSE
= 4.5v, V
IOUTLO
pulsed
3µs
from 4.5v to 4.4v, 100ns rise
and fall times
V
HISENSE
= 3v, V
IOUTLO
pulsed
3µs
from 3.0v to 2.9v, 100ns rise
and fall times
LOSENSE grounded 300 500 ns
3v < V
V
LOSENSE
HISENSE
= V
< 11v
HISENSE
30 100 ns
7
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
DYNAMIC ELECTRICAL CHARACTERISTICS (cont.)
Unless specified: 0 < TJ < 125° C, VIN12V = 12V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE Vds SENSING (Cont.)
POWER GOOD
(1)
(1)
Comparator Propagation
t
PWRGD
Delay
SOFTSTART
Comparator Propagation
(1)
t
SLST
overdrive = 10mv 560 900 ns
Delay
DEADTIME
Driver Nonoverlap Time t
(2)
NOL
C
= 9nF, 10% threshold
LOWDR
30 100 ns
on LOWDR
LODRV
Propagation Delay t
(1)
LODRVDLY
Notes
(1) Guaranteed, but not tested.
(2) Test circuit and timing diagram.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
TEST CIRCUIT
TIMING DIAGRAM
1µs
400 ns
© 2000 SEMTECH CORP.
8
PRELIMINARY - August 7, 2000
TYPICAL PERFORMANCE CURVES
5V Efficiency
95%
93%
91%
89%
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155 Effiency, 5Vin
SC1155
5V Regulation
Effiency
87%
85%
83%
81%
79%
77%
75%
0 2 4 6 8 10 12 14 16 18 20
Current, A
SC1155 Voltage Regulation, 5Vin
3%
2%
1.85Vout
1.50Vout
1.10Vout
1%
0%
Regulation
-1%
-2%
-3%
0 2 4 6 8 101214161820
© 2000 SEMTECH CORP.
1.85Vout
1.50Vout
1.10Vout
Current, A
9
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
TYPICAL PERFORMANCE CURVES (Cont.)
12V Efficiency
SC1155 Effiency, 12Vin
95%
93%
91%
89%
SC1155
12V Regulation
Effiency
87%
85%
83%
81%
79%
77%
75%
0 2 4 6 8 10 12 14 16 18 20
Current, A
SC1155 Voltage Regulation, 12Vin
3%
2%
1.85Vout
1.50Vout
1.10Vout
1%
0%
Regulation
-1%
-2%
-3%
© 2000 SEMTECH CORP.
1.85Vout
1.50Vout
1.10Vout
0 2 4 6 8 101214161820
Current, A
10
PRELIMINARY - August 7, 2000
BLOCK DIAGRAM
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
DRV
VIN12V
Vcc
DRIVE
BOOT
REGULATOR
HIGHDR
BOOTLO
LOWDR
DRVGND
LOWDR
PREREG
FILTER
LODRV
SOFTST
ANALOG BIAS
I(VREFB) / 5
VREF
DELAY
RISING EDGE
+
--+
+
--+
+
-
VREFB
VHYST
FILTER
HIGHDR
FILTER
VSENSE LOHIB
LOSENSE
+-
1.15VREF 0.93VREF
SHUTDOWN
IOUTLOHISENSEIOUT
-
+
DROOP
VREF
VID
DAC
VID4
VID3
VID2
VID1
VID0
+
-
+
-
G=2
+
-
11111
DECODE
© 2000 SEMTECH CORP.
50uA
PWRGD
BANDGAP
FAULT
INH
Q
R
S
+
-
0.93VREF
+
-
UVLO
DEGLITCH
DEGLITCH
10V
+
-
+
-
2V
Vcc
+
-
VSENSE
INHIBIT
AGND
OCP
100mV
1.15VREF
11
PRELIMINARY - August 7, 2000
OUTPUT VOLTAGE TABLE
0 = VSS; 1 = OPEN
VID4 VID3 VID2 VID1 VID0 VDC
1 1 1 1 1 Output Off
1 1 1101.1
1 1 1 0 1 1.125
1 1 1 0 0 1.15
1 1 0 1 1 1.175
1 1 0101.2
1 1 0 0 1 1.225
1 1 0 0 0 1.250
1 0 1 1 1 1.275
1 0 1101.3
1 0 1 0 1 1.325
1 0 1 0 0 1.35
1 0 0 1 1 1.375
1 0 0101.4
1 0 0 0 1 1.425
1 0 0 0 0 1.45
0 1 1 1 1 1.475
0 1 1101.5
0 1 1 0 1 1.525
0 1 1 0 0 1.55
0 1 0 1 1 1.575
0 1 0101.6
0 1 0 0 1 1.625
0 1 0 0 0 1.65
0 0 1 1 1 1.675
0 0 1101.7
0 0 1 0 1 1.725
0 0 1 0 0 1.75
0 0 0 1 1 1.775
0 0 0101.8
0 0 0 0 1 1.825
0 0 0 0 0 1.85
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
(V)
NOTE:
(1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, turning both
MOSFETs off, and the controller will be set to a low-Iq state.
© 2000 SEMTECH CORP.
12
PRELIMINARY - August 7, 2000
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
FUNCTIONAL DESCRIPTION
Reference/Voltage Identification
The reference/voltage identif ication (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID
pins are TTL compatable inputs to the VID selection
network. They are internally pulled up to +5V generated from the +12V supply by a resistor divider, and
provide programm ability of output voltage from 1.1V to
1.85V in 25mV increments.
Refer to the Output Voltage Table for the VID code
settings. The output voltage of the VID network, VREF
is within 1% of the nominal setting over the full input
and output voltage range and junction temperature
range. The output of the reference/VID network is
indirectly brought out through a buffer to the REFB pin.
The voltage on this pin will be within 3mV of VREF. It is
not recommended to dr ive loads with REFB other than
setting the hysteresis of the hysteretic comparator,
because the current drawn from REFB sets the charging current for the sof t s tart c apac itor. Ref er to the s of t
start section for additional information.
Hysteretic Comparator
The hysteretic comparator regulates the output voltage
of the synchronous-buck conver ter. The hysteresis is
set by connecting the center point of a resistor divider
from REFB to AGND to the HYST pin. The hysteresis
of the comparator will be equal to twice the voltage
difference between REFB and HYST, and has a m aximum value of 60mV. The maximum propagation delay
from the comparator inputs to the driver outputs is
250ns.
Low Side Driver
The low side driver is designed to drive a low R
N-channel MOSFET, and is rated for 2 amps source
and sink current. The bias for the low side driver is
provided internally from VDRV.
High Side Driver
The high side driver is designed to drive a low R
N-channel MOSFET, and is rated for 2 amps source
and sink current. It can be configured either as a
ground referenced driver or as a floating bootstrap
driver. When configured as a floating driver, the bias
voltage to the driver is developed from the DRV regulator. The internal bootstr ap diode, connected between
DS(ON)
DS(ON)
the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be
applied between the BOOT pin and ground is 25V. The
driver can be referenced to ground by connecting
BOOTLO to PGND, and c onnecting +12V to the BO O T
pin.
Deadtime Control
Deadtime control prevents shoot- through current from
flowing through the main power FET s during switching
transitions by actively controlling the turn-on times of
the FET drivers. T he high side driver is not allowed to
turn on until the gate drive voltage to the low-side FET
is below 2 volts. The low side driver is not allowed to
turn on until the voltage at the junction of the 2 FETs
(VPHASE) is below 2 volts. An internal low-pass filter
with an 11MHz pole is located between the output of
the low-side driver (DL) and the input of the deadtime
circuit. This controls the high-side driver by filtering out
the noise that could appear on DL when the high-side
driver turns on.
Current Sensing
Current sensing is achieved by sampling and holding
the voltage across the high side FET while it is turned
on. The sampling network consists of an internal 50Ω
switch and an external 0.1µF hold capacitor . Internal
logic controls the turn-on and turn-off of the sample/
hold switch such that the switch does not tur n on until
VPHASE transitions high and turns of f when the input
to the high side driver goes low. Thus sampling will
occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the
sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high side FET and the
voltage across the sense resistor can be sampled by
the current sensing circuit.
Droop Compensation
The droop compensation network reduces the load
transient overshoot/undershoot at VOUT, relative to
VREF. VOUT is programmed to a voltage greater than
VREF (equal to VREF x (1+R5/R6)) by an external
resistor divider from VOUT to the VSENSE pin to
reduce the undershoot on VOUT during a low to high
load current transient. The over shoot during a high to
low load current transient is reduced by subtracting the
voltage that is on the DROOP pin from VREF. The
voltage on the IO pin is divided down with an external
© 2000 SEMTECH CORP.
13
PRELIMINARY - August 7, 2000
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
FUNCTIONAL DESCRIPTION (cont.)
resistor divider, and connected to the DROOP pin.
Thus, under loaded conditions, VOUT is regulated to
Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2).
Inhibit
The inhibit pin is a TTL compatible digital pin that is
used to enable the controller. When INH is low, the
output drivers are low, the soft start capacitor is discharged, the soft start cur rent source is disabled, and
the controller is in a low I
the short across the soft start capacitor is removed, the
soft start current source is enabled, and normal converter operation begins. W hen the system logic supply
is connected to INH, it controls power sequencing by
locking out controller operation until the system logic
supply exceeds the input threshold voltage of the INH
circuit; thus the +12V supply and the system logic
supply (either +5V or 3.3V) must be above UVLO
thresholds before the controller is allowed to start up.
VIN
The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start
threshold during power-up. While the controller is
disabled, the output drivers will be low, the soft start
capacitor will be shorted and the soft start current is
disabled and the controller will be in a low I
When VIN exceeds the start threshold, the short across
the soft start capacitor is removed, the soft start current
source is enabled and norm al converter operation begins. There is a 2V hysteresis in the undervoltage
lockout circuit for noise immunity.
state. When INH goes high,
Q
state.
Q
these resistor values will determine the soft start charging current. The maximum current that can be sourced
by REFB is 500µA.
Power Good
The power good circuit monitors for an undervoltage
condition on VOUT. If VSENSE is 7% (nom inal) below
VREF, then the power good pin is pulled low. The
PWRGD pin is an open drain output.
Overvoltage Protection
The overvoltage protection circuit monitors VOUT for
an overvoltage condition. If VSENSE is 15% above
VREF, than a fault latch is set and both output drivers
are turned off. T he latch will rem ain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity.
Overcurrent Protection
The overcurrent protection circ uit monitors the current
through the high side FET. The overcurrent thres hold
is adjustable with an external resistor divider between
IO and AGND, with the divider voltage connected to the
OCP pin. If the voltage on the OCP pin exceeds
100mV, then a fault latch is set and the output drivers
are turned off. T he latch will rem ain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity. The OCP circuit is
also designed to protect the high side FET against a
short-to-ground fault on the terminal common to both
power FETs (VPHASE).
Drive Regulator
Soft Start
The soft star t circuit controls the rate at which VOUT
powers up. A capacitor is connected between SS and
AGND and is charged by an internal current source.
The value of the current source is proportional to the
reference voltage so the charging rate of C
is also
SS
proportional to the reference voltage. By making the
charging current proportional to VREF, the power-up
time for VOUT will be independent of VREF. Thus, C
can remain the same value for all VID settings. The
soft start charging cur rent is determined by the following equation: I
SS
= I
/5. Where I
REFB
is the current
REFB
flowing out of the REFB pin. It is recommended that no
additional loads be connected to REFB, other than the
resistor divider for setting the hysteresis voltage. T hus
© 2000 SEMTECH CORP.
The drive regulator provides drive voltage to the low
side driver, and to the high side driver when the high
side driver is configured as a floating driver. The
minimum drive voltage is 7V. The minimum short
circuit current is 100mA.
SS
14
PRELIMINARY - August 7, 2000
APPLICATION CIRCUIT
+12V
+12V
+5V
+12V
+5V
+5V
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
+
_
Vout
Vout
GND
Vin +5 to +12V
+
_
J1
123
4
C9
0.1
C20
0.1
L1
1uH
C19
150uF 16V
C18
150uF 16V
J2
12345
C27
C26
C25
C24
C23
C22
C21
6
0.1
150uF/4V
150uF/4V
150uF/4V
150uF/4V
150uF/4V
150uF/4V
C17
PWRGD
INHIB
R10
10k
+5V
C11
0.01
R9
10k
+5V
28
PWRGD
U1
SC1155
IOUT1DROOP2OCP3VHYST4VREFB5VSENSE6AGND7SOFTST8N/C9LODRV10LOHIB11DRVGND12LOWDR13DRV
109876
S1
12345
23
24
25
26
27
VID4
VID3
VID2
VID1
VID0
C6
0.1
R5
100
R6
20k
C3
0.01
C4
R3
2.7k
R4
1k
R1
2k
R2
1k
0.01
150uF 16V
Ra*
C16
0.1
C12
0.1
21
22
IOUTLO
INHIBIT
C5
0.001
19
20
HISENSE
LOSENSE
+5V
C8
0.01
C7
0.1
0
18
BOOTLO
pin18
L2
1.5uH
Rb*
0
D1
MBRD1035
C14
0.33
Q1
IRL3103S
R11
2.2
17
HIGHDR
Dopt.
MBR0530
Q2
IRL2203S
+12V
R12
C13
0.33
16
3.9
C9
2.2uF 16V
15
BOOT
VIN12V
C8
14
2.2uF 16V
* Only one resistor/jumper to be installed, either Ra or Rb.
R7
150
R8
10k
© 2000 SEMTECH CORP.
C2
0.01
15
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
SC1155
WITH VRM 9.0 VID RANGE
PRELIMINARY - August 7, 2000
MATERIALS LIST
Quantity Reference Part/Description Vendor Notes
1 C5 0.001µF
6 C1-C4, C8, C11 0.01µF
3 C17-C19 150µF, 16V (TPS) AVX
7 C6,C7,C9,C12,C16,C20, C27 0.1µF
2 C13,C14 0.33µF
6 C21-C26 150µF, 4V, (PosCap) Sanyo
2 C10,C15 2.2µF, 16V
1 D1 MBRD1035 MOT
1 L1 1µH, DO5022P-102 Coilcraft
1 L2 1.5µH, DO5022P-152HC Coi l craft
1 Q1 IRL3103NS, D2PAK Int. Rect .
1 Q2 IRL2203NS, D2PAK Int. Rect .
2RA,RB
1R1 2K
2 R2,R4 1K
1R3 2.7K
1 R5 100
1 R6 20K
1 R7 150
3 R8,R9,R10 10K
1 R11 2.2
1 R12 3.9
1 U1 SC1155, SO-28 SEMTECH
0Ω
Layout guidelines
1. Locate R8 and C5 close to pins 6 and 7.
2. Locate C6 close to pins 5 and 7.
3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND.
4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND.
5. Locate bootstrap capacitor C13 close to the IC.
6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective.
7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise.
8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin.
9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass.
10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower
Vout settings, it needs to be placed next to the aforementioned FET in very close proximity.
11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be
achieved by connecting the AGND to the ground side of the bulk output capacitors.
12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple
vias.
13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the
chip with the cathode connected to BOOTLO and anode connected to DRVGND.
© 2000 SEMTECH CORP.
16
PRELIMINARY - August 7, 2000
EVALUATION BOARD ARTWORK
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
TOP LAYER
BOTTOM LAYER
© 2000 SEMTECH CORP.
17
PRELIMINARY - August 7, 2000
EVALUATION BOARD LAYOUT
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
TOP VIEW
BOTTOM VIEW
© 2000 SEMTECH CORP.
18
PRELIMINARY - August 7, 2000
OUTLINE - SO-28
PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
WITH VRM 9.0 VID RANGE
SC1155
ECN00-1229
© 2000 SEMTECH CORP.
19
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