SEMTECH SC1112 Technical data

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Description

SC1112

Triple Low Dropout

Regulator Controllers

Features

The SC1112 was designed for the latest high speed
motherboards. It includes three low dropout regulator con­trollers. The controllers provide the power for the system
AGTL bus Termination Voltage, Chipset, and clock circuitry.

An adjustable controller with a 1.2V reference is available,
while two selectable outputs are provided for the VTT
(1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A)
and the AGP (1.5V or 3.3V). The SC1112 low dropout
regulators are designed to track the 3.3V power supply
as the VTTIN supply is cycled On and Off. A latched short
circuit protection is also available for the VTT output.

Other features include an integrated charge pump that
provides adequate gate drives for the external Mosfets,
and a capacitive programable delay for the power good
signal.

Typical Application Circuit

K Triple linear controllers
K Selectable and Adjustable Output Voltages
K LDOs track input voltage within 200mV (Function of

the Mosfets used) until regulation

K Integrated Charge Pump
K Programmable Power Good delay Signal
K Latched Over Current Protection (VTT)

Applications

K Pentium
K Triple power supplies

®

III Motherboards

ADJ

C13

0.1u

C6
330u

C12
330u

VTT

1K

R1

POWER GOOD

Q2 C14

0.1u

C11

RA

RB

1u

22n

C10

C5

SC1112/A

5VSTBY

ADJGATE

ADJSEN

CAP- VTTGATE

CAP+

FC

DELAY

PWRGD

VTT SELECT Signal

GND

AGPGATE

AGPSEN

VTTSEN

AGPSEL

VTTSEL

VTTIN

C3

0.1u

C19
330u

AGP SELECT Signal

Q1

C8

330u

C2

C9

0.1u

C18

330u

Q3

C16
330u

330u

C1
10u

C17

0.1u

+3.3V

+5V STBY

AGP

VTT

Revision 7, October 2001

1

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Absolute Maximum Ratings

retemaraPlobmySmumixaMstinU

DNGotYBTSV5 7+ot3.0-V

DNGotNESTTV 5ot3.0-V

DNGotNESPGA 5ot3.0-V

DNGotNESJDA 5ot3.0-V

SC1112

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egnaRerutarepmeTnoitcnuJT
egnaRerutarepmeTegarotST

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tneibmAotnoitcnuJecnatsiseRlamrehT

esaCotnoitcnuJecnadepmIlamrehT

)ledoMydoBnamuH(gnitaRDSEDSE2Vk

Electrical Characteristics

Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V ; TA = 25°C

retemaraPlobmySsnoitidnoCniMpyTxaMstinU

)YBTSV5(ylppuS

egatloVylppuS

tnerruCylppuS

noitcetorPtiucriCtrohSTTV

dlohserhTremiTyaleDtiucriCtrohSTTV

)4(

emiTyaleDtiucriCtrohSTTV

tnerruCecruoSyaleDtiucriCtrohSTTV

)4(

dlohserhTtiucriCtrohSTTV

dooGrewoPTTV

)5(

dlohserhTremiTyaleDDGRWP

)5(

dlohsaerhTDGRWP

)5(

dlohsaerhTDGRWP

)5(

emiTyaleDDGRWP

)5(

emiTyaleDDGRWP

)5(

tnerruCecruoSDGRWP

snoitceSraeniL

I

)4(

CS

CS

)4(

I

CS

GP

GP
GP

GP
GP

I

GP

A

J

GTS

L

θ

AJ

θ

CJ

YBTSV5

YBTSV5

hT

dt

YBTSV5V5=6 8 21Am

57.4552.5V

07+ot0C°

521+ot0C°

051+ot56-C°
003C°
031W/C°

03W/C°

5.1V
CS*yaledC(

I/)

HT

CS

S

612282Aµ

CSTTV

hT

HT_yaleD

2.1_HT

5.1_HT

2.1_dt

5.1_dt

056007057Vm

054.1005.1055.1V

060.1580.1011.1V

033.1053.1093.1V
GP*yaledC(
GP*yaledC(

I/)

2.1_HT

GP

I/)

5.1_HT

GP

S
S

612282Aµ

dlohserhTylppuStupnITTV

)3()1(

ecnereffiDgnikcarT

NITTV

HT

V

atleD

KCART

NI

I

O

,V03.3=

A0=

2 2001 Semtech Corp.

54.125.155.1V
002Vm

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POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C

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).tnoC(snoitceSraeniL

SC1112

TTVegatloVtuptuO)A2111CS(

TTV

2.1

TTV

52.1

TTV

5.1

PGAegatloVtuptuOPGA

5.1

PGA

3.3

JDAegatloVtuptuOJDAI

tnerruCsaiBNESTTV

saibI

I

O

I

)2111CS(

O

I

O

I

O

I

O

O

NESTTV

A2ot0=%2-)BR/AR+1(*2.1%2+V

WOL=LESTTV,A2ot0=671.1002.1422.1V

WOL=LESTTV,A2ot0=522.1052.1572.1

HGIH=LESTTV,A2ot0=074.1005.1035.1V

WOL=LESPGA,A2ot0=074.1005.1035.1V

HGIH=LESPGA,A2ot0=432.3003.3V

09021041Aµ

)2111CS(

tnerruCsaiBNESTTV

saibI

NESTTV

15Aµ

)A2111CS(

tnerruCsaiBNESPGAsaibI

tnerruCsaiBNESJDAsaibI

tnerruCetaGTTVecruosI

NESPGA

NESJDA

etagTTV

knisI

etagTTV

V0.3=etagV,V57.4=YBTSV5005Aµ

011051071Aµ

15Aµ

005Aµ

tnerruCetaGPGAecruosI

tnerruCetaGJDAecruosI

noitalugeRdaoLDAOL

noitalugeReniLENIL

etagPGA

knisI

etagPGA

etagJDA

knisI

etagJDA

GER

GER

I,V03.3=NITTV

O

V0.3=etagV,V57.4=YBTSV5005Aµ

005Aµ

V0.3=etagV,V57.4=YBTSV5005Aµ

005Aµ

A2ot0=3.0%

,V74.3otV31.3=NITTV

3.0%

A2=oI

)2(

)LOA(niaG

NIAG

ODL

ETAGottuptuOSODL05Bd

Notes:

(1) All electrical characteristics are for the application circuit on page 19.
(2) Guaranteed by design
(3) Tracking Difference is defined as the delta between 3.3V V in and the VTT , AGP, ADJ output voltages during the linear ramp up until
regulation is achieved. The Tracking V oltage difference might vary depending on MOSFET s Rdson, and Load Conditions.
(4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch
timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit
protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip
threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input
voltage or the 5VSTBY is cycled.
(5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG
source current I
capacitor is charged above the PG

 2001 Semtech Corp.

(20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the

PG

(1.5V), the PWRGD pin is released from ground.

Delay_TH

3

td1.2

or PG

level. At that time the PWRGD

td1.5

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Timing Diagrams

SC1112

NORMAL STARTUP CONDITION

The delay capacitor does not
begin charging until VTTIN has
reached 1.5V and VTT is above
the powergood threshold of

1.08V.
Once DELAY reaches 1.5V,

the PWRGD signal goes high.
VTTGATE initially turns on

hard, until VTT reaches
regulation. Then VTTGATE
drops to its normal regulating
level.

VTTIN

VTT

DELAY

PWRGD

VTTGATE

VTTIN=1.5V

DELAY=1.5V

SHORT-CIRCUIT STARTUP

VTTIN

VTT

The delay capacitor does not
begin charging until VTTIN has
reached 1.5V and VTT is below
the short circuit threshold of

0.7V.
VTTGATE initially turns on hard

and is latched off when DELAY
reaches 1.5V and VTT is below

0.7V

DELAY

PWRGD

VTTGATE

VTTIN=1.5V

DELAY=1.5V

4 2001 Semtech Corp.

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POWER MANAGEMENT

Timing Diagrams (Cont.)

Once VTT drops out of
regulation, VTTGATE turns on
harder to try and raise VTT.

When VTT drops below 1.08V,
the delay capacitor is
discharged and PWRGD goes
low. When VTT drops below

0.7V, the delay capacitor
begins charging.

If VTT is still below 0.7V when
DELAY reaches 1.5V,
VTTGATE is latched off.

VTTIN

VTT

DELAY

SHORT-CIRCUIT DURING NORMAL
OPERATION

VTT=1.08V

VTT=0.7V

DELAY=1.5V

SC1112

PWRGD

VTTGATE

VTTIN

Once VTT drops out of
regulation, VTTGATE turns on
harder to try and raise VTT.

When VTT drops below 1.08V,
the delay capacitor is discharged
and PWRGD goes low. When
VTT drops below 0.7V, the delay
capacitor begins charging.

If VTT recovers above 0.7V
before DELAY reaches 1.5V,
DELAY is again discharged.

If VTT reaches 1.08V the delay
capacitor begins charging and
normal operation continues.

VTT

DELAY

VTT=1.08V

SHORT-CIRCUIT AND RECOVERY
DURING NORMAL OPERATION

VTT=0.7V

VTT=1.08V

DELAY=1.5V

 2001 Semtech Corp.

PWRGD

VTTGATE

5

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POWER MANAGEMENT

SC1112

Pin Configuration

5VSTBY
PWRGD

DELAY

VTTSEL

AGPSEL

ADJGATE

ADJSEN

CAP-

(16-Pin SOIC or TSSOP)

Pin Descriptions

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1YBTSV5 .srellortnocTEFdnarotallicsO,pmuPegrahC,feRrofrewopseilppus,tupniybdnatSV5

Top View

16

1

15

2

14

3

13

4

12

5

11

6
7

10

8

9

GND
VTTIN

VTTGATE
VTTSEN
AGPGATE
AGPSEN
FC
CAP+

Ordering Information

)2()1(

rebmuNtraP

egakcaP

RTS2111CS

61-OSC°521ot°0

RTSA2111CS
RTST2111CS

61-POSSTC°521ot°0

RTSTA2111CS

BVE2111CSdraoBnoitaulavE

Note:
(1) Only available in tape and reel packaging. A reel contains
2500 devices.
(2) Part Number (SO-16): SC1 1 12STR = 1.25V and
SC1 1 12ASTR = 1.2V .
Part Number (TSSOP-16): SC1 1 12TSTR = 1.25V and
SC11 12ATSTR = 1.2V.

pmeT

)

T(egnaR

J

2DGRWP.tuptuoTTVrofgalFdooGrewoProtcellocnepO
3YALED TTVfogalFdooGrewoPehtrofyaledehtmargorplliwDNGotnipsihtmorfroticapacA

4LESTTV:egatlovtuptuoTTVehtsmargorptahtlangisLTT

5LESPGA:egatlovtuptuoPGAehtsmargorptahtlangisLTT

6ETAGJDA.PGAroftuptuoevirdetaG
7NESJDA.JDAroftupniesneS
8-PAC.roticapactsoobotnoitcennocevitageN
9+PAC.roticapactsoobotnoitcennocevitisoP

01CF .DNGotnipsihtmorfdetcennocebdluohspmupegrahclanretniehtrofroticapacretliF
11NESPGA.PGAroftupniesneS
21ETAGPGA.PGAroftuptuoevirdetaG
31NESTTV.TTVroftupniesneS

.emitytinummihctilgehtdnatuptuo

VX2.1=TTV,WOL=LESTTV

V5.1=TTV,HGIH=LESTTV

V5.1=PGA,WOL=LESPGA

V3.3=PGA,HGIH=LESPGA

41ETAGTTV.TTVroftuptuoevirdetaG
51NITTV.niV3.3ehtotdetcennocenilesnestiucrictrohS
61DNG.dnuorG

NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.

6 2001 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Block Diagram

SC1112

VTTIN

DELAY

PWRGD

5VSTBY

Bandgap
Reference

+

-

_
+ _

1.5V

1.35V

1.2V

1.08V

0.7V

1.5V

+
_

+
_

+
_

0.7V

VTTSEN

Pwrgd
Threshold

VTTSEL

Vref

FC

1.5V

+
_

S

Q

R

+
_

Vref

Oscillator

ChargePump

Disable1.5

1.2V

Disable1.2

1.5V

Disable1.5

Disable3.3

1.2V

+
_

VTTGATE

VTTSEN

+
_

FC

+

AGPGATE

AGPSEN

+
_

FC

+
_

ADJGATE

GND

AGPSEL

CAP+

ADJSEN

CAP-

 2001 Semtech Corp.

7

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POWER MANAGEMENT

Typical Characteristics

SC1112

1.5055

1.5050

1.5045

1.5040

(V)

1.5

1.5035

VTT

1.5030

1.5025

1.5020

1.5015
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

VTT(1.25V) Output Voltage @ Io = 0A vs Ta

1.2485

1.2480

1.2475

VTT(1.5V) Output Voltage @ Io = 0A vs Ta

VTT(1.5V) Output Voltage @ Io = 2A vs Ta

1.5035

1.5030

1.5025

1.5020

(V)

1.5

1.5015

VTT

1.5010

1.5005

1.5000

1.4995
0 1020304050 6070

Ta (°C.)

5V St by = 5.25V
5V St by = 5.00V
5V St by = 4.75V

VTT(1.5V) Output Voltage @ Io = 2A vs Ta

1.2465

1.2460

1.2455

1.2470

(V)

1.2

1.2465

VTT

1.2460

1.2455

1.2450

1.2445
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

VTT Input Supply Threshold vs Ta

1.498

1.497

1.496

1.495

(V)

TH

VTTIN

1.494

1.493

1.492

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

1.2450

(V)

1.2

1.2445

VTT

1.2440

1.2435

1.2430

1.2425
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

VTT Sense Bias current vs Ta

116

114

112

(uA)

110

VTTSEN

Ibias

108

106

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

1.491
0 10203040506070

Ta (°C.)

104

0 10203040506070

8 2001 Semtech Corp.

Ta (°C.)

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POWER MANAGEMENT

Typical Characteristics (Cont.)

SC1112

VTT Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta

800

750

700

650

(uA)

600

VTT_Gate

I

550

500

450

400

0 10203040506070

Ta (°C.)

Source current
Sink current

VTT Short circuit Delay source current vs Ta

23.60

23.40

23.20

23.00

22.80

22.60

(uA)

SC

I

22.40

22.20

22.00

21.80

21.60
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

VTT Short circuit Delay Time (Cdelay = 0.1uF) vs Ta

8.40

8.30

8.20

8.10

(mS)

td

SC

8.00

7.90

7.80

7.70
0 10203040506070

Ta (°C.)

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

VTT Short circuit Delay Timer Threshold vs Ta

1.515

1.510

1.505

1.500

1.495

(V)

th

1.490

SC

1.485

1.480

1.475

1.470

1.465
0 10203040506070

Ta (°C.)

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

 2001 Semtech Corp.

9

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POWER MANAGEMENT

Typical Characteristics (Cont.)

VTT (1.25V) Power Good Threshold vs Ta

1.098

SC1112

VTT (1.25V) Power Good Delay Time vs Ta

8.40

1.096

1.094

1.092

1.090

(V)

TH_1.25

1.088

PG

1.086

1.084

1.082

1.080
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

VTT (1.5V) Power Good Threshold vs Ta

1.361

1.360

1.359

1.358

1.357

1.356

(V)

TH_1.5

1.355

PG

1.354

1.353

1.352

1.351

1.350

0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

8.30

8.20

8.10

(mS)

td_1.25

PG

8.00

7.90

7.80

7.70
0 10203040506070

Ta (°C.)

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

VTT (1.5V) Power Good Delay Time vs Ta

8.40

8.30

8.20

8.10

(mS)

td_1.5

PG

8.00

7.90

7.80

7.70
0 10203040506070

Ta (°C.)

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

VTT Power Good Source current vs Ta

23.60

23.40

23.20

23.00

22.80

22.60

(uA)

PG

I

22.40

22.20

22.00

21.80

21.60

21.40
0 10203040506070

Ta (°C.)

10 2001 Semtech Corp.

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

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POWER MANAGEMENT

Typical Characteristics (Cont.)

SC1112

AGP (1.5V) Output Voltage @ Io = 0A vs Ta

1.5055

1.5050

1.5045

1.5040

1.5035

(V)

1.5

1.5030

AGP

1.5025

1.5020

1.5015

1.5010

1.5005
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

AGP (3.3V) Output Voltage @ Io = 0A vs Ta

3.2900

3.2890

3.2880

3.2870

(V)

3.3

3.2860

AGP

3.2850

AGP (1.5V) Output Voltage @ Io = 2A vs Ta

1.5035

1.5030

1.5025

1.5020

1.5015

(V)

1.5

1.5010

AGP

1.5005

1.5000

1.4995

1.4990

1.4985
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

AGP (3.3V) Output Voltage @ Io = 2A vs Ta

3.2900

3.2890

3.2880

3.2870

(V)

3.3

3.2860

AGP

3.2850

3.2840

3.2830

3.2820
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

AGP Sense Bias current vs Ta

142

140

138

136

(uA)

AGPSEN

134

Ibias

132

130

128

0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

3.2840

3.2830

3.2820
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

AGP Gate Current @ Vgate = 3V, 5V Stby = 4.75 vs Ta

900

850

800

(uA)

750

AGP_Gate

I

700

650

600

0 10203040506070

Ta (°C.)

Sink cu rrent

Source current

 2001 Semtech Corp.

11

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POWER MANAGEMENT

Typical Characteristics (Cont.)

SC1112

ADJ (1.2V) Output Voltage @ Io = 0A vs Ta

1.2020

1.2010

1.2000

1.1990

(V)

1.2

ADJ

1.1980

1.1970

1.1960

1.1950
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

ADJ Sense Bias current vs Ta

350

330

310

290

270

(uA)

250

ADJSEN

230

Ibias

210

190

170

150

0 10203040506070

Ta (°C.)

5V Stby = 4.75V
5V Stby = 5.00V
5V Stby = 5.25V

ADJ (1.2V) Output Voltage @ Io = 2A vs Ta

1.1955

1.1950

1.1945

1.1940

(V)

1.2

1.1935

ADJ

1.1930

1.1925

1.1920

1.1915
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

ADJ Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta

900

850

800

(uA)

750

ADJ_Gate

I

700

650

600

0 10203040506070

Ta (°C.)

Sink current

Source current

12 2001 Semtech Corp.

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POWER MANAGEMENT

Typical Characteristics (Cont.)

SC1112

I 5V Stby vs Ta

7.50

7.30

7.10

6.90

6.70

6.50

I5vstby (mA)

6.30

6.10

5.90

5.70

5.50
0 10203040506070

Ta (°C.)

5V Stby = 5.25V
5V Stby = 5.00V
5V Stby = 4.75V

Line Regulation VTTIN = 3.13V to 3.47V Io = 2A vs Ta

160.0E-3

140.0E-3

120.0E-3

Output Select Threshold vs Ta

1.60

1.55

1.50

1.45

1.40

1.35

Output Select Threshold (V)

1.30

1.25

1.20
0 10203040506070

Ta (°C.)

VTTSEL
AGPSEL

Load Regulation VTTIN = 3.3V Io = 0 to 2A vs Ta

180.0E-3

170.0E-3

160.0E-3

100.0E-3

80.0E-3

Line Regulation(%)

60.0E-3

40.0E-3

20.0E-3

000.0E+0
0 10203040506070

Ta (°C.)

VTT 1.25V
AGP 1.25V

Charge Pump Output Voltage vs Ta

9.32

9.31

9.30

9.29

9.28

9.27

9.26

V Charge Pump(V)

9.25

9.24

9.23

9.22

9.21
0 10203040506070

Ta (°C.)

V Charge Pump

150.0E-3

140.0E-3

Load Regulation(%)

130.0E-3

120.0E-3

110.0E-3

100.0E-3
0 10203040506070

Ta (°C.)

VTT 1.25V
AGP 1.25V

Charge Pump Frequency vs Ta

375

Charge Pump Frequency

370

365

360

355

Charge Pump Frequency (kHz)

350

345

0 10203040506070

Ta (°C.)

 2001 Semtech Corp.

13

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POWER MANAGEMENT

Typical Gain & Phase Margin

SC1112

SC1112 Gain / Phase VTT = 1.25V @ 2A

60

50

40

30

20

Gain (dB)

10

0

-10

-20

-30
10 100 1000 10000 100000 1000000

Phase

Gain

Freq (Hz)

Gain
Phase ( d eg )

SC1112 Gain / Phase ADJ = 1.2V @ 2A

50

40

Gain
Phase (deg)

Gain

30

20

10

Gain (dB)

0

-10

-20

-30
10 100 1000 10000 100000 1000000

Phase

Freq (Hz)

200

180

160

140

120

100

80

60

40

20

0

200

180

160

140

120

100

80

60

40

20

0

Phase (deg)

Phase (deg)

SC1112 Gain / Phase VTT = 1.5V @ 2A

60

50

40

30

20

10

Gain (dB)

0

-10

-20

-30
10 100 1000 10000 100000 1000000

Phase

Gain

Freq (Hz)

Gain
Phase (deg)

SC1112 Gain / Phase AGP = 1.5V @ 2A

50

40

30

20

Gain (dB)

10

0

-10

-20

10 100 1000 10000 100000 1000000

Phase

Gain

Freq (Hz)

Gain
Phase (deg)

200

180

160

140

120

100

80

60

40

20

0

200

180

160

140

120

100

80

60

40

20

0

Phase (deg)

Phase (deg)

14 2001 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Applications Infomation

Theory Of Operation

SC1112

The SC1112 was designed for the latest high speed mother
boards requiring a controled power up sequencing of the
Outputs, and a programable delay for the Power good sig­nal.

Three Linear controllers have been incorperated into the
SC1112. The VTT output can be programmed to either a

1.250V or a 1.500V by applying a LOW or a HIGH control
signal to the VTTSEL pin. AGP output can also be
prgorammed via AGPSEL pin to a 1.50V or a 3.30V. The
SC1112 also provides an Adjustable output which utilizes
a resistive voltage divider.

The +5VSTBY supply will power the internal Reference,
Charge Pump, Oscillator, and the Fet controllers. After the
+5VSTBy has been established, LDO outputs will track the
VTTIN (3.30V) supply as it is applied.

An external capaitor connected to the Delay pin will pro­gram the VTT short circuit delay time (SCtd), and the PWRGD
delay time (PGtd).

During power up, an internal short circuit glitch timer will
start once the VTT Input Voltage exceeds the VTTIN

(1.5V).

TH

During the glitch timer immunity time, determined by the
Delay capacitor (Delay time is approximately equal to
(Cdelay*SCTH)/ISC), the short circuit protection is disabled
to allow VTT output to rise above the trip threashold (0.7V).

If the VTT output has not risen above the trip threashold
after the immunity time has elapsed, the VTT output is
latched off and will only be enabled again if either the VTT
input voltage or the 5VSTBY is cycled.

PWRGD pin is kept low during the power up, until the VTT
output has reached its PG

td1.25

the PWRGD source current I

or PG

(20uA) is enabled and will

PG

level. At that time

td1.5

start charging the external PWRGD delay capacitor
connected to the DELAY pin. Once the capacitor is charged
above the PG

(1.5V), the PWRGD pin is released from

Delay_TH

ground. A detailed timing diagram is shown on pages 4 to

5.

Also included is an overcurrent protection circuit that moni­tors the VTT voltage. If the output voltage drops below
700mV, as would occur during an overcurrent or short
condition, the device will pull the drive pin low and latch
off the output.

Fixed Output Voltage Options (VTT, AGP)

Please refer to the Application Circuit on Page 1. The VTT
and the AGP fixed output voltage can be programed from
a Control logic signal. Table below shows the possible Volt­ages:

LESTTVLESPGATTVPGA

00 V52.1V05.1

01 V52.1V03.3

10 V05.1V05.1

11 V05.1V03.3

Once the VTTSEL or the AGPSEL signal is established, an
internal resistive divider is used to compare the bandgap
reference voltage with the feed back output voltage. The
drive pin voltage is then adjusted to
maintain the output voltage set by the internal resistor
divider. Referring to the block diagram on page 7.

It is possible to adjust the output voltage of the VTT or
AGP, by applying an external resistor divider to the sense
pin (please refer to Figure 1 on Page 11). Since the sense
pin sinks a nominal 100µA, the resistor
values should be selected to allow 10mA to flow through
the divider. This will ensure that variations in this current
do not adversely affect output voltage regulation. Thus a
target value for R2 (maximum) can be calculated:

V

2R

The output voltage can only be adjusted upwards from the
fixed output voltage, and can be calculated using the
following equation:

)FIXED(OUT

mA10

Ω≤

1R




)FIXED(OUT)ADJUSTED(OUT





+•=

1VV



2R



VoltsA1001R

µ•+

 2001 Semtech Corp.

15

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POWER MANAGEMENT

Applications Infomation (Cont.)

SC1112

5VSTBY

ADJGATE

ADJSEN

CAP- VTTGATE

CAP+

FC

DELAY

PWRGD

GND

AGPGATE

AGPSEN

VTTSEN

AGPSEL

VTTSEL

VTTIN

C3

0.1u

C19
330u

Q1

330u

C8

C9

0.1u

C2

C18

330u

Q3

C16
330u

R1

C14
330u

C1
10u

C17

0.1u

SC1112

+3.3V

+5V STBY

AGP

VTT

VTT SELECT Signal

AGP SELECT Signal

Figure 1: Adjusting The Output Voltage of VTT or AGP

Adjustable Output Voltage Option

The adjustable output voltage option does not have an
internal resistor divider. The adjust pin connects directly to
the inverting input of the error amplifier, and the
output voltage is set using external resistors (please
refer to Figure 2). In this case, the adjust pin sources a
nominal 0.5µA, so the resistor values should be selected
to allow 50µA to flow through the divider. Again, a target
value for RB (maximum) can be
calculated:

RB

V200.1

Ω≤

A50

µ

The output voltage can be calculated as follows:

RA

OUT








1200.1V

+•=µµ



RB



RAA5.0

•−

C13

0.1u

R2

C6
330u

C12
330u

RA

RB

Q2

1K

R1

VTT

POWER GOOD

0.1u

C11

1u

C10

22n

C5

SC11

5VSTBY

ADJGATE

ADJSEN

CAP­CAP+

FC

DELAY

PWRGD

The maximum output voltage that can be obtained from
the adjustable option is determined by the input supply
voltage and the R

and gate threshold voltage of the

DS(ON)

external MOSFET. Assuming that the MOSFET gate
threshold voltage is sufficiently low for the output
voltage chosen and a worst-case drive voltage of 9V, V

OUT(MAX)

is given by:

•−=

RIVTTINV

)MAX)(ON(DS)MAX(OUT)MIN()MAX(OUT

Figure 2

16 2001 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Applications Infomation (Cont.)

SC1112

Short Circuit Protection

The VTT short circuit protection feature of the SC1112 is
implemented by using the R

of the MOSFET. As the

DS(ON)

output current increases, the regulation loop maintains
the output voltage by turning the FET on more and more.
Eventually, as the R

limit is reached, the MOSFET will

DS(ON)

be unable to turn on any further, and the output
voltage will start to fall. When the VTT output voltage falls
to approximately 700mV, the LDO controller is latched off,
setting output voltage to 0V. Power must be cycled to re­set the latch.

To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially
disabled. It is enabled once the short circuit delay time
has elapsed. Timing diagram on pages 4 to 5 will show a
detailed operation of the Short circuit protection circuitry.

To be most effective, the MOSFET R

should not be

DS(ON)

selected artificially low. The MOSFET should be
chosen so that at maximum required current, it is almost
fully turned on. If, for example, a supply of 1.5V at 4A is
required from a 3.3V ± 5% rail, the maximum allowable
R

would be:

DS(ON)

Layout Guidelines

One of the advantages of using the SC1112 to drive an
external MOSFET is that the bandgap reference and
control circuitry do not need to be located right next to the
power device, thus a very accurate output voltage can be
obtained since heating effects will be minimal.

The 0.1µF bypass capacitor should be located close to the
+5VSTBY supply pin, and connected directly to the ground
plane. The ground pin of the device should also be con­nected directly to the ground plane. The sense or adjust
pin does not need to be close to the output voltage plane,
but should be routed to avoid noisy traces if at all pos­sible.

Power dissipation within the device is practically
negligible, requiring no special consideration during
layout.

()

R

=

)MAX)(ON(DS

•−•

025.15.13.395.0

4

Ω≈

m400

To allow for temperature effects 200mΩ would be a
suitable room temperature maximum, allowing a peak
short circuit current of approximately 15A for a short time
before shutdown.

Capacitor Selection

Output Capacitors: low ESR aluminum electrolytic or tan-

talum capacitors are recommended for bulk
capacitance, with ceramic bypass capacitors for decoupling
high frequency transients.

Input Capacitors: placement of low ESR aluminum
electrolytic or tantalum capacitors at the input to the
MOSFET (VTTIN) will help to hold up the power supply
during fast load changes, thus improving overall transient
response. The +5VSTBY supply should be bypassed with a
10µF ceramic capacitor.

 2001 Semtech Corp.

17

www.semtech.com

POWER MANAGEMENT

Evaluation Board Gerbers

SC1112

Board Layout Assembly Top

Board Layout Assembly Bottom

Board Layout T op Board Layout Bottom

18 2001 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Evaluation Board Schematic

SC1112

+5VSTBY

J1

+5VSTBY

C1

10uF

GND
J2

+3.3V

J3

+3.3V

+3.3V

GND
J5

J4

C18

330uF

+

C2

330uF

+

C4

0.1uF

C3

0.1uF

VTT

POWER GOOD

GND
J7

16

GND

U1 SC1112CS

5VSTBY

1

R1

1k

J6

Q1

IRFR120N

15

VTTIN

VTTGATE

PWRGD

DELAY

3

2

C5 22nF

VTT

J8

VTT

131114

VTTSEN

VTTSEL

4

100k

R2

VTT

J10

J9

C19

330uF

+

C8

330uF

+

C9

0.1uF

12

AGPGATE

AGPSEL

5

6

100k

R3

GND

GND

J12

C10

98

AGPSEN

ADJGATE

ADJSEN FC

7 10

C14

330uF

+

C15

0.1uF

Q3

1uF

CAP+CAP-

C11 0.1uF

J14

J15

VTT SELECT Signal

AGP SELECT Signal

AGP

J18

AGP

IRFR120N

JP2

*

1
1

*

JP1

AGP

GND

GND

J20

J21

J19

C16

330uF

+

C17

0.1uF

JP1 = SHORT, VTT = 1.25 V

JP1 = OPEN, VTT = 1.5 V

JP2 = OPEN, AGP = 3.3 V

JP2 = SHORT, AGP = 1.5 V

*

*

*

*

2
2

 2001 Semtech Corp.

C7

0.1uF

+

C6

330uF

Q2

IRFR120N

ADJ

J11

ADJ

19

**

J13

ADJ

RA

C13

+

C12

RB

**

0.1uF

330uF

J16

ADJ = 1.2*(1+RA/RB)
**

GND

J17

GND

www.semtech.com

POWER MANAGEMENT

Evaluation Board Bill of Materials

metI.ytQecnerefeRtraPtnirPtooF

111CFu016021
28 91C,81C,61C,41C,21C,8C,6C,2CFu033130./001.SL/57.2.D/LYCPC
38 71C,51C,31C,11C,9C,7C,4C,3CFu1.05080
415CFn225080
5101CFu15080
62 2PJ,1PJ2PTP2/AIV
711JYBTSV5+2505DE
89 12J,02J,71J,61J,21J,01J,7J,5J,2JDNG2505DE
92 4J,3JV3.3+2505DE

SC1112

0116JdooGrewoP2505DE
112 9J,8JTTV2505DE
212 21J,11JJDA2505DE
31141JlangiSTCELESTTV2505DE
41151JlangiSTCELESPGA2505DE
512 91J,81JPGA2505DE
613 3Q,2Q,1QN021RFRITEFKAPD
713 BR,AR,1Rk15080
812 3R,2Rk0015080
9111URTS2111CS61-OS

Outline Drawing - TSSOP-16

20 2001 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Outline Drawing - SO-16

SC1112

Land Pattern - SO-16

Contact Information

 2001 Semtech Corp.

Semtech Corporation

Power Management Products Division

652 Mitchell Rd., Newbury Park, CA 91320

Phone: [phone] FAX [phone]

21

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