Semiconductor NCP5388 Specifications

Page 1

NCP5388

2/3/4 Phase Buck Controller for VR10 and VR11 Pentium IV Processor Applications

The NCP5388 is a two−, three−, or four−phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power Intel’s most demanding Pentium® IV Processors and low voltage, high current power supplies. Dual−edge pulse−width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient loads thereby requiring less bulk and ceramic output capacitors to satisfy transient load−line requirements.

A high performance operational error amplifier is provided, which allows for easy compensation of the system. The proprietary method of Dynamic Reference Injection (Patent Pending) makes the error amplifier compensation virtually independent of the system response to VID changes, eliminating the need for tradeoffs between load transients and Dynamic VID performance.

Features

• Meets Intel’s VR 10.0, 10.1, 10.2, and 11.0 Specifications

• Dual−Edge PWM for Fastest Initial Response to Transient Loading

• High Performance Operational Error Amplifier

• Supports both VR11 and Legacy VR10 Soft−Start Modes

• Dynamic Reference Injection (Patent Pending)

• 8−Bit DAC per Intel’s VR11 Specifications

• DAC Range from 0.5 V to 1.6 V

• "0.75% System Voltage Accuracy

• Remote Temperature Sensing per VR11

• 2, 3, or 4−Phase Operation

• True Differential Remote Voltage Sensing Amplifier

• Phase−to−Phase Current Balancing

• “Lossless” Differential Inductor Current Sensing

• Differential Current Sense Amplifiers for each Phase

• Adaptive Voltage Positioning (AVP)

• Fixed No−Load Voltage Positioning at –19 mV

• Frequency Range: 100 kHz–1.0 MHz

• Latched Overvoltage Protection (OVP)

• Threshold Sensitive Enable Pin for VTT Sensing

• Power Good Output with Internal Delays

• Programmable Soft−Start Time

• Operates from 12 V

• This is a Pb−Free Device*

http://onsemi.com

MARKING DIAGRAM

40 PIN QFN, 7x7

MN SUFFIX

CASE 488AG

NCP5388 = Specific Device Code AA = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G/G = Pb−Free Package

*Pin 41 is the thermal pad on the bottom of the device.

ORDERING INFORMATION

Device Package Shipping

NCP5388MNR2G QFN−40

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

NCP5388

AAWLYYWWG

†

2500 / Tape & Reel

Applications

• Pentium IV Processors

• VRM Modules

• Graphics Cards

• Low Voltage, High Current Power Supplies

June, 2010 − Rev. 11

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

1 Publication Order Number:

NCP5388/D

Page 2

NCP5388

PIN CONNECTIONS

34G433G332G231

NTC

VCC

VREF

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VR10/11

VR_FAN

VR_HOT

SS11ROSC12ILIM13AGND14VS+15VS−16DIFFOUT17COMP18VFB19VDRP

VR_RDY

NCP5388

DGND

DRVON

(Top View)

CS4

CS4N

CS3

CS3N

CS2

CS2N

CS1

CS1N

http://onsemi.com

Page 3

NCP5388

VR10/11

VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7

VS−

VS+

DIFFOUT

VFB

COMP

VDRP

CS1

CS1N

CS2

CS2N

CS3

CS3N

CS4

CS4N

1.3 V

VR10/11

DAC

Droop

Amplifier

Gain = 6

Oscillator

Diff Amp

Error Amp

+ −

1.3 V

NCP5388

Fault

OVER

4OFF

Fault

ENB

VREF

NTC

VR_FAN

NTC

VR_HOT

DGND

ROSC

ILIM

VCC

AGND

DAC

VS+

VS−

Current Limit

9.0 V

UVLO

Figure 1. Simplified Block Diagram

http://onsemi.com

Fault Logic

3 Phase

Detect

and Monitor Circuits

DRVON

VR_RDY

Page 4

NCP5388

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID8

VR_EN

VR_RDY

VR_HOT

VR_FAN

VTT

680  PULLUPS

RISO1

RT2

CFB1 RFB1

RFB

RDRP

CF RF

RISO2

RVCC

+12 V

U20

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VR10/VR11

VR_RDY

VR_HOT

VR_FAN

VS−

VS+

NCP5388

DIFFOUT

VFB

VDRP

COMP

ILIM

RLIM1

VCC

CVCC1

DGND

AGND

DRVON

SSROSC

VREF

NTC

CS1

CS1N

CS2

CS2N

CS3

CS3N

CS4

CS4N

1112

CSS

12 V_FILTER

RNTC1

RT1

RNTC2

12 V_FILTER

BAT54HT1

NCP3418B

VCC4BST

DRVH

DRVL

PGND

VCC4BST

DRVH

DRVL

PGND

VCC4BST

DRVH

DRVL

PGND

NTD85N02RT4

12 V_FILTER

NTD60N02RT4

12 V_FILTER

RS1

CS1

RLIM2

RT2 LOCATED NEAR OUTPUT INDUCTORS

VCCP

VSSP

Figure 2. Application Schematic for Four Phases

12 V_FILTER

http://onsemi.com

VCC4BST

DRVH

DRVL

PGND

12 V_FILTER

CPU GND

Page 5

NCP5388

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID8

VR_EN

VR_RDY

VR_HOT

VR_FAN

VTT

RISO1

680  PULLUPS

RISO2

RT2

CFB1 RFB1

RFB

RDRP

RVCC

+12 V

VCC

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VR10/VR11

VR_RDY

VR_HOT

VR_FAN

VS−

VS+

NCP5388

DIFFOUT

VFB

VDRP

COMP

ILIM

RLIM1

CVCC1

DGND

AGND

DRVON

SSROSC

VREF

NTC

CS1

CS1N

CS2

CS2N

CS3

CS3N

CS4

CS4N

1112

CSS

12 V_FILTER

RT1

RNTC2

RNTC1

12 V_FILTER

BAT54HT1

NCP3418B

VCC4BST

DRVH

DRVL

PGND

VCC4BST

DRVH

DRVL

PGND

VCC4BST

DRVH

DRVL

PGND

NTD85N02RT4

12 V_FILTER

NTD60N02RT4

12 V_FILTER

RS1

CS1

RLIM2

RT2 LOCATED NEAR OUTPUT INDUCTORS

VCCP

VSSP

Figure 3. Application Schematic for Three Phases

CPU GND

http://onsemi.com

Page 6

NCP5388

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID8

VR_EN

VR_RDY

VR_HOT

VR_FAN

VTT

RISO1

680  PULLUPS

RISO2

RT2

CFB1 RFB1

RFB

RVCC

+12 V

U21

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VR10/VR11

VR_RDY

VR_HOT

VR_FAN

VS−

VS+

NCP5388

DIFFOUT

VFB

VCC

CVCC1

DGND

AGND

VREF

NTC

CS1

CS1N

CS2

CS2N

CS3

CS3N

CS4

CS4N

12 V_FILTER

RT1

RNTC2

RNTC1

12 V_FILTER

BAT54HT1

NCP3418B

VCC4BST

DRVH

DRVL

PGND

VCC4BST

DRVH

DRVL

PGND

NTD85N02RT4

12 V_FILTER

NTD60N02RT4

12 V_FILTER

RS1

CS1

RDRP

CF RF

VCCP

VSSP

VDRP

COMP

ILIM

RLIM1

RLIM2

RT2 LOCATED NEAR OUTPUT INDUCTORS

DRVON

SSROSC

1112

CSS

Figure 4. Application Schematic for Two Phases

CPU GND

http://onsemi.com

Page 7

NCP5388

PIN DESCRIPTIONS

Pin No. Symbol Description

1 EN Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open−collector output

2 – 9 VID0–VID7 Voltage ID DAC inputs.

10 VR10/VR11 VR select bit. Connect this pin to VTT (1.25 V) to select the VR11 DAC table. Ground this pin to select the

11 SS A capacitor from this pin to ground programs the soft−start time.

12 ROSC A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies a regulated

13 ILIM Over current shutdown threshold. To program the shutdown threshold, connect this pin to the R

14 AGND Power supply return for the analog circuits that control output voltage.

15 VS+ Non−inverting input to the internal differential remote V

16 VS− Inverting input to the internal differential remote V

17 DIFFOUT Output of the differential remote sense amplifier.

18 COMP Output of the error amplifier.

19 VFB Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the

20 VDRP Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin minus 1.3 V is

21, 23,

CSxN Inverting input to current sense amplifier #x, x = 1, 2, 3, 4.

25, 27

22, 24,

CSx Non−inverting input to current sense amplifier #x, x = 1, 2, 3, 4.

26, 28

29 DRVON Gate Driver enable output. This pin produces a logic HIGH to enable gate drivers and a logic LOW to disable

30 – 33 G1 – G4 PWM control signal outputs to gate drivers.

34 VREF Voltage reference pin. This pin may be used to implement remote NTC temperature sensing as shown in the

35 DGND Power supply return for the digital circuits. Connect to AGND.

36 VCC Power for the internal control circuits.

37 VR_RDY Voltage Regulator Ready (PowerGood) output. Open drain type output with internal delays that will transition

38 NTC Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from

39 VR_FAN Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.416 V.

40 VR_HOT Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.086 V.

41 THPAD Copper pad on the bottom of the IC for heatsinking. This pin should be connected to the ground plane under

(with a pull−up resistor) or a logic gate (CMOS or totem−pole output) may be used to drive this pin. A Low to High transition on this pin will initiate a soft start. If the Enable function is not required, this pin should be tied directly to VREF.

VR10 DAC table with VR11 type startup. Connect this pin to V legacy VR10 type startup.

(4 V) to select VR10 DAC table with

REF

2.0 V which may be used with a voltage divider to the ILIM pin to set the over current shutdown threshold as shown in the Applications Schematics.

pin via a resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin directly to the R generated by the R

amount of current from the droop resistor (R load.

pin. To guarantee correct operation, this pin should only be connected to the voltage

OSC

pin – do not connect this pin to any externally generated voltages.

OSC

sense amplifier.

CORE

sense amplifier.

CORE

) will set the amount of output voltage droop (AVP) during

DRP

OSC

proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no AVP.

gate drivers and has an internal 70 k to ground.

Applications Schematic.

High when V and Low when V mV until VCC is removed.

this pin to V

is higher than 300 mV below DAC, Low when V

CORE

REF

is higher than DAC+185 mV. This output is latched Low if V

CORE

. As the NTC’s temperature increases the voltage on this pin will decrease.

is lower than 380 mV below DAC,

CORE

exceeds DAC+185

CORE

This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 1.176 V.

This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 0.846 V.

the IC.

http://onsemi.com

Page 8

NCP5388

MAXIMUM RATINGS

Rating Value Unit

Operating Ambient Temperature Range 0 to 70 °C

Operating Junction Temperature Range 0 to 85 °C

Storage Temperature Range −55 to 150 °C

Lead Temperature Soldering, Reflow (60 to 120 seconds minimum above 237°C): 260 °C

Thermal Resistance, Junction−to−Ambient (R

JEDEC Moisture Sensitivity Level ≤ 3 MSL

Maximum Voltage – VCC pin with respect to AGND 15 V

Maximum Voltage – all other pins with respect to AGND 5.5 V

Minimum Voltage – all pins with respect to AGND −0.3 V

Maximum Current into pins: COMP, VDRP, DIFFOUT, VREF 3.0 mA

Maximum Current into pins: VR_RDY, G1, G2, G3, G4, SS, VR_FAN, VR_HOT, DRVON 20 mA

Maximum Current out of pins: COMP, VDRP, DIFFOUT, ROSC, VREF 3.0 mA

Maximum Current out of pins: G1, G2, G3, G4 20 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

NOTE: ESD Senstive Device.

) on a thermally conductive PCB in free air 83 °C/W

http://onsemi.com

Page 9

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter Test Conditions Min Ty p Max Units

Error Amplifier

Input Bias Current −200 −50 −10 nA

Inverting Input Voltage 1.0 k between VFB and COMP Pins − 1.3 − V

Input Offset Voltage (Note 1) −1.0 − 1.0 mV

Open Loop DC Gain (Note 1) CL = 60 pF to GND,

Open Loop Unity Gain Bandwidth (Note 1)

Open Loop Phase Margin (Note 1) CL = 60 pF to GND,

Slew Rate (Note 1) Vin = 100 mV, G = −1.0 V/V,

Maximum Output Voltage I

Minimum Output Voltage I

Output Source Current (Note 1) V

Output Sink Current (Note 1) V

Remote Sense Differential Amplifier

VS+ Input Resistance (Note 1) DRVON = High

VS+ Input Open Circuit Voltage (Note 1)

VS− Input Resistance (Note 1) VS+ = DAC Voltage

VS− Input Open Circuit Voltage (Note 1)

Input Voltage Range −0.3 − 3.0 V

Input Offset Voltage (Note 1) −1.0 − 1.0 mV

−3dB Bandwidth (Note 1) CL = 80 pF to GND,

DC Gain I

Slew Rate (Note 1) Vin = 1.0 V,

Maximum Output Voltage I

Minimum Output Voltage I

Output Source Current (Note 1) V

Output Sink Current (Note 1) V

1. Guaranteed by design. Not tested in production.

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

RL = 10 k to GND

CL = 60 pF to GND, RL = 10 k to GND

RL = 10 k to GND

1.2 V < V

< 2.2 V,

out

CL = 60 pF, DC Load = ±125 A

= 1.0 mA 3.0 3.3 − V

SOURCE

= 1.0 mA − 0.9 1.0 V

SINK

= 3.0 V − 2.0 − mA

out

= 1.0 V − 2.0 − mA

out

DRVON = Low

DRVON = High DRVON = Low

DRVON = High

DRVON = High VS+ = DAC Voltage

RL = 10 k to GND

= 100 A 0.982 1.000 1.018 V/V

DIFFOUT

V

= 1.0 V to 2.0 V,

out

CL = 80 pF to GND, Load = ±125 A

= 1.0 mA 3.0 − − V

SOURCE

= 1.0 mA − − 0.5 V

SINK

= 2.1 V − 25 − mA

out

= 1.0 V − 1.4 − mA

out

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

− 78 − dB

− 15 − MHz

− 65 − deg

− 5.0 − V/s

−

0.5

0.67

0.05

−

− 10 − k

0.333*DA C

+ 0.433

− 12 − MHz

− 10 − V/s

k

http://onsemi.com

Page 10

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

Adaptive Voltage Positioning Amplifier

DRP

Current Sense Input to V

−3dB Bandwidth (Note 1)

Current Sense Input to V Slew Rate (Note 1)

Current Summing Amp Output Offset Voltage

Maximum V

Minimum V

Output Voltage CSx − CSxN = 0.12 V

DRP

Output Voltage CSx − CSxN = −0.12 V

DRP

Output Source Current (Note 1) VDRP = 2.9 V − 9.0 − mA

Output Sink Current (Note 1) VDRP = 1.0 V − 2.0 − mA

Current Sense Amplifiers

Input Bias Current CSx = CSxN = 1.4 V −200 −100 − nA

Common Mode Input Voltage Range (Note 1)

Differential Mode Input Voltage Range −120 − 120 mV

Input Offset Voltage (Note 1) CSx = CSxN = 1.0 V −3.0 − 3.0 mV

Current Sense Input to PWM Comparator Input Gain

Oscillator

Switching Frequency Range (Note 1) 100 − 1000 kHz

Switching Frequency Accuracy (Note 1)

Switching Frequency Accuracy R

Switching Frequency Accuracy (Note 1)

Switching Frequency Accuracy R

Output Voltage 10 k < R

OSC

Output Voltage (Note 1) 49.9 k < R

OSC

1. Guaranteed by design. Not tested in production.

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

Gain −60 mV < (CSx−CSxN)

DRP

Output

< +60 mV, T

CL = 330 pF to GND,

= 25°C

RL = 10 k to GND

DRP

Output

V(CSx−CSxN) = 25 mV (all phases),

1.3 V < V

< 1.9 V,

out

CL = 330 pF to GND, Load = ±400 A

CSx – CSxN = 0, CSx =1.0 V −40 − +40 mV

(all phases), I

SOURCE

= 1.0 mA

(all phases), I

= 1.0 mA

SINK

0 mV < (CSx−CSxN) < 25 mV T

= 25°C

= 100 k, 2 or 4−phase 93.6 104 114.4 kHz

OSC

= 49.9 k, 2 or 4−phase 184.5 205 225.5 kHz

OSC

= 24.9 k, 2 or 4−phase 360 400 440 kHz

OSC

= 10 k, 2 or 4−phase 829 921 1013 kHz

OSC

= 100 k, 3−phase 90 100 11 0 kHz

OSC

= 49.9 k, 3−phase 178.2 198 217.8 kHz

OSC

= 24.9 k, 3−phase 351 390 429 kHz

OSC

= 10 k, 3−phase 818 909 1000 kHz

OSC

< 49.9 k 1.92 2.00 2.08 V

OSC

< 100 k − 2.00 − V

OSC

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

5.7 6.0 6.3 V/V

− 7.2 − MHz

− 3.7 − V/s

3.02 − − V

− − 0.5 V

−0.3 − 2.0 V

5.7 6.0 6.3 V/V

http://onsemi.com

Page 11

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

Modulators (PWM Comparators)

Minimum Pulse Width Fs = 400 kHz − 30 40 ns

Magnitude of the PWM Ramp − 1.0 − V

0% Duty Cycle COMP voltage when the PWM

100% Duty Cycle COMP voltage when the PWM

Minimum PWM Linear Duty Cycle (Note 1)

PWM Comparator Offset Mismatch (Note 1)

Phase Angle Error Between adjacent phases,

Propagation Delay (Note 1) Ramp/Comp crossing to Gx high − 20 − ns

Propagation Delay (Note 1) Ramp/Comp crossing to Gx low − 20 − ns

PWM Outputs

Output High Voltage Sourcing 500 A 3.3 4.0 4.7 V

Output Low Voltage Sinking 500 A − 25 100 mV

Rise Time CL = 20 pF, Vo = 0.3 to 2.0 V − 10 − ns

Fall Time CL = 20 pF, Vo = Vmax to 0.7 V − 10 − ns

Output Impedance – LO State Resistance to GND (Gx = LO) − 50 − 

G4 Gate Pin Source Current during Phase Detect

Phase Detection Period − 50 − s

G4 Phase Detect Threshold Resistance

Gate Driver Enable (DRVON)

Output High Voltage Sourcing 500 A 4.0 5.3 5.5 V

Output Low Voltage Sinking 500 A − 50 200 mV

Rise Time CL (PCB) = 20 pF,

Fall Time CL (PCB) = 20 pF,

Internal Pulldown Resistance VCC < UVLO Threshold − 70 140 k

1. Guaranteed by design. Not tested in production.

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

outputs remain LO

outputs remain HI

FS = 400 kHz − 90 − %

Between any 2 phases, FS = 400 kHz

FS = 400 kHz

Vo = 10% to 90%

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

− 1.2 − V

− 2.3 − V

− − 40 mV

−15 − 15 °

− 70 − A

− − 1.0 k

− 25 − ns

http://onsemi.com

Page 12

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

VR_RDY (Power Good) Output

Saturation Voltage I

Rise Time External pullup of 1.0 k to 1.25 V,

Output Voltage at Power−up (Note 1) External VR_RDY pullup resistor of 2.0

High – Output Leakage Current VR_RDY = 5.5 V via 1.0 K − − 1.0 A

Threshold Voltage VCORE increasing,

Rising Delay VCORE increasing 0.3 1.40 2.0 ms

Falling Delay VCORE decreasing − 5.0 − s

VR_FAN AND VR_HOT

NTC Pin Bias Current 0 V < NTC < 5.0 V −1.0 − 1.0 A

VR_FAN Upper Voltage Threshold Fraction of VREF voltage above which

VR_FAN Lower Voltage Threshold Fraction of VREF voltage below which

VR_FAN Hysteresis 210 240 270 mV

VR_FAN Output Voltage at Powerup (Note 1)

VR_FAN Output Saturation Voltage I

VR_FAN Output Leakage Current High Impedance State,

VR_HOT Upper Voltage Threshold Fraction of VREF voltage above which

VR_HOT Lower Voltage Threshold Fraction of VREF voltage below which

VR_HOT Hysteresis 210 240 270 mV

VR_HOT Output Voltage at Powerup (Note 1)

VR_HOT Saturation Output Voltage I

VR_HOT Output Leakage Current High Impedance State,

1. Guaranteed by design. Not tested in production.

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

= 10 mA − − 0.4 V

SINK

= 20 pF,

LOAD

Vo = 10% to 90%

k to 5.0 V, t

≤ 3 x t

R_VCC

100 s ≤ t

R_5V

R_VCC

≤ 20 ms

DAC = 1.3 V

VR_FAN output pulls low

VR_FAN output is open

External Pullup resistor of 2.0 k to 5.0 V, t

≤ 3 x t

R_VCC

100 s ≤ t

= 4.0 mA − − 0.3 V

SINK

R_5V

R_VCC

≤ 20 ms

VR_FAN = 5.0 V

VR_HOT output pulls low

VR_HOT output is open

External Pullup resistor of 2.0 k to 5.0 V, t

≤ 3 x t

R_VCC

100 s ≤ t

= 4.0 mA − − 0.3 V

SINK

R_5V

R_VCC

≤ 20 ms

VR_HOT = 5.0 V

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

− − 150 ns

− − 1.0 V

− 300 − mV below

0.3518 0.3625 0.3737

0.2892 0.3025 0.3112

− − 1.0 V

− − 1.0 A

0.2732 0.2815 0.2897

0.2107 0.2190 0.2272

− − 1.0 V

− − 1.0 A

DAC

http://onsemi.com

Page 13

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

Soft−Start

SS Pin Source Current ENABLE = HI, V

Soft−Start Ramp Time CSS = 0.01 F, DRVON = HI to V

SS Pin Discharge Voltage ENABLE = LO − − 50 mV

Soft−Start Discharge Time From ENABLE = LO to V

VR11 V

Threshold Voltage − 1.081 − V

BOOT

VR11 Dwell Time at V

Enable Input

Enable High Input Leakage Current EN = 3.0 V − − 10 A

Upper Threshold V

Lower Threshold V

Total Hysteresis V

Enable Delay Time Enable transitioning HI to start of SS

Disable Delay Time Enable transitioning Low to

Current Limit

Current Sense Inputs to I

ILIM Pin Input Bias Current V

ILIM Pin Working Voltage Range 0.3 − 2.0 V

ILIM Input Offset Voltage −50 − 50 mV

Overvoltage Protection

Overvoltage Threshold DAC+160 DAC+180 DAC+200 mV

Undervoltage Protection

UVLO Start Threshold 8.2 9.0 9.5 V

UVLO Stop Threshold 7.2 8.0 8.5 V

UVLO Hysteresis − 1.0 − V

VID Inputs

Upper Threshold V

Lower Threshold V

Input Bias Current V

Delay before Latching VID Change (VID De−Skewing)

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

< 1.1 V − 5.0 − A

SS PIN

> 1.15 V, VR11

SS mode only

SS PIN

= 1.1 V

Discharge Voltage,

SS PIN

< max

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

125 − − A

1.5 2.2 3.0 ms

− 5.0 − s

CSS = 0.01 F

(Note 1) 50 225 900 s

BOOT

UPPER

LOWER

UPPER

– V

LOWER

0.80 0.85 0.90 V

0.67 0.75 0.83 V

70 100 130 mV

0.5 1.5 3.0 ms

voltage rise

− − 200 ns

DRVON = Low

Gain 20 mV < (CSx−CSxN) < 60 mV

LIM

= 25°C

(all CS channels together)

= 2.0 V − 0.1 1.0 A

ILIM

UPPER

LOWER

= 1.25 V − 100 500 nA

VIDX

Measured from the 1st edge of a VID

5.7 6.0 6.3 V/V

− − 800 mV

400 − − mV

500 − 1000 ns

change

http://onsemi.com

Page 14

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

VR10/VR11 Select

VR10/VR11 DAC Table Threshold 0.4 − 0.775 V

VR10 w/ Legacy SS/VR11 Threshold 2.7 − 3.1 V

Internal DAC Slew Rate Limiter

Positive Slew Rate Limit VID step range of +10mV to +500mV − 7.3 − mV/s

Negative Slew Rate Limit VID step range of −10mV to −500mV − 7.3 − mV/s

Voltage Reference (V

Output Voltage 0 < I

REF

Input Supply Current

VCC Operating Current FSW = 400 kHz − 20 − mA

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

)

REF

< 250 A 3.92 4.00 4.08 V

VREF

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

http://onsemi.com

Page 15

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter UnitsMaxTypMinTest Conditions

VR10 DAC

System Voltage Accuracy 1.0 V < DAC < 1.6 V

No−Load Offset Voltage from Nominal DAC Specification

VR10 VID Codes

VID4

400 mV

0 1 0 1 0 1 1 1.60000

0 1 0 1 0 1 0 1.59375

0 1 0 1 1 0 1 1.58750

0 1 0 1 1 0 0 1.58125

0 1 0 1 1 1 1 1.57500

0 1 0 1 1 1 0 1.56875

0 1 1 0 0 0 1 1.56250

0 1 1 0 0 0 0 1.55625

0 1 1 0 0 1 1 1.55000

0 1 1 0 0 1 0 1.54375

0 1 1 0 1 0 1 1.53750

0 1 1 0 1 0 0 1.53125

0 1 1 0 1 1 1 1.52500

0 1 1 0 1 1 0 1.51875

0 1 1 1 0 0 1 1.51250

0 1 1 1 0 0 0 1.50625

0 1 1 1 0 1 1 1.50000

0 1 1 1 0 1 0 1.49375

0 1 1 1 1 0 1 1.48750

0 1 1 1 1 0 0 1.48125

0 1 1 1 1 1 1 1.47500

0 1 1 1 1 1 0 1.46875

1 0 0 0 0 0 1 1.46250

1 0 0 0 0 0 0 1.45625

1 0 0 0 0 1 1 1.45000

1 0 0 0 0 1 0 1.44375

1 0 0 0 1 0 1 1.43750

1 0 0 0 1 0 0 1.43125

1 0 0 0 1 1 1 1.42500

1 0 0 0 1 1 0 1.41875

1 0 0 1 0 0 1 1.41250

1 0 0 1 0 0 0 1.40625

1 0 0 1 0 1 1 1.40000

1 0 0 1 0 1 0 1.39375

1 0 0 1 1 0 1 1.38750

1 0 0 1 1 0 0 1.38125

1 0 0 1 1 1 1 1.37500

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

0.8 V < DAC < 1.0 V

0.5 V < DAC < 0.8 V

With CS Input Vin = 0 V −19 mV

VID3

200 mV

VID2

100 mV

VID1

50 mV

VID0

25 mV

= 0.1 F, FSW = 400 kHz, unless otherwise stated)

VCC

− − ±0.75 ±7.0 ±8.0

VID5

12.5 mV

VID6

6.25 mV

% mV mV

Nominal DAC

Voltage (V)

http://onsemi.com

Page 16

NCP5388

VR10 VID Codes

VID4

400 mV

1 0 0 1 1 1 0 1.36875

1 0 1 0 0 0 1 1.36250

1 0 1 0 0 0 0 1.35625

1 0 1 0 0 1 1 1.35000

1 0 1 0 0 1 0 1.34375

1 0 1 0 1 0 1 1.33750

1 0 1 0 1 0 0 1.33125

1 0 1 0 1 1 1 1.32500

1 0 1 0 1 1 0 1.31875

1 0 1 1 0 0 1 1.31250

1 0 1 1 0 0 0 1.30625

1 0 1 1 0 1 1 1.30000

1 0 1 1 0 1 0 1.29375

1 0 1 1 1 0 1 1.28750

1 0 1 1 1 0 0 1.28125

1 0 1 1 1 1 1 1.27500

1 0 1 1 1 1 0 1.26875

1 1 0 0 0 0 1 1.26250

1 1 0 0 0 0 0 1.25625

1 1 0 0 0 1 1 1.25000

1 1 0 0 0 1 0 1.24375

1 1 0 0 1 0 1 1.23750

1 1 0 0 1 0 0 1.23125

1 1 0 0 1 1 1 1.22500

1 1 0 0 1 1 0 1.21875

1 1 0 1 0 0 1 1.21250

1 1 0 1 0 0 0 1.20625

1 1 0 1 0 1 1 1.20000

1 1 0 1 0 1 0 1.19375

1 1 0 1 1 0 1 1.18750

1 1 0 1 1 0 0 1.18125

1 1 0 1 1 1 1 1.17500

1 1 0 1 1 1 0 1.16875

1 1 1 0 0 0 1 1.16250

1 1 1 0 0 0 0 1.15625

1 1 1 0 0 1 1 1.15000

1 1 1 0 0 1 0 1.14375

1 1 1 0 1 0 1 1.13750

1 1 1 0 1 0 0 1.13125

1 1 1 0 1 1 1 1.12500

1 1 1 0 1 1 0 1.11875

1 1 1 1 0 0 1 1.11250

1 1 1 1 0 0 0 1.10625

1 1 1 1 0 1 1 1.10000

1 1 1 1 0 1 0 1.09375

1 1 1 1 1 0 1 OFF

1 1 1 1 1 0 0 OFF

VID3

200 mV

VID2

100 mV

VID1

50 mV

VID0

25 mV

VID5

12.5 mV

VID6

6.25 mV

Nominal DAC

Voltage (V)

http://onsemi.com

Page 17

NCP5388

VR10 VID Codes

VID4

400 mV

1 1 1 1 1 1 1 OFF

1 1 1 1 1 1 0 OFF

0 0 0 0 0 0 1 1.08750

0 0 0 0 0 0 0 1.08125

0 0 0 0 0 1 1 1.07500

0 0 0 0 0 1 0 1.06875

0 0 0 0 1 0 1 1.06250

0 0 0 0 1 0 0 1.05625

0 0 0 0 1 1 1 1.05000

0 0 0 0 1 1 0 1.04375

0 0 0 1 0 0 1 1.03750

0 0 0 1 0 0 0 1.03125

0 0 0 1 0 1 1 1.02500

0 0 0 1 0 1 0 1.01875

0 0 0 1 1 0 1 1.01250

0 0 0 1 1 0 0 1.00625

0 0 0 1 1 1 1 1.00000

0 0 0 1 1 1 0 0.99375

0 0 1 0 0 0 1 0.98750

0 0 1 0 0 0 0 0.98125

0 0 1 0 0 1 1 0.97500

0 0 1 0 0 1 0 0.96875

0 0 1 0 1 0 1 0.96250

0 0 1 0 1 0 0 0.95625

0 0 1 0 1 1 1 0.95000

0 0 1 0 1 1 0 0.94375

0 0 1 1 0 0 1 0.93750

0 0 1 1 0 0 0 0.93125

0 0 1 1 0 1 1 0.92500

0 0 1 1 0 1 0 0.91875

0 0 1 1 1 0 1 0.91250

0 0 1 1 1 0 0 0.90625

0 0 1 1 1 1 1 0.90000

0 0 1 1 1 1 0 0.89375

0 1 0 0 0 0 1 0.88750

0 1 0 0 0 0 0 0.88125

0 1 0 0 0 1 1 0.87500

0 1 0 0 0 1 0 0.86875

0 1 0 0 1 0 1 0.86250

0 1 0 0 1 0 0 0.85625

0 1 0 0 1 1 1 0.85000

0 1 0 0 1 1 0 0.84375

0 1 0 1 0 0 1 0.83750

0 1 0 1 0 0 0 0.83125

VID3

200 mV

VID2

100 mV

VID1

50 mV

VID0

25 mV

VID5

12.5 mV

VID6

6.25 mV

Nominal DAC

Voltage (V)

http://onsemi.com

Page 18

NCP5388

ELECTRICAL CHARACTERISTICS

(0°C < T

< 70°C; 0°C < T

Parameter Test Conditions Min Ty p Max Units

VR 11 DAC

System Voltage Accuracy 1.0 V < DAC < 1.6 V

No−Load Offset Voltage from Nominal DAC Specification

Table 2: VR11 VID Codes

VID7

800 mV

0 0 0 0 0 0 0 0 OFF 00

0 0 0 0 0 0 0 1 OFF 01

0 0 0 0 0 0 1 0 1.60000 02

0 0 0 0 0 0 1 1 1.59375 03

0 0 0 0 0 1 0 0 1.58750 04

0 0 0 0 0 1 0 1 1.58125 05

0 0 0 0 0 1 1 0 1.57500 06

0 0 0 0 0 1 1 1 1.56875 07

0 0 0 0 1 0 0 0 1.56250 08

0 0 0 0 1 0 0 1 1.55625 09

0 0 0 0 1 0 1 0 1.55000 0A

0 0 0 0 1 0 1 1 1.54375 0B

0 0 0 0 1 1 0 0 1.53750 0C

0 0 0 0 1 1 0 1 1.53125 0D

0 0 0 0 1 1 1 0 1.52500 0E

0 0 0 0 1 1 1 1 1.51875 0F

0 0 0 1 0 0 0 0 1.51250 10

0 0 0 1 0 0 0 1 1.50625 11

0 0 0 1 0 0 1 0 1.50000 12

0 0 0 1 0 0 1 1 1.49375 13

0 0 0 1 0 1 0 0 1.48750 14

0 0 0 1 0 1 0 1 1.48125 15

0 0 0 1 0 1 1 0 1.47500 16

0 0 0 1 0 1 1 1 1.46875 17

0 0 0 1 1 0 0 0 1.46250 18

0 0 0 1 1 0 0 1 1.45625 19

0 0 0 1 1 0 1 0 1.45000 1A

0 0 0 1 1 0 1 1 1.44375 1B

0 0 0 1 1 1 0 0 1.43750 1C

0 0 0 1 1 1 0 1 1.43125 1D

0 0 0 1 1 1 1 0 1.42500 1E

0 0 0 1 1 1 1 1 1.41875 1F

0 0 1 0 0 0 0 0 1.41250 20

0 0 1 0 0 0 0 1 1.40625 21

0 0 1 0 0 0 1 0 1.40000 22

0 0 1 0 0 0 1 1 1.39375 23

0 0 1 0 0 1 0 0 1.38750 24

VID6

400 mV

< 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; C

0.8 V < DAC < 1.0 V

0.5 V < DAC < 0.8 V

With CS Input Vin = 0 V −19 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

= 0.1 F, unless otherwise stated)

VCC

− − ±0.75

VID1

12.5 mV

VID0

6.25 mV

±7.0 ±8.0

Nominal

DAC

Voltage (V)

% mV mV

HEX

http://onsemi.com

Page 19

NCP5388

Table 2: VR11 VID Codes

VID7

800 mV

0 0 1 0 0 1 0 1 1.38125 25

0 0 1 0 0 1 1 0 1.37500 26

0 0 1 0 0 1 1 1 1.36875 27

0 0 1 0 1 0 0 0 1.36250 28

0 0 1 0 1 0 0 1 1.35625 29

0 0 1 0 1 0 1 0 1.35000 2A

0 0 1 0 1 0 1 1 1.34375 2B

0 0 1 0 1 1 0 0 1.33750 2C

0 0 1 0 1 1 0 1 1.33125 2D

0 0 1 0 1 1 1 0 1.32500 2E

0 0 1 0 1 1 1 1 1.31875 2F

0 0 1 1 0 0 0 0 1.31250 30

0 0 1 1 0 0 0 1 1.30625 31

0 0 1 1 0 0 1 0 1.30000 32

0 0 1 1 0 0 1 1 1.29375 33

0 0 1 1 0 1 0 0 1.28750 34

0 0 1 1 0 1 0 1 1.28125 35

0 0 1 1 0 1 1 0 1.27500 36

0 0 1 1 0 1 1 1 1.26875 37

0 0 1 1 1 0 0 0 1.26250 38

0 0 1 1 1 0 0 1 1.25625 39

0 0 1 1 1 0 1 0 1.25000 3A

0 0 1 1 1 0 1 1 1.24375 3B

0 0 1 1 1 1 0 0 1.23750 3C

0 0 1 1 1 1 0 1 1.23125 3D

0 0 1 1 1 1 1 0 1.22500 3E

0 0 1 1 1 1 1 1 1.21875 3F

0 1 0 0 0 0 0 0 1.21250 40

0 1 0 0 0 0 0 1 1.20625 41

0 1 0 0 0 0 1 0 1.20000 42

0 1 0 0 0 0 1 1 1.19375 43

0 1 0 0 0 1 0 0 1.18750 44

0 1 0 0 0 1 0 1 1.18125 45

0 1 0 0 0 1 1 0 1.17500 46

0 1 0 0 0 1 1 1 1.16875 47

0 1 0 0 1 0 0 0 1.16250 48

0 1 0 0 1 0 0 1 1.15625 49

0 1 0 0 1 0 1 0 1.15000 4A

0 1 0 0 1 0 1 1 1.14375 4B

0 1 0 0 1 1 0 0 1.13750 4C

0 1 0 0 1 1 0 1 1.13125 4D

0 1 0 0 1 1 1 0 1.12500 4E

0 1 0 0 1 1 1 1 1.11875 4F

0 1 0 1 0 0 0 0 1.11250 50

0 1 0 1 0 0 0 1 1.10625 51

0 1 0 1 0 0 1 0 1.10000 52

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

DAC

Voltage (V)

HEXNominal

http://onsemi.com

Page 20

NCP5388

Table 2: VR11 VID Codes

VID7

800 mV

0 1 0 1 0 0 1 1 1.09375 53

0 1 0 1 0 1 0 0 1.08750 54

0 1 0 1 0 1 0 1 1.08125 55

0 1 0 1 0 1 1 0 1.07500 56

0 1 0 1 0 1 1 1 1.06875 57

0 1 0 1 1 0 0 0 1.06250 58

0 1 0 1 1 0 0 1 1.05625 59

0 1 0 1 1 0 1 0 1.05000 5A

0 1 0 1 1 0 1 1 1.04375 5B

0 1 0 1 1 1 0 0 1.03750 5C

0 1 0 1 1 1 0 1 1.03125 5D

0 1 0 1 1 1 1 0 1.02500 5E

0 1 0 1 1 1 1 1 1.01875 5F

0 1 1 0 0 0 0 0 1.01250 60

0 1 1 0 0 0 0 1 1.00625 61

0 1 1 0 0 0 1 0 1.00000 62

0 1 1 0 0 0 1 1 0.99375 63

0 1 1 0 0 1 0 0 0.98750 64

0 1 1 0 0 1 0 1 0.98125 65

0 1 1 0 0 1 1 0 0.97500 66

0 1 1 0 0 1 1 1 0.96875 67

0 1 1 0 1 0 0 0 0.96250 68

0 1 1 0 1 0 0 1 0.95625 69

0 1 1 0 1 0 1 0 0.95000 6A

0 1 1 0 1 0 1 1 0.94375 6B

0 1 1 0 1 1 0 0 0.93750 6C

0 1 1 0 1 1 0 1 0.93125 6D

0 1 1 0 1 1 1 0 0.92500 6E

0 1 1 0 1 1 1 1 0.91875 6F

0 1 1 1 0 0 0 0 0.91250 70

0 1 1 1 0 0 0 1 0.90625 71

0 1 1 1 0 0 1 0 0.90000 72

0 1 1 1 0 0 1 1 0.89375 73

0 1 1 1 0 1 0 0 0.88750 74

0 1 1 1 0 1 0 1 0.88125 75

0 1 1 1 0 1 1 0 0.87500 76

0 1 1 1 0 1 1 1 0.86875 77

0 1 1 1 1 0 0 0 0.86250 78

0 1 1 1 1 0 0 1 0.85625 79

0 1 1 1 1 0 1 0 0.85000 7A

0 1 1 1 1 0 1 1 0.84375 7B

0 1 1 1 1 1 0 0 0.83750 7C

0 1 1 1 1 1 0 1 0.83125 7D

0 1 1 1 1 1 1 0 0.82500 7E

0 1 1 1 1 1 1 1 0.81875 7F

1 0 0 0 0 0 0 0 0.81250 80

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

DAC

Voltage (V)

HEXNominal

http://onsemi.com

Page 21

NCP5388

Table 2: VR11 VID Codes

VID7

800 mV

1 0 0 0 0 0 0 1 0.80625 81

1 0 0 0 0 0 1 0 0.80000 82

1 0 0 0 0 0 1 1 0.79375 83

1 0 0 0 0 1 0 0 0.78750 84

1 0 0 0 0 1 0 1 0.78125 85

1 0 0 0 0 1 1 0 0.77500 86

1 0 0 0 0 1 1 1 0.76875 87

1 0 0 0 1 0 0 0 0.76250 88

1 0 0 0 1 0 0 1 0.75625 89

1 0 0 0 1 0 1 0 0.75000 8A

1 0 0 0 1 0 1 1 0.74375 8B

1 0 0 0 1 1 0 0 0.73750 8C

1 0 0 0 1 1 0 1 0.73125 8D

1 0 0 0 1 1 1 0 0.72500 8E

1 0 0 0 1 1 1 1 0.71875 8F

1 0 0 1 0 0 0 0 0.71250 90

1 0 0 1 0 0 0 1 0.70625 91

1 0 0 1 0 0 1 0 0.70000 92

1 0 0 1 0 0 1 1 0.69375 93

1 0 0 1 0 1 0 0 0.68750 94

1 0 0 1 0 1 0 1 0.68125 95

1 0 0 1 0 1 1 0 0.67500 96

1 0 0 1 0 1 1 1 0.66875 97

1 0 0 1 1 0 0 0 0.66250 98

1 0 0 1 1 0 0 1 0.65625 99

1 0 0 1 1 0 1 0 0.65000 9A

1 0 0 1 1 0 1 1 0.64375 9B

1 0 0 1 1 1 0 0 0.63750 9C

1 0 0 1 1 1 0 1 0.63125 9D

1 0 0 1 1 1 1 0 0.62500 9E

1 0 0 1 1 1 1 1 0.61875 9F

1 0 1 0 0 0 0 0 0.61250 A0

1 0 1 0 0 0 0 1 0.60625 A1

1 0 1 0 0 0 1 0 0.60000 A2

1 0 1 0 0 0 1 1 0.59375 A3

1 0 1 0 0 1 0 0 0.58750 A4

1 0 1 0 0 1 0 1 0.58125 A5

1 0 1 0 0 1 1 0 0.57500 A6

1 0 1 0 0 1 1 1 0.56875 A7

1 0 1 0 1 0 0 0 0.56250 A8

1 0 1 0 1 0 0 1 0.55625 A9

1 0 1 0 1 0 1 0 0.55000 AA

1 0 1 0 1 0 1 1 0.54375 AB

1 0 1 0 1 1 0 0 0.53750 AC

1 0 1 0 1 1 0 1 0.53125 AD

1 0 1 0 1 1 1 0 0.52500 AE

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

DAC

Voltage (V)

HEXNominal

http://onsemi.com

Page 22

NCP5388

Table 2: VR11 VID Codes

VID7

800 mV

1 0 1 0 1 1 1 1 0.51875 AF

1 0 1 1 0 0 0 0 0.51250 B0

1 0 1 1 0 0 0 1 0.50625 B1

1 0 1 1 0 0 1 0 0.50000 B2

1 1 1 1 1 1 1 0 OFF FE

1 1 1 1 1 1 1 1 OFF FF

VID6

400 mV

VID5

200 mV

VID4

100 mV

VID3

50 mV

VID2

25 mV

VID1

12.5 mV

VID0

6.25 mV

DAC

Voltage (V)

OFF B3 to FD

HEXNominal

http://onsemi.com

Page 23

NCP5388

TYPICAL CHARACTERISTICS

13.6

13.4

13.2

13.0

12.8

, IC QUIESCENT CURRENT (mA)

12.6 0

10 20 30 40

TA, AMBIENT TEMPERATURE (°C)

Figure 5. IC Quiescent Current vs. Ambient

Temperature

0.0198

0.0196

0.0194

0.0192

0.0190

0.0188

DAC OFFSET

0.0186

0.0184

0.0182

0.0180

, UNDERVOLTAGE LOCKOUT

THRESHOLD VOLTAGE (V)

50 60 70

0 20 3040506070

Figure 6. VCC Undervoltage Lockout

Threshold Voltage vs. Ambient Temperature

25°C

0°C

70°C

0.6

0.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

VID

VCC Increasing Voltage

VCC Decreasing Voltage

TA, AMBIENT TEMPERATURE (°C)

1.5 1.6

Figure 7. Typical DAC Voltage Offset vs.

Temperature

http://onsemi.com

Page 24

NCP5388

FUNCTIONAL DESCRIPTION

General

The NCP5388 dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current VR10 or VR11 CPU power system. The IC consists of the following blocks: Precision Programmable DAC, Differential Remote Voltage Sense Amplifier, High Performance Voltage Error Amplifier, Differential Current Feedback Amplifiers, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft−Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor.

Remote Output Sensing Amplifier (RSA)

A true differential amplifier allows the NCP5388 to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VS+, and the Vcore ground reference point to VS−. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage to allow both positive and negative error voltages.

Precision Programmable DAC

A precision programmable DAC is provided. This DAC has 0.75% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support either VR10 or VR11 specifications. A program selection pin is provided to accomplish this. This pin also sets the startup mode of operation. Connect this pin to 1.25 V to select the VR11 DAC table, and the VR11 startup mode. Connect this pin to ground to select the VR10 DAC table and the VR11 startup mode. Connect this pin to VREF to select the VR10 DAC table and the VR10 startup mode.

High Performance Voltage Error Amplifier

The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as a voltage regulator for VR10 or VR11, a capacitor from COMP to VFB is required for stable unity gain test configurations.

Gate Driver Outputs and 2/3/4 Phase Operation

The part can be configured to run in 2−, 3−, or 4−phase mode. In 2−phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2−phase Applications Schematic. In 3−phase mode, gate output G4 must be grounded as shown in the 3−phase Applications Schematic. In 4−phase mode all 4 gate outputs are used as

shown in the 4−phase Applications Schematic. The following truth table summarizes the modes of operation:

Gate Output Connections

Mode

2−Phase Normal OPEN Normal OPEN

3−Phase Normal Normal Normal GND

4−Phase Normal Normal Normal Normal

G1 G2 G3 G4

These are the only allowable connection schemes to

program the modes of operation.

Differential Current Sense Amplifiers

Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase

is unused, the differential inputs to that phase’s current sense amplifier must be shorted together and connected to V

as shown in the 2− and 3−phase Application

CCP

Schematics.

A voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. The output of the current sense amplifiers are used to control three functions. First, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. In this function, all of the current sense outputs are summed so that the total output current is used for output voltage positioning. Second, the output signal is fed to the current limit circuit. This again is the summed current of all phases in operation. Finally, the individual phase current is connected to the PWM comparator. In this way current balance is accomplished.

Oscillator and Triangle Wave Generator

A programmable precision oscillator is provided. The oscillator ’s frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 1.0 MHz/phase. The oscillator generates up to 4 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2−, 3−, and 4−phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively.

http://onsemi.com

Page 25

NCP5388

PWM Comparators with Hysteresis

Four PWM comparators receive the error amplifier output signal at their noninverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it’s inverting input. The output of the comparator generates the PWM outputs G1, G2, G3, and G4.

During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by V

. During a transient event,

out/Vin

both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave.

PROTECTION FEATURES

Undervoltage Lockout

An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft−start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft−start.

Overcurrent Shutdown

A programmable overcurrent function is incorporated within the IC. A comparator and latch makeup this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels – effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the current sense amplifiers. The overcurrent latch is set when the current

information exceeds the voltage at the ILIM pin. The outputs are immediately disabled, the VR_RDY and DRVON pins are pulled low, and the soft−start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re−applied, or the ENABLE input is brought low and then high.

Overvoltage Protection and Power Good Monitor

An output voltage monitor is incorporated. During normal operation, if the voltage at the DIFFOUT pin exceeds 1.3 V, the VR_RDY pin goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. During normal operation, if the output voltage falls more than 300 mV below the DAC setting, the VR_RDY pin will be set low until the output rises.

Soft−Start

The NCP5388 incorporates an externally programmable soft−start. The soft−start circuit works by controlling the ramp−up of the DAC voltage during powerup. The initial soft−start pin voltage is 0 V. The soft−start circuitry clamps the DAC input of the Remote Sense Amplifier to the SS pin voltage until the SS pin voltage exceeds the DAC setting minus VID offset. The soft−start pin is pulled to 0 V if there is an overcurrent shutdown, if the ENABLE pin is low, if VCC is below the UVLO threshold, or if an overvoltage condition exists.

There are two possible soft−start modes: Legacy VR10 and VR11. VR10 mode simply ramps Vcore from 0 V directly to the DAC setting at the rate set by the capacitor connected to the SS pin. The VR11 mode ramps Vcore to

1.1 V at the SS capacitor charge rate, pauses at 1.1 V for 170 s, reads the VID pins to determine the DAC setting, then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of 7.3 mV/s. Typical VR10 and VR11 soft−start sequences are shown in the following graphs.

http://onsemi.com

Page 26

NCP5388

2.4

2.2

2.0

1.8

1.6

1.4

1.2

VOLTAGE

1.0

0.8

0.6

0.4

0.2

TIME

Figure 8. Typical VR10 Soft−Start Sequence to Vcore = 1.3 V

2.4

2.2

2.0

1.8

1.6

1.4

1.2

VOLTAGE

1.0

0.8

0.6

0.4

0.2

Boot Voltage

Boot

Dwell Time

TIME

VID Setting

Vcore Voltage SS Pin Voltage

VID Setting

NCP5388 Internal Dynamic VID Rate Limit

Vcore Voltage SS Pin Voltage

Figure 9. Typical VR11 Soft−Start Sequence to Vcore = 1.3 V

http://onsemi.com

Page 27

NCP5388

APPLICATION INFORMATION

The NCP5388 is a high performance multiphase controller optimized to meet the Intel VR11 Specifications. The demo board for the NCP5388 is available by request. It is configured as a four phase solution with decoupling designed to provide a 1.0 m load line under a 100 A step load. A schematic is available upon request from ON Semiconductor.

Startup Procedure

The demo board comes with a Socket 775 and requires an Intel dynamic load tool (VTT Tool) available through a third party supplier, Cascade Systems. The web page is http://www.cascadesystems.net/.

Start by installing the test tool software. It’s best to power the test tool from a separate ATX power supply. The test tool should be set to a valid VID code of 0.5 V or above in−order for the controller to start. Consult the VTT help manual for more detailed instructions.

Startup Sequence

1. Make sure the VTT software is installed.

2. Powerup the PC or Laptop do not start the VTT software.

3. Insert the VTT Test Tool adapter into the socket and lock it down.

4. Inset the socket saver pin field into the bottom of the VTT test tool.

5. Carefully line up the tool with the socket in the board and press tool into the board.

6. Connect the scope probe, or DMM to the voltage sense lines on the test tool. When using a scope probe it is best to isolate the scope from the AC ground. Make the ground connection on the scope probe as short as possible.

7. Connect the first ATX supply to the VTT tool.

8. Powerup the first ATX supply to the VTT tool.

9. Start the VTT tool software in VR11 mode with the current limit set to 150 A.

10. Using the VTT tool software, select a VID code that is 0.5 V or above.

11. Connect the second ATX supply to the demo board.

12. Set the VID DIP switches. All the VID switches should be up or open.

13. Set the VR_ENABLE DIP switch down or closed.

14. Set the VR10 DIP switch up or open.

15. Set the VID_SEL switch up or open.

16. Start the second ATX supply by turning it on and setting the PSON DIP switch low. The green VID lights should light up to match the VTT tool VID setting.

17. Set the VR_ENABLE DIP switch up to start the NCP5388.

18. Check that the output voltage is about 19 mV below the VID setting.

Step Load Testing

The VTT tool is used to generate the high di/dt step load. Select the dynamic loading option in the VTT test tool software. Set the desired step load size, frequency, duty, and slew rate. See Figures 10 and 11.

Figure 10. Typical Step Load Response

Figure 11. Typical Load Release Event

http://onsemi.com

Page 28

NCP5388

Dynamic VID Testing

The VTT tool provides for VID stepping based on the Intel Requirements. Select the Dynamic VID option. Before enabling the test set the lowest VID to 0.5 V or greater and set the highest VID to a value that is greater than the lowest VID selection, then enable the test. See Figures 12 through 14.

Figure 12. 1.6 to 0.5 Dynamic VID Response

Design Methodology

Decoupling the VCC Pin on the IC

An RC input filter is required as shown in the VCC pin to minimize supply noise on the IC. The resistor should be sized such that it does not generate a large voltage drop between the 12 V supply and the IC. See the schematic values.

Understanding Soft−Start

The controller supports two different startup routines. A legacy VR10 ramp to the initial VID code, or a VR11 Ramp to the 1.1 V VID code, with a pause to capture the VID code then resume ramping to target value based on an internal slew rate limit. See Figures 15 and 16. The controller is designed to regulate to the voltage on the SS pin until it reaches the internal DAC voltage. The soft−start cap sets the initial ramp rate using a typical 5.0 A current. The typical value to use for the soft−start cap (SS), is typically set to 0.01  F. This results in a ramp time to 1.1 V of 2.2 ms based on equation 1.

Css^ i

1.1 · V

2.2 · ms

Css+ 0.01 · F

and iss+ 5·A

(eq. 1)

Figure 13. Dynamic VID Settling Time Rising

Figure 14. Dynamic VID Settling Time Falling

Figure 15. VR11 Startup

Figure 16. VR10 Legacy Startup

http://onsemi.com

Page 29

NCP5388

Programming the Current Limit and the Oscillator Frequency

The demo board is set for an operating frequency of approximately 300 kHz. The OSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider.

The series resistors RLIM1 and RLIM2 sink current to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the resistance. The resistance may be estimated by equation 2 or 3 depending on the phase count.

100

ROSC (kOhms)

100

200

300

400

500

600

700

32.36 k ^

ROSC +

4 Phase Mode

3 Phase Mode

800

10.14 10 300 · k

4 Phase Mode

10.14 10 Frequency

3 Phase Mode

9.711 10 Frequency

900

1000

* 1440

* 1111

(eq. 2)

(eq. 3)

Frequency (kHz)

Figure 17. ROSC vs. Phase Frequency

The current limit function is based on the total sensed current of all phases multiplied by a gain of 5.94. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum

Calculate the current limit voltage:

ILIMIT

^ 5.94 ·ǒI

MIN_OCP

· DCR

Tmax

)

Solve for the individual resistors:

RLIM2 +

Final Equation for the Current Limit Threshold

LIMIT(Tinductor

) ^

5.94 · (DCR

ILIMIT·ROSC

2·V

2·V·RLIM2

RLIM1)RLIM2

·(1) 0.00393 · C−1(T

25C

) 0.02

The inductors on the demo board have a DCR at 25°C of

0.75 m. Selecting the closest available values of 16.9 k for RLIM1 and 15.8 k for RLIM2 yield a nominal operating frequency of 305 kHz and an approximate current limit of 180 A at 100°C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no−load offset of approximately 1.3 V.

current limit based on the expected average maximum temperature of the inductor windings.

DCR

50C

2·Vin·F

Inductor

· Vout

−25 · C)))

DCR

(1 ) 0.00393 · C−1(T

Vin−Vout

RLIM1 + R

Tmax

* (N−1) ·

Vout

2·Vin·F

+ DCR

OSC−RLIM2

25C

Vout

Vin−Vout

Tmax

−25 · C))

* 0.02

* (N−1) ·

Inductor Selection

When using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. The inductor also must not go into hard saturation before current limit trips. The demo board includes a four phase output filter using the T50−8 core from Micrometals with 4turns and a DCR target of 0.75 m @ 25°C. Smaller DCR values can be used, however, current sharing accuracy and droop accuracy decrease as DCR decreases. Use the excel spreadsheet for regulation accuracy calculations for a specific value of DCR.

(eq. 4)

(eq. 5)

(eq. 6)

Vout

(eq. 7)

http://onsemi.com

Page 30

NCP5388

Inductor Current Sense Compensation

The NCP5388 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of

Rsense(T) +

Figure 18.

0.47 · F · DCR

The demoboard inductor measured 350 nH and 0.75 m at room temp. The actual value used for Rsense was 953  which matches the equation for Rsense at approximately 50C. Because the inductor value is a function of load and

the current flowing through the inductor’s DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.47 F capacitor for C and then solve for R.

·(1) 0.00393 · C−1·(T−25 · C))

25C

inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution.

It is desirable to keep the Rsense resistor value below

1.0 k whenever possible by increasing the capacitor values in the inductor compensation network. The bias current flowing out of the current sense pins is approximately 100 nA. This current flows through the current sense resistor and creates an offset at the capacitor which will appear as a load current at the Vdroop pin. A 1.0 k resistor will keep this offset at the droop pin below 2.5 mV.

Simple Average PSPICE Model

A simple state average model shown in Figure 19 can be used to determine a stable solution and provide insight into the control system.

(eq. 8)

−

VRamp_min

1.3 V

−

1E3

Vin 12

4.3 kCF1.5 n

Unity Gain

BW = 15 MHz

10.6 n

−

GAIN = 6

CFB1

680 p

Voff

DCR

(0.85e−3/4)

RFB1

100

RFB

1 k

22 p

1 k

(250e−9/4)

Voff

RDRP

5.11 k

−

LBRD

100 p CBulk (560e−6*10)

ESRBulk (7e−3/10)

ESLBulk (3.5e−9/10)

1.3

−

RBRD

0.75 m

Voffset

−

CCer (22e−6*18)

ESRCer (1.5e−3/18)

ESLCer (1.5e−9/18)

VDAC

1.25 V

1Aac 0Adc

−

I1 = 10 I2 = 110 TD = 10u TR = 50n TF = 50n PW = 40u PER = 80u

Vout

−

Figure 19.

http://onsemi.com

Page 31

NCP5388

A complex switching model is available by request which includes a more detailed board parasitic for this demo board.

Compensation and Output Filter Design

The values shown on the demo board are a good place to start for any similar output filter solution. The dynamic performance can then be adjusted by swapping out various individual components.

If the required output filter and switching frequency are significantly different, it’s best to use the available PSPICE models to design the compensation and output filter from scratch.

The design target for this demo board was 1.0 m out to

2.0 MHz. The phase switching frequency is currently set to 300 kHz. It can easily be seen that the board impedance of

0.75 m between the load and the bulk capacitance has a large effect on the output filter. In this case the ten 560 F

1/(2*PI*CFB1*(RFB1+RFB))

1/(2*PI*CF*RF)

1/(2*PI*(RBRD+ESRBulk)*CBulk)

−20

RF/RFB

bulk capacitors have an ESR of 7.0 m. Thus the bulk ESR plus the board impedance is 0.7 m + 0.75 m or

1.45 m. The actual output filter impedance does not drop to 1.0 m until the ceramic breaks in at over 375 kHz. The controller must provide some loop gain slightly less than one out to a frequency in excess 300 kHz. At frequencies below where the bulk capacitance ESR breaks with the bulk capacitance, the DC−DC converter must have sufficiently high gain to control the output impedance completely. Standard Type−3 compensation works well with the NCP5388. RFB1 should be kept above 50  for amplifier stability reasons.

The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below 1.0 m. See the example of the locations of the poles and zeros that were set to optimize the model above.

Zout Open Loop

Zout Closed Loop

Open Loop Gain with Current loop Closed

Voltage Loop Compensation Gain

1/(2*PI*RF*CF)

RF/RFB1

Error Amp Open Loop Gain

−40

−60

−80

1mOhm

1/(2*PI*SQRT(ESL_Cer*CCer))

1/(2*PI*CCer*(RBRD+ESRBulk))

−100 100 1000 10000 100000 1000000 10000000

Frequency

Figure 20.

By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk

and ceramic capacitor type output filter.

2 ·CF·RF

2 ·CFBI·(RFBI) RFB)

2 · (RBRD ) ESRBulk) · CBulk

http://onsemi.com

2 · CCer * (RBRD ) ESRBulk)

(eq. 9)

Page 32

NCP5388

RFB is always set to 1.0 k and RFB1 is usually set to 100  for maximum phase boost. The value of RF is typically set to 4.0 k.

Droop Injection and Thermal Compensation

The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This induces an

RRDP determines the target output impedance by the

basic equation:

Vout

+ Zout +

Iout

RDRP +

The value of the inductor’s DCR varies with temperature

according to the following equation 10:

offset which is proportional to the output current thereby forcing the controlled resistive output impedance.

DCR

The system can be thermally compensated to cancel this effect out to a great degree by adding an NTC (negative temperature coefficient resistor) in parallel with RFB to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the

Tmax

+ DCR

·(1) 0.00393 · C−1(T

25C

NTC helps make the device appear more linear with temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended value for RISO1 and RISO2 is approximately 1.0 k.

Tmax

−25 · C))

The output impedance varies with inductor temperature by the equation:

Zout(T) +

RFB · DCR

·(1) 0.00393 · C−1(T

25C

Rdroop

−25C)) · 5.94

max

By including the NTC RT2 and the series isolation resistors the new equation becomes:

Zout(T) +

RFB · (RISO1)RT2(T))RISO2)

RFB)RISO1)RT2(T))RISO2

· DCR

·(1) 0.00393 · C−1(T

25C

Rdroop

RFB · DCR · 5.94

RDRP

RFB · DCR · 5.94

Zout

−25C)) · 5.94

max

(eq.

10)

(eq. 11)

(eq. 12)

(eq. 13)

The typical equation of a NTC is based on a curve fit equation 13.

RT2(T) + RT2

25C

·e

ƪǒ



273 )T

298

(eq. 14)

The demo board is populated with a 10 k NTC with a Beta of 4300. Figure 21 shows the uncompensated and compensated output impedance versus temperature.

Figure 21. Uncompensated and Compensated Output

Impedance vs. Temperature

ON Semiconductor provides an excel spreadsheet to help with the selection of the NTC. The actual selection of the NTC will be effected by the location of the output inductor with respect to the NTC and airflow, and should be verified with an actual system thermal solution.

VRHOT and VRFAN

Thermal monitoring provides two threshold sensitive comparators for thermal monitoring. The circuit consists of two comparators that compare the voltage on the NTC pin to an internal resistor divider connected to VREF. By powering the external temperature sense divider with VREF the tolerance of the VREF voltage is canceled out. The data sheet specifications for the thresholds are shown as ratios with respect to VREF.

VR_FAN Upper Threshold Ratio = 0.3625

VR_FAN Lower Threshold Ratio = 0.3025

VR_HOT Upper Threshold Ratio = 0.2815

VR_HOT Lower Threshold Ratio = 0.2190

The following equations can be used to find the temperature trip points.

RT1(T) + RT1

Ratio

NTC

(T) :

25C

RNTC1 )RNTC2 ) RT1(T)

273 )T

RNTC2 ) RT1(T)

ƪǒ



·e

298

(eq. 15)

(eq. 16)

The demo board contains a 68 K NTC for RT1 with a Beta of 4750. RNTC1 is populated with 15 k and RNTC2 is populated with a zero ohm resistor. Figure 22 is a plot of equation 15. The horizontal trip thresholds intersect the Ratio

NTC

curve.

http://onsemi.com

Page 33

NCP5388

Figure 22.

OVP

The overvoltage protection threshold is not adjustable. OVP protection is enabled as soon as soft−start begins and is disabled when the part is disabled. When OVP is tripped, the controller commands all four gate drivers to enable their low side MOSFETs, and VR_RDY transitions low. In order to recover from an OVP condition, VCC must fall below the UVLO threshold. See the state diagram for

further details. The OVP circuit monitors the output of DIFFOUT. If the DIFFOUT signal reaches 180 mV above the nominal 1.3 V offset the OVP will trip. The DIFFOUT signal is the difference between the output voltage and the DAC voltage plus the 1.3 V internal offset. This results in the OVP tracking the DAC voltage even during a dynamic change in the VID setting during operation.

Gate Driver and MOSFET Selection

ON Semiconductor provides the companion gate driver IC (NCP3418B). The NCP3418B driver is optimized to work with a range of MOSFETs commonly used in CPU applications. The NCP3418B provides special functionality and is required for the high performance dynamic VID operation of the part. Contact your local ON Semiconductor applications engineer for MOSFET recommendations.

Board Stack−Up

The demo board follows the recommended Intel Stack−up and copper thickness as shown.

Figure 23.

Board Layout

A complete Allegro ATX and BTX demo board layout file and schematics are available by request at www.onsemi.com and can be viewed using the Allegro Free Physical Viewer 15.x from the Cadence website http://www.cadence.com/.

http://onsemi.com

Close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller IC. Routing should follow the demo board example. For further information or layout review contact ON Semiconductor.

Page 34

2 X

LOCATION

0.15 C

2 X

PIN ONE

0.15 C

TOP VIEW

NCP5388

PACKAGE DIMENSIONS

40 PIN QFN, 7x7

MN SUFFIX

CASE 488AG−01

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETER.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF

b 0.18 0.30

D 7.00 BSC D2 5.50 5.70

E 7.00 BSC

e 0.50 BSC

L 0.30 0.50

k 0.20 −−−

5.70E2 5.50

0.10 C

(A3)

40 X

0.08 C

SEATING PLANE

40 X

SIDE VIEW

EXPOSED PAD

40 X

A0.10 BC

0.05 C

BOTTOM VIEW

Pentium is a registered trademark of Intel Corporation.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc Sales Representative

NCP5388/D