Seiko Epson S1C17 Series Manual

CMOS 16-BIT SINGLE CHIP MICROCOMPUTER

S1C17 Family

S1C17 Core Manual

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

Devices

S1 C 17xxx F 00E1

Packing specifications

00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G: TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q: TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed

Specification

Package

D: die form; F: QFP, B: BGA

Model number

Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1 C 17000 H2 1

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx: Emulation memory for external ROM Tx : A socket for mounting

Cx : Compiler package Sx : Middleware package

Corresponding model number

17xxx: for S1C17xxx

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

00

Configuration of product number

– Contents –

CONTENTS

1 Summary .......................................................................................................................1-

1.1 Features ...........................................................................................................................1-1

2 Registers .......................................................................................................................2-1

2.1 General-Purpose Registers (R0–R7) ...............................................................................2-1

2.2 Program Counter (PC) .....................................................................................................2-1

2.3 Processor Status Register (PSR) .....................................................................................2-2

2.4 Stack Pointer (SP) ............................................................................................................2-4

2.4.1 About the Stack Area .........................................................................................2-4

2.4.2 SP Operation at Subroutine Call/Return ............................................................2-

2.4.3 SP Operation when an Interrupt Occurs ............................................................2-

2.4.4 Saving/Restoring Register Data Using a Load Instruction ................................2-

2.5 Register Notation and Register Numbers ........................................................................2-

2.5.1 General-Purpose Registers ...............................................................................2-7

2.5.2 Special Registers ...............................................................................................2-

3 Data Formats .................................................................................................................3-1

3.1 Data Formats Handled in Operations Between Registers ...............................................3-1

3.1.1 Unsigned 8-Bit Transfer (Register → Register) ..................................................3-1

3.1.2 Signed 8-Bit Transfer (Register

3.1.

3 16-Bit Transfer (Register → Register) ................................................................3-2

3.1.4 24-Bit Transfer (Register

3.2 Data Formats Handled in Operations Between Memory and a Register .........................3-

3.2.1 Unsigned 8-Bit Transfer (Memory → Register) ..................................................3-3

3.2.2 Signed 8-Bit Transfer (Memory

3.2.3 8-Bit Transfer (Register

3.2.4 16-Bit Transfer (Memory

3.2.5 16-Bit Transfer (Register

3.2.6 32-Bit Transfer (Memory

3.2.7 32-Bit Transfer (Register

→ Memory) ..................................................................3-3

→ Register) ......................................................3-1

→ Register) ................................................................3-2

→ Register) ......................................................3-3

→ Register) ................................................................3-3

→ Memory) ................................................................3-4

→ Register) ................................................................3-4

→ Memory) ................................................................3-4

4 Address Map .................................................................................................................4-1

4.1 Address Space .................................................................................................................4-1

4.2 Processor Information in the Core I/O Area ....................................................................4-2

4.2.1 Trap Table Base Register (TTBR, 0xffff80) .........................................................4-2

4.2.2 Processor ID Register (IDIR, 0xffff84) ...............................................................4-

4.2.3 Debug RAM Base Register (DBRAM, 0xffff90) ..................................................4-

5 Instruction Set ..............................................................................................................5-1

5.1 List of Instructions ............................................................................................................5-1

5.2 Addressing Modes (without ext extension) .....................................................................5-5

5.2.1 Immediate Addressing .......................................................................................5-5

5.2.2 Register Direct Addressing ................................................................................5-

5.2.3 Register Indirect Addressing ..............................................................................5-

5.2.4

Register Indirect Addressing with Post-increment/decrement or Pre-decrement ...

5.2.5 Register Indirect Addressing with Displacement ...............................................5-

5.2.6 Signed PC Relative Addressing ........................................................................5-

5.2.7 PC Absolute Addressing ....................................................................................5-

5-6

1

4 5 6 7

7

2

2 2

5 6

7 7 7

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5.3 Addressing Modes with ext .............................................................................................5-8

5.3.1 Extension of Immediate Addressing ..................................................................5-8

5.3.2 Extension of Register Direct Addressing ...........................................................5-

5.3.3 Extension of Register Indirect Addressing ........................................................5-1

5.3.4 Extension of Register Indirect Addressing with Displacement ..........................5-1

5.3.5 Extension of

5.3.6 Extension of

Signed PC Relative Addressing ...................................................5-11

PC Absolute Addressing ..............................................................5-12

5.4 Data Transfer Instructions ...............................................................................................5-1

5.5 Logical Operation Instructions .........................................................................................5-14

5.6 Arithmetic Operation Instructions ....................................................................................5-15

5.7 Shift and Swap Instructions .............................................................................................5-16

5.8 Branch and Delayed Branch Instructions ........................................................................5-17

5.8.1 Types of Branch Instructions .............................................................................5-17

5.8.2 Delayed Branch Instructions .............................................................................5-2

5.9 System Control Instructions ............................................................................................5-2

5.10 Conversion Instructions .................................................................................................5-23

5.11 Coprocessor Instructions ..............................................................................................5-24

6 Functions ......................................................................................................................6-1

6.1 Transition of the Processor Status ....................................................................................6-1

6.1.1 Reset State ........................................................................................................6-1

6.1.2 Program Execution State ...................................................................................6-

6.1.3 Interrupt Handling ..............................................................................................6-

6.1.4 Debug Interrupt ..................................................................................................6-

6.1.5 HALT and SLEEP Modes ...................................................................................6-

6.2 Program Execution ...........................................................................................................6-

6.2.1 Instruction Fetch and Execution .........................................................................6-2

6.2.2 Execution Cycles and Flags ...............................................................................6-

6.3 Interrupts ..........................................................................................................................6-

6.3.1 Priority of Interrupts ...........................................................................................6-6

6.3.2 Vector Table ........................................................................................................6-

6.3.3 Interrupt Handling ..............................................................................................6-

6.3.4 Reset .................................................................................................................6-

6.3.5 Address Misaligned Interrupt .............................................................................6-

6.3.6 NMI ....................................................................................................................6-

6.3.7 Maskable External Interrupts .............................................................................6-

6.3.8 Software Interrupts ............................................................................................6-

6.3.9 Interrupt Masked Period .....................................................................................6-

6.4 Power-Down Mode ..........................................................................................................6-1

6.5 Debug Circuit ..................................................................................................................6-11

6.5.1 Debugging Functions ........................................................................................6-11

6.5.2 Resource Requirements and Debugging Tools .................................................6-1

6.5.3 Registers for Debugging ...................................................................................6-1

7 Details of Instructions ..................................................................................................7-1

adc %rd, %rs adc/c %rd, %rs adc/nc %rd, %rs adc %rd, imm7

%rd, %rs

add

%rd, %rs

add/c

%rd, %rs

add/nc add %rd,

%rd, %rs

add.a

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............................................................................................................................. 7-

.......................................................................................................................... 7-

............................................................................................................................. 7-

imm7

.......................................................................................................................... 7-

............................................................................................................................. 7-

S1C17 FAMILY S1C17 CORE MANUAL

9

0 1

3

1 2

1 1 1 1 2

3 6

7 7 7 8 8 8 9 9

0

1 2

2 2 2 3 4 4 4 5 6

CONTENTS

add.a/c %rd, %rs add.a/nc

%rd, %rs add.a %rd, add.a

%sp, %rs add.a %sp, and %rd, %rs and/c %rd, %rs and/nc %rd, %rs and %rd, sign7 brk

........................................................................................................................................... 7-12

call %rb call.d %rb call sign10 call.d sign10 calla %rb calla.d %rb calla imm7 calla.d imm7 cmc %rd, %rs cmc/c %rd, %rs cmc/nc %rd, %rs cmc %rd, sign7 cmp %rd, %rs cmp/c %rd, %rs cmp/nc %rd, %rs cmp %rd, sign7 cmp.a %rd, %rs cmp.a/c %rd, %rs cmp.a/nc %rd, %rs cmp.a %rd, imm7

%rd, %rs

cv.ab

l %rd, %rs

cv.a

s %rd, %rs

cv.a

la %rd, %rs

cv.

ls %rd, %rs

cv. di

........................................................................................................................................... 7-28

ei

........................................................................................................................................... 7-29

imm13

ext halt

........................................................................................................................................... 7-31

int imm5 intl imm5, imm3 jpa %rb jpa.d %rb jpa imm7 jpa.d imm7 jpr %rb

%rb

jpr.d jpr sign10

sign10

jpr.d jreq sign7 jreq.d sign7

sign7

jrge

sign7

jrge.d

sign7

jrgt

sign7

jrgt.d jrle sign7

sign7

jrle.d jrlt sign7

............................................................................................................................. 7-

imm7

.......................................................................................................................... 7-

............................................................................................................................ 7-

imm7

......................................................................................................................... 7-

............................................................................................................................ 7-1

......................................................................................................................... 7-1

.................................................................................................................................... 7-1

................................................................................................................................ 7-1

.................................................................................................................................... 7-1

.................................................................................................................................. 7-1

............................................................................................................................ 7-1

......................................................................................................................... 7-1

............................................................................................................................ 7-1

......................................................................................................................... 7-2

............................................................................................................................ 7-2

......................................................................................................................... 7-2

............................................................................................................................ 7-2

................................................................................................................................ 7-3

.................................................................................................................................. 7-3

...................................................................................................................... 7-3

.................................................................................................................................... 7-3

.................................................................................................................................. 7-3

.................................................................................................................................... 7-3

................................................................................................................................ 7-3

.................................................................................................................................. 7-3

.................................................................................................................................. 7-4

6 6 7 8 9

0 0 0 1

3 3 4 4 5 5 6 6 7 7 7 8 9 9 9 0 1 1 1 2 3 4 5 6 7

0

2 3 4 4 5 5 6 6 7 7 8 8 9 9 0 0 1 1 2

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jrlt.d sign7 jrne sign7

sign7

jrne.d

sign7

jruge

sign7

jruge.d jrugt sign7 jrugt.d sign7 jrule sign7

sign7

jrule.d jrult sign7 jrult.d sign7 ld %rd, %rs ld %rd, [%rb] ld %rd, [%rb]+ ld %rd, [%rb]ld %rd, -[%rb] ld %rd, [%sp + imm7] ld %rd, [imm7] ld %rd, sign7 ld [ ld [ ld [ ld -[ ld [%sp + ld [ ld.a %rd, %pc ld.a %rd, %rs ld.a %rd, %sp ld.a %rd, [%rb] ld.a %rd, [%rb]+ ld.a %rd, [%rb]ld.a %rd, -[%rb] ld.a %rd, [%sp] ld.a %rd, [%sp]+ ld.a %rd, [%sp]ld.a %rd, -[%sp] ld.a %rd, [%sp + imm7] ld.a %rd, [imm7] ld.a %rd, imm7 ld.a %sp, %rs ld.a %sp, ld.a [ ld.a [ ld.a [ ld.a -[ ld.a [%sp], %rs ld.a [%sp]+, %rs ld.a [%sp]-, %rs ld.a -[%sp], %rs ld.a [%sp + ld.a [ ld.b %rd, %rs ld.b %rd, [%rb] ld.b %rd, [%rb]+ ld.b %rd, [%rb]ld.b %rd, -[%rb] ld.b %rd, [%sp + imm7] ld.b %rd, [imm7] ld.b [

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.................................................................................................................................. 7-4

............................................................................................................................ 7-4

......................................................................................................................... 7-4

....................................................................................................................... 7-4

........................................................................................................................ 7-4

........................................................................................................... 7-5

....................................................................................................................... 7-5

......................................................................................................................... 7-5

%rb], %rs %rb]+, %rs %rb]-, %rs

%rb], %rs

imm7], %rs

......................................................................................................................... 7-5

....................................................................................................................... 7-5

........................................................................................................................ 7-5

imm7], %rs

........................................................................................................... 7-5

....................................................................................................................... 7-5

........................................................................................................................... 7-5

............................................................................................................................ 7-5

........................................................................................................................... 7-6

......................................................................................................................... 7-6

....................................................................................................................... 7-6

........................................................................................................................ 7-6

......................................................................................................................... 7-6

....................................................................................................................... 7-6

........................................................................................................................ 7-6

........................................................................................................... 7-6

....................................................................................................................... 7-6

......................................................................................................................... 7-6

........................................................................................................................... 7-68

imm7

........................................................................................................................ 7-6

%rb], %rs %rb]+, %rs %rb]-, %rs

%rb], %rs

......................................................................................................................... 7-7

....................................................................................................................... 7-7

........................................................................................................................ 7-7

......................................................................................................................... 7-72

....................................................................................................................... 7-72

........................................................................................................................ 7-72

imm7], %rs

........................................................................................................... 7-7

....................................................................................................................... 7-7

............................................................................................................................ 7-7

......................................................................................................................... 7-7

....................................................................................................................... 7-7

........................................................................................................................ 7-7

........................................................................................................... 7-7

....................................................................................................................... 7-8

%rb], %rs

......................................................................................................................... 7-8

2 3 3 4 4 5 5 6 6 7 7 8 9 9 9 9 1 2 3 4 4 4 4 6 7 8 9 0 1 1 1 1 3 3 3 3 5 6 7

9 0 0 0 0

4 5 6 7 7 7 7 9 0 1

S1C17 FAMILY S1C17 CORE MANUAL

CONTENTS

ld.b [%rb]+, %rs ld.b [ ld.b -[

%rb]-, %rs

%rb], %rs

ld.b [%sp + ld.b [

imm7], %rs ld.ca %rd, %rs ld.ca %rd, imm7 ld.cf %rd, %rs ld.cf %rd, imm7 ld.cw %rd, %rs ld.cw %rd, imm7 ld.ub %rd, %rs ld.ub %rd, [%rb] ld.ub %rd, [%rb]+ ld.ub %rd, [%rb]ld.ub %rd, -[%rb] ld.ub %rd, [%sp + imm7] ld.ub %rd, [imm7] nop

........................................................................................................................................... 7-96

not %rd, %rs not/c %rd, %rs not/nc %rd, %rs not %rd, sign7 or %rd, %rs or/c %rd, %rs or/nc %rd, %rs or %rd, sign7 ret

.......................................................................................................................................... 7-101

ret.d

.......................................................................................................................................... 7-101

retd

.......................................................................................................................................... 7-102

reti

.......................................................................................................................................... 7-103

reti.d

.......................................................................................................................................... 7-103

sa %rd, %rs sa %rd, imm7 sbc %rd, %rs sbc/c %rd, %rs sbc/nc %rd, %rs sbc %rd, imm7 sl %rd, %rs sl %rd, imm7 slp

.......................................................................................................................................... 7-110

sr %rd, %rs sr %rd, imm7 sub %rd, %rs sub/c %rd, %rs sub/nc %rd, %rs sub %rd, imm7 sub.a %rd, %rs sub.a/c %rd, %rs sub.a/nc %rd, %rs sub.a %rd, imm7 sub.a %sp, %rs sub.a %sp, swap %rd, %rs xor %rd, %rs xor/c %rd, %rs xor/nc %rd, %rs xor %rd, sign7

....................................................................................................................... 7-8

........................................................................................................................ 7-8

imm7], %rs

........................................................................................................... 7-8

....................................................................................................................... 7-8

............................................................................................................................ 7-8

......................................................................................................................... 7-8

............................................................................................................................ 7-8

......................................................................................................................... 7-8

............................................................................................................................ 7-8

......................................................................................................................... 7-9

............................................................................................................................ 7-9

......................................................................................................................... 7-9

....................................................................................................................... 7-9

........................................................................................................................ 7-9

........................................................................................................... 7-9

....................................................................................................................... 7-9

............................................................................................................................ 7-9

......................................................................................................................... 7-9

............................................................................................................................ 7-9

........................................................................................................................ 7-10

........................................................................................................................... 7-10

........................................................................................................................ 7-10

........................................................................................................................... 7-10

........................................................................................................................ 7-10

........................................................................................................................... 7-10

........................................................................................................................ 7-10

........................................................................................................................... 7-11

........................................................................................................................ 7-11

........................................................................................................................... 7-11

........................................................................................................................ 7-11

........................................................................................................................... 7-11

........................................................................................................................ 7-11

.......................................................................................................................... 7-11

imm7

....................................................................................................................... 7-11

........................................................................................................................... 7-119

........................................................................................................................... 7-12

........................................................................................................................ 7-12

1 1 1 3 4 5 6 7 8 9 0 1 2 2 2 2 4 5

7 7 7 8 9 9 9

0

4 5 6 6 6 7 8 9

1 2 3 3 3 4 5 5 5 6 7 8

0 0 0 1

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CONTENTS

Appendix List of S1C17 Core Instructions .................................................................. Ap-1

vi

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S1C17 FAMILY S1C17 CORE MANUAL

1 SUMMARY

1 Summary

The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation with a maximum 60 MHz to 90 MHz clock, large address space up to 16M bytes addressable, main instructions executable in one clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications that do not need a lot of data processing power like the S1C33 Cores the high-end processors, such as controllers and sequencers for which an eight-bit CPU is commonly used. The S1C17 Core incorporates a coprocessor interface allowing implementation of additional computing features.

Furthermore, Seiko Epson provides a software development environment similar to the S1C33 Family that includes an IDE work bench, a C compiler, a serial ICE and a debugger, for supporting the developer to develop application software.

1.1 Features

Processor type

• Seiko Epson original 16-bit RISC processor

• 0.35–0.15 µm low power CMOS process technology

Operating-clock frequency

• 90 MHz maximum (depending on the processor model and process technology)

Instruction set

• Code length: 16-bit fixed length

• Number of instructions: 111 basic instructions (184 including variations)

• Execution cycle: Main instructions executed in one cycles

• Extended immediate instructions: Immediate extended up to 24 bits

• Compact and fast instruction set optimized for development in C language

Register set

• Eight 24-bit general-purpose registers

• Two 24-bit special registers

• One 8-bit special register

Memory space and bus

• Up to 16M bytes of memory space (24-bit address)

• Harvard architecture using separated instruction bus (16 bits) and data bus (32 bits)

Interrupts

• Reset, NMI, and 32 external interrupts supported

• Address misaligned interrupt

• Debug interrupt

• Direct branching from vector table to interrupt handler routine

• Programmable software interrupts with a vector number specified (all vector numbers specifiable)

Power saving

• HALT (

• SLEEP (

halt instruction)

slp instruction)

Coprocessor interface

• ALU instructions can be enhanced

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1-1

1 SUMMARY

THIS PAGE IS BLANK.

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S1C17 FAMILY S1C17 CORE MANUAL

2 REGISTERS

R4

R5

R6

R7

R3 R2 R1 R0

bit 23 bit 0

General-purpose registers

PC

bit 23

7 6 5 4 3 2 1 0

bit 0

PSR

SP

Special registers

IL[2:0]

7 6 5IE4C3V2Z1N0

Symbol

R0–R7

Size

24 bits

Initial value

0x000000 or indeterminate

Register name

General-Purpose Register

R/W

Symbol

PC

Size

24 bits

Initial value

(Reset vector)

Register name

Program Counter

R/W

R

Effective address 0

0123

2 Registers

The S1C17 Core contains eight general-purpose registers and three special registers.

Figure 2.1 Registers

2.1 General-Purpose Registers (R0–R7)

The eight registers R0–R7 (r0–r7) are 24-bit general-purpose registers that can be used for data manipulation, data transfer, memory addressing, or other general purposes. The contents of all of these registers are handled as 24-bit data or addresses. 8- or 16-bit data can be sign- or zero-extended to a 24-bit quantity when it is loaded into one of these registers using a load instruction or a conversion instruction. When these registers are used for address references, 24-bit memory space can be accessed directly. At initial reset, the contents of the general-purpose registers are set to 0 (may be indeterminate without initialization depending on the configuration).

2.2 Program Counter (PC)

The Program Counter (hereinafter referred to as the “PC”) is a 24-bit counter for holding the address of an instruction to be executed. More specifically, the PC value indicates the address of the next instruction to be executed. As the instructions in the S1C17 Core are fixed at 16 bits in length, the LSB (bit 0) of the PC is always 0. Although the S1C17 Core allows the PC to be referenced in a program, the user cannot alter it. Note, however, that the value actually loaded into the register when a struction) is executed is the “PC value for the At an initial reset, the reset vector (address) written at the top of vector table indicated by TTBR is loaded into the PC, and the processor starts executing a program from the address indicated by the PC.

S1C17 FAMILY S1C17 CORE MANUAL

Figure 2.2.1 Program Counter (PC)

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ld.a %rd,%pc instruction (can be executed as a delayed in-

ld instruction + 2.”

2-1

2 REGISTERS

Symbol

PSR

Size

8 bits

Initial value

0x00

Register name

Processor Status Register

R/W

IL[2:0]

7 6 5IE4C3V2Z1N0

0 0 0 0 0 0 0 0Initial value

PSR

2.3 Processor Status Register (PSR)

The Processor Status Register (hereinafter referred to as the “PSR”) is an 8-bit register for storing the internal status of the processor. The PSR stores the internal status of the processor when the status has been changed by instruction execution. It is referenced in arithmetic operations or branch instructions, and therefore constitutes an important internal status in program composition. The PSR does not allow the program to directly alter its contents except for the IE bit. As the PSR affects program execution, whenever an interrupt occurs, the PSR is saved to the stack, except for de bug interrupts, to maintain the PSR value. The IE flag (bit 4) in it is cleared to 0. The return from interrupt handling, and the PSR value is restored from the stack at the same time.

Figure 2.3.1 Processor Status Register (PSR)

IL[2:0] (bits 7–5): Interrupt Level

These bits indicate the priority levels of the processor interrupts. Maskable interrupt requests are accepted only

when their priority levels are higher than that set in the IL bit field. When an interrupt request is accepted, the IL bit field is set to the priority level of that interrupt, and all interrupt requests generated thereafter with the same or lower priority levels are masked, unless the IL bit field is set to a different level or the interrupt handler routine is terminated by the reti instruction.

reti instruction is used to

-

IE (bit 4):

Interrupt Enable

This bit controls maskable external interrupts by accepting or disabling them. When IE bit = 1, the processor

enables maskable external interrupts. When IE bit = 0, the processor disables maskable external interrupts.

When an interrupt is accepted, the PSR is saved to the stack and this bit is cleared to 0. However, the PSR is not

saved to the stack for debug interrupts, nor is this bit cleared to 0.

C (bit 3):

Carry

This bit indicates a carry or borrow. More specifically, this bit is set to 1 when, in an add or subtract instruction

in which the result of operation is handled as an unsigned 16-bit integer, the execution of the instruction result ed in exceeding the range of values representable by an unsigned 16-bit integer, or is reset to 0 when the result is within the range of said values.

The C flag is set under the following conditions:

(1) When an addition executed by an add instruction resulted in a value greater than the maximum value 0xffff

representable by an unsigned 16-bit integer

(2) When a subtraction executed by a subtract instruction resulted in a value smaller than the minimum value

0x0000 representable by an unsigned 16-bit integer

V (bit 2): O

Verflow

This bit indicates that an overflow or underflow occurred in an arithmetic operation. More specifically, this bit

is set to 1 when, in an add or subtract instruction in which the result of operation is handled as a signed 16-bit integer, the execution of the instruction resulted in an overflow or underflow, or is reset to 0 when the result of the add or subtract operation is within the range of values representable by a signed 16-bit integer. This flag is also reset to 0 by executing a logical operation instruction.

-

2-2

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S1C17 FAMILY S1C17 CORE MANUAL

2 REGISTERS

The V flag is set under the following conditions:

(1) When negative integers are added together, the operation produced a 0 (positive) in the sign bit (most sig

nificant bit of the result)

-

(2) When positive integers are added together, the operation resulted in a 1 (negative) in the sign bit (most sig

nificant bit of the result)

(3) When a negative integer is subtracted from a positive integer, the operation resulted in producing a 1 (nega

tive) in the sign bit (most significant bit of the result)

(4) When a positive integer is subtracted from a negative integer, the operation resulted in producing a 0 (positive)

in the sign bit (most significant bit of the result)

Z (bit 1):

Zero

This bit indicates that an operation resulted in 0. More specifically, this bit is set to 1 when the execution of a

logical operation, arithmetic operation, or shift instruction resulted in 0, or is otherwise reset to 0.

N (bit 0):

Negative

This bit indicates a sign. More specifically, the most significant bit (bit 15) of the result of a logical operation,

arithmetic operation, or shift instruction is copied to this N flag.

-

S1C17 FAMILY S1C17 CORE MANUAL

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2-3

2 REGISTERS

Symbol

SP

Size

24 bits

Initial value

0x000000

Register name

Stack Pointer

R/W

32-bit boundary address 0 0

01223

Fixed

(read only)

SP

7 0

0xffffff

0x000000

SP = SP - 4

7 0

0xffffff

0x00

PC[23:16]

PC[15:8]

PC[7:0]

0x000000

2.4 Stack Pointer (SP)

The Stack Pointer (hereinafter referred to as the “SP”) is a 24-bit register for holding the start address of the stack. The stack is an area locatable at any place in the system RAM, the start address of which is set in the SP during the initialization process. The 2 low-order bits of the SP are fixed to 0 and cannot be accessed for writing. Therefore, the addresses specifiable by the SP are those that lie on 32-bit boundaries.

Figure 2.4.1 Stack Pointer (SP)

2.4.1 About the Stack Area

The size of an area usable as the stack is limited according to the RAM size available for the system and the size of the area occupied by ordinary RAM data. Care must be taken to prevent the stack and data area from overlapping. Furthermore, as the SP becomes 0x000000 when it is initialized upon reset, “last stack address + 4, with 2 loworder bits = 0” must be written to the SP in the beginning part of the initialization routine. A load instruction may be used to write this address. If an interrupt occurs before the stack is set up, it is possible that the PC or PSR will be saved to an indeterminate location, and normal operation of a program cannot be guaranteed. To prevent such a problem, NMIs (nonmaskable interrupts) that cannot be controlled in software are masked out in hardware until the SP is initialized.

2.4.2 SP Operation at Subroutine Call/Return

A subroutine call instruction, call or calla, uses four bytes of the stack. The call/calla instruction saves the contents of the PC (return address) onto the stack before branching to a subroutine. The saved address is restored into the PC by the struction.

SP operation by the

(1) SP = SP - 4 (2) PC → [SP]

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EPSON

ret instruction, and the program is returned to the address next to that of the call/calla in-

call/calla instruction

Figure 2.4.2.1 SP and Stack (1)

S1C17 FAMILY S1C17 CORE MANUAL

2 REGISTERS

SP

7 0

0xffffff

0x000000

SP = SP + 4

7 0

0xffffff

0x00

PC[23:16]

0x00

PC[23:16]

PC[15:8]

PC[7:0]

PC[15:8]

PC[7:0]

0x000000

SP

7 0

0xffffff

0x000000

SP = SP - 4

7 0

0xffffff

0x00

PC[23:16]

PC[15:8]

PC[7:0]

0x000000

SP

7 0

0xffffff

0x000000

SP = SP + 4

7 0

0xffffff

PSR

PC[23:16]

PSR

PC[23:16]

PC[15:8]

PC[7:0]

PC[15:8]

PC[7:0]

0x000000

SP operation by the ret instruction

(1) [SP] → PC (2) SP = SP + 4

Figure 2.4.2.2 SP and Stack (2)

2.4.3 SP Operation when an Interrupt Occurs

If an interrupt or a software interrupt resulting from the int/intl instruction occurs, the processor enters an interrupt handling process. The processor saves the contents of the PC and PSR into the stack indicated by the SP before branching to the rel evant interrupt handler routine. This is to save the contents of the two registers before they are altered by interrupt handling. The PC and PSR data is saved into the stack as shown in the diagram below. For returning from the handler routine, the reti instruction is used to restore the contents of the PC and PSR from the stack. In the in the diagram below.

reti instruction, the PC and PSR are read out of the stack, and the SP address is altered as shown

-

SP operation when an interrupt occurred

(1) SP = SP - 4 (2) PC → [SP] (3) PSR → [SP + 3]

Figure 2.4.3.1 SP and Stack (3)

SP operation when the reti instruction is executed

(1) [SP] → PC (2) [SP+ 3] → PSR (3) SP = SP + 4

S1C17 FAMILY S1C17 CORE MANUAL

Figure 2.4.3.2 SP and Stack (4)

EPSON

2-5

2 REGISTERS

SP

7 0

0xffffff

0x000000

SP = SP - 4

7 0

0xffffff

0x00

R0[23:16]

R0[15:8]

R0[7:0]

0x000000

SP

7 0

0xffffff

0x000000

SP = SP + 4

7 0

0xffffff

0x00

R0[23:16]

0x00

R0[23:16]

R0[15:8]

R0[7:0]

R0[15:8]

R0[7:0]

0x000000

2.4.4 Saving/Restoring Register Data Using a Load Instruction

The S1C17 Core provides load instructions to save and restore register data to/from the stack instead of push/pop instructions.

Saving register data into the stack

Example: (1) SP = SP - 4 (2) R0 → [SP]

Restoring register data from the stack

Example: (1) [SP] → R0 (2) SP = SP + 4

ld.a -[%sp],%r0

Figure 2.4.4.1 SP and Stack (5)

ld.a %r0,[%sp]+

Figure 2.4.4.2 SP and Stack (6)

In addition to the instructions shown above, some other load instructions have been provided for operating the stack. Refer to Chapter 7, “Details of Instructions,” for more information on those instructions.

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S1C17 FAMILY S1C17 CORE MANUAL

2 REGISTERS

General-purpose register

R0 R1 R2 R3 R4 R5 R6 R7

Register number

0 1 2 3 4 5 6 7

Register notation

%r0 %r1 %r2 %r3 %r4 %r5 %r6 %r7

2.5 Register Notation and Register Numbers

The following describes the register notation and register numbers in the S1C17 Core instruction set.

2.5.1 General-Purpose Registers

In the instruction code, a general-purpose register is specified using a 3-bit field, with the register number entered in that field. In the mnemonic, a register is specified by prefixing the register name with “

%rs rs is a metasymbol indicating the general-purpose register that holds the source data to be operated on or

transferred. The register is actually written as

%r0, %r1, ... or %r7.

%rd rd is a metasymbol indicating the general-purpose register that is the destination in which the result of op-

eration is to be stored or data is to be loaded. The register is actually written as

%rb rb is a metasymbol indicating the general-purpose register that holds the base address of memory to be ac-

cessed. In this case, the general-purpose registers serve as an index register. The register is actually written as [%r0], [%r1], ... or [%r7], with each register name enclosed in brackets “[]” to denote register indi rect addressing.

In register indirect addressing, the post-increment/decrement and pre-decrement functions provided for

continuous memory addresses can be used.

Post-increment function

Example:

ld %rd,[%rb]+ ; (1)ld %rd,[%rb] (2)%rb = %rb + 2

The base address is incremented by an amount equal to the accessed size after the memory has been ac

cessed.

%.”

%r0, %r1, ... or %r7.

-

Post-decrement function

Example:

ld.a %rd,[%rb]- ; (1)ld.a %rd,[%rb] (2)%rb = %rb - 4

The base address is decremented by an amount equal to the accessed size after the memory has been ac

cessed.

Pre-decrement function

Example:

ld.b -[%rb],%rs ; (1)%rb = %rb - 1 (2)ld.b [%rb],%rs

The base address is decremented by an amount equal to the access size before accessing the memory.

Also any desired value can be specified as the address increment/decrement value using the

ext instruc-

tion.

rb is also used as a symbol indicating the register that contains the jump address for the call or jump in- structions. In this case, the brackets “

[]” are unnecessary, and the register is written as %r0, %r1, ... or

%r7.

The bit field that specifies a register in the instruction code contains the code corresponding to a given register number. The relationship between the general-purpose registers and the register numbers is listed in the table below.

Table 2.5.1.1 General-Purpose Registers

-

2.5.2 Special Registers

The special registers that can be directly specified in the S1C17 Core instructions are the SP (Stack Pointer) and PC (Program Counter) only. The register is actually written as [%sp+imm7], or %pc.

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%sp, [%sp], -[%sp], [%sp]+, [%sp]-,

2-7

2 REGISTERS

THIS PAGE IS BLANK.

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S1C17 FAMILY S1C17 CORE MANUAL

3 DATA FORMATS

%rs X

23 16X15 8

Byte

7 0

23 16 15 8

Byte

7 0

0

%rd 00000000 00000000

%rs X

23 16X15 8 7 0

23 16 15 8

Byte

7 0

%rd SSSSSSSSSS

Byte

0

00000000

3 Data Formats

3.1 Data Formats Handled in Operations Between Registers

The S1C17 Core can handle 8-, 16-, and 24-bit data in register operations. In this manual, data sizes are expressed as follows: 8-bit data 16-bit data Word 24-bit data Address data

Data sizes can be selected only in data transfer (load instruction) between one general-purpose register and another. In an 8-bit data transfer with a general-purpose register as the destination, the data is sign- or zero-extended to 16 bits before being loaded into the register. Whether the data will be sign- or zero-extended is determined by the load instruction used. In a 16-bit or 8-bit data transfer using a general-purpose register as the source, the data to be transferred is stored in the low-order 16 bits or the low-order 8 bits of the source register. The data transfer sizes and types are described below.

3.1.1 Unsigned 8-Bit Transfer (Register → Register)

Example: ld.ub %rd,%rs

Byte, B, or b

, W, or w

, A, a

Figure 3.1.1.1 Unsigned 8-Bit Transfer (Register → Register)

Bits 23–8 in the destination register are set to 0x0000.

3.1.2 Signed 8-Bit Transfer (Register → Register)

Example: ld.b %rd,%rs

Figure 3.1.2.1 Signed 8-Bit Transfer (Register → Register)

Bits 15–8 in the destination register are sign-extended and bits 23–16 are set to 0x00.

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3-1

3 DATA FORMATS

X%rs

23 16 15

16-bit data

0

23 16 15

16-bit data

0

%rd 00000000

%rs

23

24-bit data

0

23

24-bit data

0

%rd

Byte 38-bit data

31 24

Byte 2

23

0x00

24 23

16

Byte 1

15 8

Byte 0

7 0

Word 116-bit data

31 16

Word 0

15 0

Address data32-bit data

31 0

3.1.3 16-Bit Transfer (Register → Register)

Example: ld %rd,%rs

Figure 3.1.3.1 16-Bit Transfer (Register → Register)

Bits 23–16 in the destination register are set to 0x00.

3.1.4 24-Bit Transfer (Register → Register)

Example: ld.a %rd,%rs

Figure 3.1.4.1 24-Bit Transfer (Register → Register)

3.2 Data Formats Handled in Operations Between Memory and a Register

The S1C17 Core can handle 8-, 16-, and 32-bit data in memory operations. In this manual, data sizes are expressed as follows: 8-bit data 16-bit data Word 32-bit data Address data

Data sizes can be selected only in data transfer (load instruction) between memory and a general-purpose register. In an 8-bit data transfer with a general-purpose register as the destination, the data is sign- or zero-extended to 16 bits before being loaded into the register. Whether the data will be sign- or zero-extended is determined by the load instruction used. In a 16-bit or 8-bit data transfer using a general-purpose register as the source, the data to be transferred is stored in the low-order 16 bits or the low-order 8 bits of the source register. Memory is accessed in little endian format one byte, 16 bits, or 32 bits at a time. If memory is to be accessed in 16-bit or 32-bit units, the specified base address must be on a 16-bit boundary (least significant address bit = 0) or 32-bit boundary (2 low-order address bits = 00), respectively. Unless this condition is satisfied, an address-misaligned interrupt is generated.

Byte, B, or b

, W, or w

, A, a

Figure 3.2.1 Data Format (Little Endian)

∗ Handling the eight high-order bits during 32-bit accesses

During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order

bits are ignored. However, the eight high-order bits are effective as the PSR value only in the stack operation when an interrupt occurs.

The data transfer sizes and types are described below.

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S1C17 FAMILY S1C17 CORE MANUAL

3.2.1 Unsigned 8-Bit Transfer (Memory → Register)

[%rb] Byte

7 0

23 16 15 8

Byte

7 0

0

%rd 00000000 00000000

[%rb]

7 0

15 8

Byte

7 0

%rd SSSSSSSSSS

Byte

23 16

0

00000000

%rs X

23 16X15 8

Byte

7 0

Byte

7 0

[%rb]

[%rb] 0b∗∗∗∗∗0 Byte 0

7

78

0

23 16 15

Byte 0Byte 1

0

0b∗∗∗∗∗1 Byte 1

%rd 00000000

Example: ld.ub %rd,[%rb]

Figure 3.2.1.1 Unsigned 8-Bit Transfer (Memory → Register)

Bits 23–8 in the destination register are set to 0x0000.

3.2.2 Signed 8-Bit Transfer (Memory → Register)

Example: ld.b %rd,[%rb]

Figure 3.2.2.1 Signed 8-Bit Transfer (Memory → Register)

Bits 15–8 in the destination register are sign-extended and bits 23–16 are set to 0x00.

3 DATA FORMATS

3.2.3 8-Bit Transfer (Register → Memory)

Example: ld.b [%rb],%rs

Figure 3.2.3.1 8-Bit Transfer (Register → Memory)

3.2.4 16-Bit Transfer (Memory → Register)

Example: ld %rd,[%rb]

Figure 3.2.4.1 16-Bit Transfer (Memory → Register)

Bits 23–16 in the destination register are set to 0x00.

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3-3

3 DATA FORMATS

X%rs

23 16

[%rb] 0b∗∗∗∗∗∗∗0 Byte 0

7 0

7815

Byte 0Byte 1

0

0b∗∗∗∗∗∗∗1 Byte 1

[%rb] 0b∗∗∗∗∗∗00 Byte 0

7816 15

Byte 0Byte 1

23

Byte 2

0

0b∗∗∗∗∗∗01 Byte 1

0b∗∗∗∗∗∗10 Byte 2

%rd

7 0

0b∗∗∗∗∗∗11 Byte 3

Ignored after read

[%rb] 0b∗∗∗∗∗∗00 Byte 0

7

78

0

16 15

Byte 0Byte 1

23

Byte 2

0

0b∗∗∗∗∗∗01 Byte 1

0b∗∗∗∗∗∗10 Byte 2

0b∗∗∗∗∗∗11 0x00

%rs

3.2.5 16-Bit Transfer (Register → Memory)

Example: ld [%rb],%rs

Figure 3.2.5.1 16-Bit Transfer (Register → Memory)

3.2.6 32-Bit Transfer (Memory → Register)

Example: ld.a %rd,[%rb]

Figure 3.2.6.1 32-Bit Transfer (Memory → Register)

3.2.7 32-Bit Transfer (Register → Memory)

Example: ld.a [%rb],%rs

Figure 3.2.7.1 32-Bit Transfer (Register → Memory)

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S1C17 FAMILY S1C17 CORE MANUAL

4 ADDRESS MAP

0xff ffff 0xff fe00

0xff fdff

0x00 0000

Reserved core I/O area

4 Address Map

4.1 Address Space

The S1C17 Core supports a 24-bit address allowing linear use of address space up to 16M bytes. Addresses 0xfffe00 to 0xffffff are reserved as an I/O area for the core. In addition to this area, a 64-byte area located in the

user RAM is required for debugging. Figure 4.1.1 shows the address space of the S1C17 Core.

Figure 4.1.1 Address Space of the S1C17 Core

The boot address and debug RAM address depend on the specifications of each the S1C17 Series models. Refer to the Technical Manual of each model.

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4-1

4 ADDRESS MAP

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0 0x0–0xFFFD00 (256 byte units)

– TTBR23 | TTBR0

D31–24

D23

|

D0

Unused (fixed at 0) Trap table base address TTBR[7:0] is fixed at 0x0.

0x0

∗

R R

Initial value is set by the TTBR pins of the C17 macro.

FFFF80

(L)

Trap table base register

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x10

IDIR7 | IDIR0

D7

|

D0

Processor ID 0x10: S1C17 Core

0x10

R

FFFF84

(B)

Processor ID register

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0 0x0–0xFFFDC0

(64 byte units)

– DBRAM23 | DBRAM0

D31–24

D23

|

D0

Unused (fixed at 0) Debug RAM base address DBRAM[5:0] is fixed at 0x0.

0x0

∗

R R

Initial value is set in the C17 RTL-define DBRAM_BASE.

FFFF90

(L)

Debug RAM base register

4.2 Processor Information in the Core I/O Area

The reserved core I/O area contains the processor information described below.

4.2.1 Trap Table Base Register (TTBR, 0xffff80)

This is a read-only register that contains the trap table base address. The trap table (also called a vector table) contains the vectors to the interrupt handler routines (handler routine start address) that will be read by the S1C17 Core to execute the handler when an interrupt occurs. The boot address from which the program starts running after a reset must be written to the top of the trap table.

4.2.2 Processor ID Register (IDIR, 0xffff84)

This is a read-only register that contains the ID code to represent a processor model. The S1C17 Core’s ID code is 0x10.

4.2.3 Debug RAM Base Register (DBRAM, 0xffff90)

This is a read-only register that contains the start address of a work area (64 bytes) for debugging.

∗ In addition to the above registers, the reserved core I/O area contains some registers for debugging. For the debug

registers, refer to Section 6.5, “Debug Circuit.”

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5 INSTRUCTION SET

Classification

Data transfer

Function

General-purpose register (byte)

→ general-purpose register (sign-extended)

Memory (byte)

→ general-purpose register (sign-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (byte)

→ general-purpose register (sign-extended)

Memory (byte)

→ general-purpose register (sign-extended) General-purpose register (byte)

→ memory Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (byte)

→ stack General-purpose register (byte)

→ memory General-purpose register (byte)

→ general-purpose register (zero-extended) Memory (byte)

→ general-purpose register (zero-extended) Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stack (byte)

→ general-purpose register (zero-extended)

Memory (byte)

→ general-purpose register (zero-extended) General-purpose register (16 bits) → general-purpose register Immediate → general-purpose register (sign-extended) Memor

y (

16 bits

) → general-purpose register Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stac

k (

16 bits

) → general-purpose register

Memor

y (

16 bits

) → general-purpose register General-purpose register

(

16 bits

) → memory Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register

(

16 bits

) → stack General-purpose register (16 bits) →

memory General-purpose register (24 bits) → general-purpose register Immediate → general-purpose register (zero-extended) Memor

y (

32 bits

) → general-purpose register *

Memory address post-increment, post-decrement, and pre-decrement functions can be used.

Stac

k (

32 bits

) → general-purpose register *

Memor

y (

32 bits

) → general-purpose register *

General-purpose register (32

bits,

zero-extended) → memory *

Memory address post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (32

bits,

zero-extended) → stack *

General-purpose register (32 bits,

zero-extended

) →

memory *

SP → general-purpose register PC → general-purpose register Stac

k (

32 bits

) → general-purpose register *

Stack pointer post-increment, post-decrement, and pre-decrement functions can be used.

ld.b

ld.ub

ld

ld.a

%rd,%rs

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb

],%rs

[%sp+imm7

],%rs

[imm7],%rs

%rd,%rs

%rd,

[%rb] %rd,[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,[imm7]

%rd,%rs

%rd,sign7

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb

],%rs

[%sp+imm7

],%rs

[imm7],%rs

%rd,%rs

%rd,imm7

%rd,

[%rb] %rd,[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb

],%rs [%sp+imm7],%rs [imm7],%rs

%rd,%sp %rd,%pc %rd,[%sp] %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp]

Mnemonic

5 Instruction Set

The S1C17 Core instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, allows most important instructions to be executed in one cycle. For details, refer to the description of each instruction in the latter sections of this manual.

5.1 List of Instructions

Table 5.1.1 S1C17 Instructions List

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5-1

5 INSTRUCTION SET

Classification

Data transfer

Integer arithmetic operation

Logical operation

Function

General-purpose register (32

bits,

zero-extended) → stack *

Stack pointer post-increment, post-decrement, and pre-decrement functions can be used.

General-purpose register (24 bits)

→ SP Immediate → SP 16-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit addition of general-purpose register and immediate 24-bit addition between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit addition of SP and general-purpose register 24-bit addition of general-purpose register and immediate 24-bit addition of SP and immediate 16-bit addition with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit addition of general-purpose register and immediate with carr

y 16-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit subtraction of general-purpose register and immediate 24-bit subtraction between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit subtraction of SP and general-purpose register 24-bit subtraction of general-purpose register and immediate 24-bit subtraction of SP and immediate 16-bit subtraction with carry between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit subtraction of general-purpose register and immediate with carr

y 16-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit comparison of general-purpose register and immediate 24-bit comparison between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

24-bit comparison of general-purpose register and immediate 16-bit compar

ison

with carry

between general-purpose registers

Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

16-bit comparison of general-purpose register and immediate

with carry Logical AND between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical AND of general-purpose register and immediate Logical OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical OR of general-purpose register and immediate Exclusive OR between general-purpose registers Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Exclusive OR of general-purpose register and immediate Logical in

version between general-purpose registers (1's complement)

Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).

Logical in

version of general-purpose register and immediate (1's complement)

ld.a

add add/c add/nc add add.a add.a/c add.a/nc add.a

adc adc/c adc/nc adc sub sub/c sub/nc sub sub.a sub.a/c sub.a/nc sub.a

sbc sbc/c sbc/nc sbc cmp cmp/c cmp/nc cmp cmp.a cmp.a/c cmp.a/nc cmp.a cmc cmc/c cmc/nc cmc and and/c and/nc and or or/c or/nc or xor xor/c xor/nc xor not not/c not/nc not

[%sp],%rs [%sp]+,%rs [%sp]-,%rs

-[%sp],%rs %sp,%rs %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%sp,%rs

%rd,imm7 %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%sp,%rs

%rd,imm7 %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

Mnemonic

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S1C17 FAMILY S1C17 CORE MANUAL

5 INSTRUCTION SET

Classification

Shift and swap

Immediate extension Conversion

Branch

System control

Coprocessor control

Function

Logical shift to the right with the number of bits specified by the register Logical shift to the right with the number of bits specified by immediate Arithmetic shift to the right with the number of bits specified by the register Arithmetic shift to the right with the number of bits specified by immediate Logical shift to the left with the number of bits specified by the register Logical shift to the left with the number of bits specified by immediate Byte

wise swap on byte boundary in 16 bits

Extend operand in the f

ollowing instruction Convert signed 8-bit data into 24 bits Convert signed 16-bit data into 24 bits Convert 32-bit data into 24 bits Converts 24-bit data into 32 bits Converts 16-bit data into 32 bits PC relative jump Delayed branching possible Absolute jump Delayed branching possible PC relative conditional jump Branch condition: !Z & !(N ^

V) Delayed branching possible PC relative conditional jump Branch condition: !(N ^

V) Delayed branching possible PC relative conditional jump Branch condition: N ^

V Delayed branching possible PC relative conditional jump Branch condition: Z | N ^

V Delayed branching possible PC relative conditional jump Branch condition: !Z & !C Delayed branching possible PC relative conditional jump Branch condition: !C Delayed branching possible PC relative conditional jump Branch condition: C Delayed branching possible PC relative conditional jump Branch condition: Z |

C Delayed branching possible PC relative conditional jump Branch condition: Z Delayed branching possible PC relative conditional jump Branch condition: !Z Delayed branching possible PC relative subroutine call Delayed call possible Absolute subroutine call Delayed call possible Return from subroutine Delayed return possible Software interr

upt

Software interrupt with interrupt le

vel setting Return from interrupt handling Delayed call possible Debug interrupt Return from debug processing No operation HALT mode SLEEP mode Enable interrupts Disable interrupts Tr

ansfer data to coprocessor

Transfer data to coprocessor and get results and flag statuses

Tr

ansfer data to coprocessor and get flag statuses

sr

sa

sl

swap ext cv.ab cv.as cv.al cv.la cv.ls jpr jpr.d jpa ipa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d int intl reti reti.d brk retd nop halt slp ei di ld.cw

ld.ca

ld.cf

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

imm13

%rd,%rs

sign10

%rb

imm7

%rb

sign7

sign10

%rb

imm7

%rb

imm5

imm5,imm3

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

Mnemonic

∗ The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the

32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memo

ry, the eight high-order bits of the read data are ignored.

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5 INSTRUCTION SET

Symbol

%rs %rd

[%rb] [%rb]+ [%rb]-

-[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]-

-[%sp]

imm3,imm5,imm7,imm13 sign7,sign10

Description

General-purpose register, source General-purpose register, destination Memory addressed by general-purpose register Memory addressed by general-purpose register with address post-incremented Memory addressed by general-purpose register with address post-decremented Memory addressed by general-purpose register with address pre-decremented Stack pointer Stack Stack with address post-incremented Stack with address post-decremented Stack with address pre-decremented Unsigned immediate (numerals indicating bit length) Signed immediate (numerals indicating bit length)

The symbols in the above table each have the meanings specified below.

Table 5.1.2 Symbol Meanings

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5 INSTRUCTION SET

imm13

(3:0)

(1)r0

23 20 19

imm13 (2)

7

imm7

6 0

5.2 Addressing Modes (without ext extension)

The instruction set of the S1C17 Core has seven discrete addressing modes, as described below. The processor determines the addressing mode according to the operand in each instruction before it accesses data. (1) Immediate addressing (2) Register direct addressing (3) Register indirect addressing (4) Register indirect addressing with post-increment/post-decrement/pre-decrement (5) Register indirect addressing with displacement (6) Signed PC relative addressing (7) PC absolute addressing

5.2.1 Immediate Addressing

The immediate included in the instruction code that is indicated as immX (unsigned immediate) or signX (signed immediate) is used as the source data. The immediate size specifiable in each instruction is indicated by a numeral in the symbol (e.g., significant bit is the sign bit, which is extended to 16 or 24 bits when the instruction is executed. Example: ld %r0,0x70 ; Load 16-bit data

Before execution r0 = 0x After execution r0 = 0x00fff0

imm7 = unsigned 7 bits; sign7 = signed 7 bits). For signed immediates such as sign7, the most

XXXXXX

The immediate

sign7 can represent values in the range of +63 to -64 (0b0111111 to 0b1000000).

Except in the case of shift-related instructions, immediate data can be extended to a maximum of 24 bits by a com bined use of the operand value and the

ext instruction. Example: ext imm13 (1) ext imm13 (2) ld.a %r0,imm7 ; Load 24-bit data

r0 after execution

5.2.2 Register Direct Addressing

The content of a specified register is used directly as the source data. Furthermore, if this addressing mode is specified as the destination for an instruction that loads the result in a register, the result is loaded in this specified regis ter. The instructions that have the following symbols as the operand are executed in this addressing mode.

%rs rs is a metasymbol indicating the general-purpose register that holds the source data to be operated on or

transferred. The register is actually written as

%rd rd is a metasymbol indicating the general-purpose register that is the destination for the result of operation.

The register is actually written as

%r0, %r1, ... or %r7. Depending on the instruction, it will also be used

as the source data.

Special register names are written as follows: Stack pointer Program counter

The register names are always prefixed by “

%sp %pc

%” to discriminate them from symbol names, label names, and the like.

%r0, %r1, ... or %r7.

-

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5 INSTRUCTION SET

5.2.3 Register Indirect Addressing

In this mode, memory is accessed indirectly by specifying a general-purpose register or the stack pointer that holds the address needed. This addressing mode is used only for load instructions that have erand. Actually, this general-purpose register is written as name enclosed in brackets “ The processor refers to the content of a specified register as the base address, and transfers data in the format that is determined by the type of load instruction. Examples: Memory → Register ld.b %r0,[%r1] ; Load 8-bit data

ld %r0,[%r1] ; Load 16-bit data ld.a %r0,[%r1] ; Load 24-bit data

[].”

[%r0], [%r1], ... [%r7], or [%sp], with the register

[%rb] or [%sp] as the op-

Register ld.b [%r1],%r0 ; Store 8-bit data

ld [%r1],%r0 ; Store 16-bit data ld.a [%r1],%r0 ; Store 24-bit data

In this example, the address indicated by r1 is the memory address from or to which data is to be trans

ferred.

In 16-bit and 24-bit transfers, the base address that is set in a register must be on a 16-bit boundary (least significant address bit = 0) or 32-bit boundary (2 low-order address bits = 0), respectively. Otherwise, an address-misaligned interrupt will be generated.

→ Memory

5.2.4 Register Indirect Addressing with Post-increment/decrement or Pre-decrement

As in register indirect addressing, the memory location to be accessed is specified indirectly by a general-purpose register or the stack pointer. In this addressing mode, the base address held in a specified register is incremented/ decremented by an amount equal to the transferred data size before or after a data transfer. In this way, data can be read from or written to continuous addresses in memory only by setting the start address once at the beginning.

∗ Increment/decrement size (without ext) Byte transfer ( 16-bit transfer ( 24-bit transfer (

Register indirect addressing with post-increment

When a data transfer finishes, the base address is incremented. This addressing mode is specified by enclosing the register name in brackets “[],” which is then suffixed by “

The register name is actually written as

ld.b, ld.ub): rb → rb + 1, rb → rb - 1

ld): rb → rb + 2, rb → rb - 2 ld.a): rb → rb + 4, rb → rb - 4

+.”

[%r0]+, [%r1]+, ... [%r7]+, or [%sp]+.

-

Register indirect addressing with post-decrement

When a data transfer finishes, the base address is decremented. This addressing mode is specified by enclosing the register name in brackets “[],” which is then suffixed by “

The register name is actually written as

[%r0]-, [%r1]-, ... [%r7]-, or [%sp]-.

Register indirect addressing with pre-decrement

The base address is decremented before a data transfer starts. This addressing mode is specified by enclosing the register name in brackets “

The register name is actually written as

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-[%r0], -[%r1], ... -[%r7], or -[%sp].

[],” which is prefixed by “-.”

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5 INSTRUCTION SET

5.2.5 Register Indirect Addressing with Displacement

In this mode, memory is accessed beginning with the address that is derived by adding a specified immediate (displacement) to the register content. Unless ext instructions are used, this addressing mode can only be used for load instructions that have Example: ld.b %r0,[%sp+0x10] The byte data at the address derived by adding 0x10 to the content of the current SP is loaded into the R0

register.

If ext instructions described in Section 5.3 are used, ordinary register indirect addressing ([%rb]) becomes a special addressing mode in which the immediate specified by the Example: ext imm13 ld.b %rd,[%rb] The memory address to be accessed is “%rb+imm13.”

[%sp+imm7] as the operand.

ext instruction constitutes the displacement.

5.2.6 Signed PC Relative Addressing

This addressing mode is used for the jpr, jr∗, and call instructions that have a signed 7- or 10-bit immediate (sign7/sign10) or %rb in their operand. When these instructions are executed, the program branches to the address derived by twice adding the Example: PC + 0 : : condition holds true. : : (PC + 0) + 0x04 PC + 8

sign7/sign10 value (16-bit boundary) or the rb register value to the current PC.

jrne 0x04 The program branches to the PC + 8 address when the jrne branch

∗ 2 → PC + 8

5.2.7 PC Absolute Addressing

This addressing mode is used for the jpa, and calla instructions that have an unsigned 7-bit immediate (imm7) or %rb in their operand. When these instructions are executed, the program directly branches to the address specified with the int and intl instructions that execute interrupt handler routines. Example: int 0x03 Executes the interrupt handler of vector No. 3 (TTBR + 0xc).

imm7 or rb register value by loading the value to the PC. Also this addressing mode is used for the

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5 INSTRUCTION SET

15

imm13

(8:0)

7

imm7

6 0

0 000

23 20 19

imm13

7

imm7

6 0

imm13(3:0) (1)

23 20 19

imm13 (2)

7

imm7

6 0

5.3 Addressing Modes with ext

The immediate specifiable in 16-bit, fixed-length instruction code is specified in a bit field of a 7- or 10-bit length, depending on the instruction used. The The ext instructions are used in combination with data transfer, arithmetic/logic, or branch instructions, and is placed directly before the instruction whose immediate needs to be extended. The instruction is expressed in the form ext imm13, in which the immediate size extendable by one ext instruction is 13 bits and up to two ext instructions can be written in succession to extend the immediate further. The ext instructions are effective only for the instructions for which the immediate extension written directly after ext is possible, and have no effect for all other instructions. When three or more ext instructions have been described sequentially, the last two are effective and others are ignored. When an instruction, which does not support the extension in the ext instruction, follows an ext, the ext instruc tion will be executed as a

nop instruction.

5.3.1 Extension of Immediate Addressing

Extension of imm7

The imm7 immediate is extended to a 16-, 20-, or 24-bit immediate.

Extending to a 16-bit immediate

To extend the immediate to 16-bit quantity, enter one

Example: ext imm13

add

%rd,imm7 ; = add %rd,imm16

ext instructions are used to extend the size of this immediate.

ext instruction directly before the target instruction.

-

Extended immediate

Extending to a 20-bit immediate

To extend the immediate to 20-bit quantity, enter one

ext instruction directly before the target instruction.

Example: ext imm13

add.a

%rd,imm7 ; = add.a %rd,imm20

Extended immediate

Bits 23–20 are filled with 0 (zero-extension).

Extending to a 24-bit immediate

To extend the immediate to 24-bit quantity, enter two

ext instructions directly before the target instruction. Example: ext imm13 (1) ext imm13 (2) ld %rd,[imm7] ; = ld %rd,[imm24]

Extended immediate

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5 INSTRUCTION SET

S15imm13

(8:0)

7

sign7

6 0

0 0 0 0 0 0 0

+

0 0 0 0

23 13 12

imm13

0

Immediate

23

Data

0

rs

23

Data + imm13

0

rd

+

13 1215

1516

imm13 (2)(1)

0

Immediate

23

Data

0

rs

Data + imm16

0

rd

imm13

(2:0)

X X X X X X X X

0 0 0 0 0 0 0 0

23

Extension of sign7

The sign7 immediate is extended to a 16-bit immediate.

Extending to a 16-bit immediate

To extend the immediate to 16-bit quantity, enter one

ext instruction directly before the target instruction.

Example: ext imm13

ld

%rd,sign7

Extended immediate

Bit 8 of the imm13 in the ext instruction is the sign, with the immediate extended to become signed

16-bit data. The most significant bit in

sign7 is handled as the MSB data of 7-bit data, and not as the

sign.

5.3.2 Extension of Register Direct Addressing

Extending register-to-register operation instructions

Register-to-register operation instructions are extended by one or two ext instructions. Unlike data transfer

instructions, these instructions add or subtract the content of the rs register and the immediate specified by an ext instruction according to the arithmetic operation to be performed. They then store the result in the rd reg-

ister. The content of the rd register does not affect the arithmetic operation performed. An example of how to extend for an add operation is shown below.

Extending to rs

+ imm13 (for 16-bit and 24-bit operation instructions)

To extend to rs + imm13, enter one ext instruction directly before the target instruction.

Example: ext imm13

add.a

If not extended, rd When extended by one

%rd,%rs

= rd + rs

ext instruction, rd = rs + imm13

Extending to rs + imm16 (for 16-bit operation instructions)

To extend to rs + imm16, enter two ext instructions directly before the target instruction.

Example: ext imm13 (1) ext imm13 (2) add %rd,%rs

If not extended, rd When extended by two

= rd + rs

ext instructions, rd = rs + imm16

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5 INSTRUCTION SET

+

13 1223

imm13 (2)imm13

(10:0)

(1)

0

Immediate

23

Data

0

rs

23

Data + imm24

0

rd

0 0 0 0 0 0 0

+

0 0 0 0

23 13 12

imm13

0

Immediate

23

Memory address pointer

0

rb

13 1223

imm13 (2)imm13

(10:0)

(1)

0

Immediate

23

Memory address pointer

0

rb

+

Extending to rs + imm24 (24-bit operation instructions)

To extend to rs + imm24, enter two ext instructions directly before the target instruction.

Example: ext imm13 (1) ext imm13 (2) add.a %rd,%rs

If not extended, rd When extended by two

= rd + rs

ext instructions, rd = rs + imm24

5.3.3 Extension of Register Indirect Addressing

Adding displacement to [%rb]

Memory is accessed at the address derived by adding the immediate specified by an ext instruction to the ad-

dress that is indirectly referenced by [%rb].

Adding a 13-bit immediate

Memory is accessed at the address derived by adding the 13-bit immediate specified by

specified by the

rb register. During address calculation, imm13 is zero-extended to 24-bit quantity.

Example: ext imm13

ld.b

%rd,[%rb] ; = ld.b %rd,[%rb+imm13]

imm13 to the address

Adding a 24-bit immediate

Memory is accessed at the address derived by adding the 24-bit immediate specified by

specified by the

rb register. Example: ext imm13 (1) ext imm13 (2) ld.b %rd,[%rb] ; = ld.b %rd,[%rb+imm24]

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S1C17 FAMILY S1C17 CORE MANUAL

imm24 to the address

5 INSTRUCTION SET

+

Immediate

23

Stack pointer

0

SP

0 000

23 20 19

imm13

7

imm7

6 0

imm13

(3:0)

(1)

23 20 19

imm13 (2)

7

imm7

6 0

Immediate

+

23

Stack pointer

0

SP

S S S S

+

0

23 21 20 8 7

imm13 sign7

0

Immediate

23

Current address

0

PC

23

New address

0

1

PC

5.3.4 Extension of Register Indirect Addressing with Displacement

Extending [%sp+imm7] displacement

The immediate (imm7) in displacement-added register indirect addressing instructions is extended. The extended data and the SP are added to comprise the source or destination address of transfer.

Extending to a 20-bit immediate

To extend the immediate to 20-bit quantity, enter one

Example: ext imm13

ld

%rd,[%sp+imm7] ; = ld %rd,[%sp+imm20]

Extending to a 24-bit immediate

To extend the immediate to 24-bit quantity, enter two

Example: ext imm13 (1) ext imm13 (2)

ld

%rd,[%sp+imm7] ; = ld %rd,[%sp+imm24]

ext instruction directly before the target instruction.

ext instructions directly before the target instruction.

5.3.5 Extension of Signed PC Relative Addressing

Extending the displacement of PC relative branch instructions

The sign7 immediate in PC relative branch instructions is extended to a signed 21-bit or a signed 24-bit im-

mediate. The value for the jump address, and the derived value is then added to PC to determine the jump address. The instructions extend this relative jump address value.

Extending to a 21-bit immediate

To extend the

struction. Example: ext imm13

jrgt

The most significant bit “S” in the immediate that has been extended by the ext instruction is the sign, with

which bits 23–21 are extended to become signed 21-bit data. The most significant bit in MSB data of 7-bit data, and not as the sign.

S1C17 FAMILY S1C17 CORE MANUAL

sign7 immediate in PC relative branch instructions is multiplied by 2 for conversion to a relative

sign7 immediate to a 21-bit immediate, enter one ext instruction directly before the target in-

sign7 ; = jrgt sign21

sign7 is handled as the

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ext

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5 INSTRUCTION SET

+

0

23 21 20 8 7

imm13 (2)S (1) sign7

0

Immediate

23

Current address

0

PC

23

New address

0

1

PC

imm13

(2:0)

+

0

23 11 10

imm13S sign10

0

Immediate

23

Current address

0

PC

23

New address

0

1

PC

0 000

23 20 19

imm13

7

imm7

6 0

New address

PC

Immediate

23 0

imm13(3:0) (1)

23 20 19

imm13 (2)

7

imm7

6 0

New address

PC

Immediate

23 0

Extending to a 24-bit immediate

To extend the

sign7 immediate to a 24-bit immediate, enter two ext instructions directly before the target in- struction. Example: ext imm13 (1) ext imm13 (2) jrgt sign7 ; = jrgt sign24

The most significant bit “S” in the immediate that has been extended by ext instructions is the sign. Bits 12–3

in the first

Also the

ext instruction are unused.

sign10 operand in the jpr and call instructions can be extended to 24-bit quantity using one ext instruction. Example: ext imm13

call

sign10 ; = call sign24

5.3.6 Extension of PC Absolute Addressing

Extending the branch destination address

The imm7 immediate is extended to a 20- or 24-bit immediate.

Extending to a 20-bit immediate

To extend the immediate to 20-bit quantity, enter one

Example: ext imm13

calla

imm7 ; = calla imm20

Extending to a 24-bit immediate

To extend the immediate to 24-bit quantity, enter two

Example: ext imm13 (1) ext imm13 (2) jpa imm7 ; = jpa imm24

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EPSON

ext instruction directly before the target instruction.

ext instructions directly before the target instruction.

S1C17 FAMILY S1C17 CORE MANUAL

5 INSTRUCTION SET

Extended with the sign in bit 7 of the byte data

23 16 15 8

Byte data

7 0

00000000 S SSSSSSSS

rd

23 16 15 8

Byte data

7 0

00000000 00000000

rd

23 16 15

16-bit data

0

00000000

rd

23

24-bit data

0

rd

5.4 Data Transfer Instructions

The transfer instructions in the S1C17 Core support data transfer between one register and another, as well as between a register and memory. A transfer data size and data extension format can be specified in the instruction code. In mnemonics, this specification is classified as follows:

ld.b Signed byte data transfer ld.ub Unsigned byte data transfer ld 16-bit data transfer ld.a 24/32-bit data transfer

In signed byte transfers to registers, the source data is sign-extended to 16 bits. In unsigned byte transfers, the source data is zero-extended to 16 bits. In transfers in which data is transferred from registers, data of a specified size on the lower side of the register is the data to be transferred.

If the destination of transfer is a general-purpose register, the register content after a transfer is as follows:

Signed byte data transfer

Unsigned byte data transfer

16-bit data transfer

24/32-bit data transfer

Refer to Chapter 3, “Data Formats,” for the data layout in the memory.

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5 INSTRUCTION SET

5.5 Logical Operation Instructions

Four discrete logical operation instructions are available for use with the S1C17 Core.

and Logical AND or Logical OR xor Exclusive-OR not Logical NOT

All logical operations are performed in a specified general-purpose register (R0–R7). The source is one of two, ei ther 16-bit data in a specified general-purpose register or immediate data (7, 13, or 16 bits). When a logical operation is performed, the V flag (bit 2) in the PSR is cleared.

Conditional execution

The logical operation instructions for between registers (op %rd,%rs) allow use of the switches to specify

whether the instruction will be executed or not depending on the C flag status.

Unconditional execution instructions

op %rd,%rs (op = and, or, xor, not)

The instruction without a switch will be always executed regardless how the C flag is set. Example:

Instructions executable under C condition

op/c %rd,%rs (op = and, or, xor, not)

The instruction with the Example:

and %rd,%rs

/c switch will be executed only when the C flag has been set to 1.

or/c %rd,%rs

-

Instructions executable under NC condition

op/nc %rd,%rs (op = and, or, xor, not)

The instruction with the Example:

xor/nc %rd,%rs

/nc switch will be executed only when the C flag has been cleared to 0.

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5 INSTRUCTION SET

5.6 Arithmetic Operation Instructions

The instruction set of the S1C17 Core supports add/subtract, and compare instructions for arithmetic operations.

add 16-bit addition add.a 24-bit addition adc 16-bit addition with carry sub 16-bit subtraction sub.a 24-bit subtraction sbc 16-bit subtraction with borrow cmp 16-bit comparison cmp.a 24-bit comparison cmc 16-bit comparison with borrow

The above arithmetic operations are performed between one general-purpose register and another (R0–R7), or be tween a general-purpose register and an immediate. Furthermore, the operations between the SP and a general-purpose register/immediate. Immediates in sizes smaller than the opera tion unit (16 bits or 24 bits), except for the The cmp instruction compares two operands, and may alter a flag, depending on the comparison result. Basically, it is used to set conditions for conditional jump instructions. If an immediate smaller than operation unit in size is specified as the source, it is sign-extended when comparison is performed.

cmp instruction, are zero-extended when operation is performed.

Conditional execution

The arithmetic operation instructions for between registers (op %rd,%rs) allow use of the switches to specify

whether the instruction will be executed or not depending on the C flag status.

add.a and sub.a instructions can perform

-

Unconditional execution instructions

op %rd,%rs (op = add, add.a, adc, sub, sub.a, sbc, cmp, cmp.a, cmc) The instruction without a switch will be always executed regardless how the C flag is set. Example:

Instructions executable under C condition

op/c %rd,%rs (op = add, add.a, adc, sub, sub.a, sbc, cmp, cmp.a, cmc)

The instruction with the Example:

Instructions executable under NC condition

op/nc %rd,%rs (op = add, add.a, adc, sub, sub.a, sbc, cmp, cmp.a, cmc)

The instruction with the Example:

add %rd,%rs

/c switch will be executed only when the C flag has been set to 1.

sub/c %rd,%rs

/nc switch will be executed only when the C flag has been cleared to 0.

cmp/nc %rd,%rs

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5-15

5 INSTRUCTION SET

15 0

C

rd

sr Logical shift right

0

15

C

rd

15 0

C

rd

sa Arithmetic shift right

MSB Sign bit

0

sl Logical shift left

0 0000000

23 16

0 0000000

23 16

0 0000000

23 16

8 715

Byte 0Byte 1

0

rs

8 715

Byte 1Byte 0

0

rd

X XXXXXXX

23 16

0 0000000

23 16

5.7 Shift and Swap Instructions

The S1C17 Core supports instructions to shift or swap the register data.

sr Logical shift right sl Logical shift left (= Arithmetic shift left) sa Arithmetic shift right swap Swap upper and lower bytes

The shift operation is effective for bits 15 to 0 in the specified register and bits 23 to 16 are set to 0. The number of bits to be shifted can be specified to 0–3 bits, 4 bits, or 8 bits using the operand ister.

%rs/imm7 = 0–3: Shift 0 to 3 bits %rs/imm7 = 4–7: Shift 4 bits (fixed) %rs/imm7 = 8 or more: Shift 8 bits (fixed)

Example: sr %rd,1 Bits 15–0 in %rd logically shifted one bit to the right sl %rd,7 Bits 15–0 in %rd logically shifted four bits to the left sa %rd,0xf Bits 15–0 in %rd arithmetically shifted eight bits to the right

imm5 or the rs reg-

The swap instruction replaces the contents of general-purpose registers with each other, as shown below.

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5.8 Branch and Delayed Branch Instructions

S 0

8 7

sign7

0

sign8

SS S S S S S S S S S S S S S S

23 1

0

Current address

PC

Branch destination address

PC

+ 2

+

S 0

11 10

sign10

0

sign11

SS S S S S S S S S S S S

23 1

0

Current address

PC

Branch destination address

PC

+ 2

+

5.8.1 Types of Branch Instructions

(1) PC relative jump instructions

PC relative jump instructions include the following:

jr* sign7

jpr

sign10

%rb

5 INSTRUCTION SET

PC relative jump instructions are provided for relocatable programming, so that the program branches to the ad

dress calculated as PC + 2 (the next address of the branch instruction) + signed displacement (specified by the operand).

The number of instruction steps to the jump address is specified for

tion length in the S1C17 Core is fixed to 16 bits, the value of

sign7/10 or rb. However, since the instruc-

sign7/10 is doubled to become a word address in

16-bit units. Therefore, the displacement actually added to the PC is a signed 8-bit/11-bit quantity derived by doubling sign7/10 (least significant bit always 0). When the rb register is used to specify the displacement, the register contents are added to the PC without doubling.

The specifiable displacement can be extended by the

ext instruction, as shown below.

For branch instructions used singly

jr* sign7 Functions as “jr* sign8” (sign8 = {sign7, 0})

For the

jr* instructions that are used singly, a signed 7-bit displacement (sign7) can be specified.

The range of addresses to which jumped is (PC - 126) to (PC + 128).

jpr sign10 Functions as “jpr sign11” (sign11 = {sign10, 0})

For the

jpr instruction that is used singly, a signed 10-bit displacement (sign10) can be specified.

-

The range of addresses to which jumped is (PC - 2,046) to (PC + 2,048).

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5 INSTRUCTION SET

S 0

20 8 7

imm13 sign7

0

sign21

S S S

23 21 1

+ 2

+

0

Current address

PC

Branch destination address

PC

S 0

11 10

imm13 sign10

0

sign24

23 1

+ 2

+

0

Current address

PC

Branch destination address

PC

0

23 21 20 8 7

imm13'S sign7

0

sign24

1

imm13(2:0)

0

Current address

PC

Branch destination address

PC

+ 2

+

When extended by one ext instruction

ext imm13 jr*

sign7 Functions as “jr* sign21” (sign21 = {imm13, sign7, 0})

The

imm13 specified by the ext instruction is extended as the 13 high-order bits of sign21.

The range of addresses to which jumped is (PC - 1,048,574) to (PC + 1,048,576).

ext imm13

jpr

The

sign10 Functions as “jpr sign24” (sign24 = {imm13, sign10, 0})

imm13 specified by the ext instruction is extended as the 13 high-order bits of sign24.

The range of addresses to which jumped is (PC - 8,388,606) to (PC + 8,388,608).

When extended by two

ext instructions

ext imm13 ext jr*

The

imm13' sign7 Functions as “jr* sign24”

imm13 specified by the first ext instruction is effective for only 3 bits, from bit 2 to bit 0 (with the 10

high-order bits ignored), so that sign24 is configured as follows:

sign24 = {imm13(2:0), imm13', sign7, 0}

The range of addresses to which jumped is (PC - 8,388,606) to (PC + 8,388,608).

The above range of addresses to which jumped is a theoretical value, and is actually limited by the range of

memory areas used.

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5 INSTRUCTION SET

23

S

D(23:1)

01

%rb

0

X

0

Current address

PC

Branch destination address

PC

+

2

+

jrgt jrge jrlt jrle jrugt jruge jrult jrule jreq jrne

Greater Than Greater or Equal Less Than Less or Equal Unsigned, Greater Than Unsigned, Greater or Equal Unsigned, Less Than Unsigned, Less or Equal Equal Not Equal

Instruction Flag condition

!Z & !(N ^ V)

!(N ^ V)

N ^ V

Z | (N ^ V)

!Z & !C

!C

C

Z | C

Z

!Z

Comparison of A:B

A > B A ≥ B A < B A ≤ B A > B A ≥ B A < B A ≤ B A = B A ≠ B

Remark

Used to compare signed data

Used to compare unsigned data

Comparison of A:B made when “cmp A,B”

23

D(23:1)

01

rb

X

0Branch destination address

PC

jpa %rb

For jpr %rb

jpr %rb

A signed 24-bit relative value is specified for

rb. The jump address is configured as follows: {

rb(23:1), 0}

The least significant bit in the rb register is always handled as 0. The range of addresses to which jumped is (PC - 8,388,606) to (PC + 8,388,608).

The above range of addresses to which jumped is a theoretical value, and is actually limited by the range of

memory areas used.

Branch conditions

The Instructions with names beginning with

jpr instruction is an unconditional jump instruction that always cause the program to branch.

jr are conditional jump instructions for which the respective branch

conditions are set by a combination of flags, so that only when the conditions are satisfied do they cause the program to branch to a specified address. The program does not branch unless the conditions are satisfied.

The conditional jump instructions basically use the result of the comparison of two values by the cmp instruc-

tion to determine whether to branch. For this reason, the name of each instruction includes a character that rep resents relative magnitude.

The types of conditional jump instructions and branch conditions are listed in Table 5.8.1.1.

Table 5.8.1.1 Conditional Jump Instructions and Branch Conditions

-

(2) Absolute jump instructions

The absolute jump instruction jpa causes the program to unconditionally branch to the location indicated by

the content of a specified general-purpose register ( imm24 using the ext instruction) as the absolute address. When the content of the rb register or the immediate is loaded into the PC, its least significant bit is always made 0.

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rb) or an immediate imm7 (can be extended to imm20 or

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5 INSTRUCTION SET

0 000 imm13 imm7

imm7 with one ext

0 0 0 0 0 0 0 0 0 0 0 0 0 0 000

23 20 19 7

imm7

6 0

imm7 with no ext

imm13

(3:0)

imm13' imm7

imm7 with two ext

X

0Branch destination address

PC

jpa imm7

(3) PC relative call instructions

The PC relative call instruction call sign10/%rb is a subroutine call instruction that is useful for relocat-

able programming, as it causes the program to unconditionally branch to a subroutine starting from an address calculated as PC + 2 (the next address of the branch instruction) + signed displacement (specified by the oper and). During branching, the program saves the address of the instruction next to the layed branching, the address of the second instruction following

call) to the stack as the return address. When

call instruction (for de-

the ret instruction is executed at the end of the subroutine, this address is loaded into the PC, and the program returns to it from the subroutine.

Note that because the instruction length is fixed to 16 bits, the least significant bit of the displacement is always

handled as 0 (

As with the PC relative jump instructions, the specifiable displacement can be extended by the

sign10 doubled, rb is not doubled), causing the program to branch to an even address.

ext instruction.

For details on how to extend the displacement, refer to the “(1) PC relative jump instructions.”

(4) Absolute call instructions

The absolute call instruction calla causes the program to unconditionally call a subroutine starting from the

location indicated by the content of a specified general-purpose register ( tended to

imm20 or imm24 using the ext instruction) as the absolute address. When the content of the rb register or the immediate is loaded into the PC, its least significant bit is always made 0. (Refer to the “(2) Absolute jump instructions.”)

rb) or an immediate imm7 (can be ex-

-

(5) Software interrupts

The software interrupts int and intl are the instructions that cause the software to generate an interrupt with

the vector numbers specified by the operand ecuted. When a software interrupt occurs, the processor saves the PSR and the instruction address next to intl to the stack, and reads the specified vector from the vector table in order to execute an interrupt handler routine. Therefore, to return from the interrupt handler routine, the reti instruction must be used, as it restores the PSR as well as the PC from the stack. For details on the software interrupt, refer to Section 6.3, “Interrupts.”

(6) Return instructions

The ret instruction, which is a return instruction for the call and calla instructions, loads the saved return

address from the stack into the PC as it terminates the subroutine. Therefore, the value of the SP when the instruction is executed must be the same as when the subroutine was executed (i.e., one that indicates the return address).

The

stack along with the return address in interrupt handling, the content of the PSR must be restored from the stack using the As in the case of the same as when the subroutine was executed.

(7) Debug interrupts

The brk and retd instructions are used to call a debug interrupt handler routine, and to return from that rou-

tine. Since these instructions are basically provided for the debug firmware, please do not use them in applica tion programs. For details on the functionality of these instructions, refer to Section 6.5, “Debug Circuit.”

imm5, by which a specified interrupt handler routine can be ex-

int/

ret

reti instruction is a return instruction for the interrupt handler routine. Since the PSR is saved to the

reti instruction. In the reti instruction, the PC and the PSR are read out of the stack in that order.

ret instruction, the value of the SP when the reti instruction is executed must be the

-

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5 INSTRUCTION SET

5.8.2 Delayed Branch Instructions

The S1C17 Core uses pipelined instruction processing, in which instructions are executed while other instructions are being fetched. In a branch instruction, because the instruction that follows it has already been fetched when it is executed, the execution cycles of the branch instruction can be reduced by one cycle by executing the prefetched in struction before the program branches. This is referred to as a delayed branch function, and the instruction executed before branching (i.e., the instruction at the address next to the branch instruction) is referred to as a delayed slot instruction. The delayed branch function can be used in the instructions listed below, which in mnemonics is identified by the extension “

Delayed branch instructions

jrgt.d jrge.d jrlt.d jrle.d jrugt.d jruge.d jrult.d

ret.d reti.d

Delayed slot instructions

All instructions other than those listed below can be used as a delayed slot instruction.

Instructions that cannot be used as a delayed slot instruction

The A delayed slot instruction is always executed regardless of whether the delayed branch instruction used is con

In “non-delayed” branch instructions (those not followed by the extension “

.d” added to the branch instruction name.

jrule.d jreq.d jrne.d call.d calla.d jpr.d jpa.d

brk call calla ext halt int jpa jpr jr* ret retd reti slp

ext instruction cannot be used to expand the operand of delayed slot instructions.

ditional or unconditional and whether it branches.

.d”), the instruction at the address next to the branch instruction is not executed if the program branches; however, if it is a conditional jump and the program does not branch, the instruction at the next address is executed as the one that follows the branch instruction.

-

The return address saved to the stack by the

call.d or calla.d instruction becomes the address for the next instruction following the delayed slot instruction, so that the delayed slot instruction is not executed when the program returns from the subroutine.

No interrupts occur in between a delayed branch instruction and a delayed slot instruction, as they are masked

out by hardware.

Application for leaf subroutines

The following shows an example application of delayed branch instructions for achieving a fast leaf subroutine

call.

Example: jpr.d SUB ; Jumps to a subroutine by a delayed branch instruction

ld.a %r7,%pc ; Loads the return address into a general-purpose register by ;

a delayed slot instruction

add.a %r1,%r2 ; Return address

: : SUB: : : jpr %r7 ;

Return

Notes: • The ld.a %rd,%pc instruction must be executed as a delayed slot instruction. If it does not

follow a delayed branch instruction, the PC value that is loaded into the the next instruction address to the

ld.a instruction.

• The delayed branch instruction listed below can only be used with the

rd register may not be

ld.a %rd,%pc de-

layed slot instruction.

-

jpr.d %rb/sign10 jr*.d sign7 jpa.d %rb/imm7

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5 INSTRUCTION SET

5.9 System Control Instructions

The following five instructions are used to control the system.

nop Only increments the PC, with no other operations performed halt Places the processor in HALT mode slp Places the processor in SLEEP mode ei Enables interrupts di Disables interrupts

For details on HALT and SLEEP modes, refer to Section 6.4, “Power-Down Mode,” and the Technical Manual for each S1C17 model. For details on the interrupt control, refer to Section 6.3, “Interrupts.”

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5 INSTRUCTION SET

rs

rd

X

23 8 7 0

23 8

8 bits

7 0

SSSSSSSSSSSSSSSSSS

Byte

rs

rd

23 16 15 0

S

SSSSSSSSS

X

23 16 15

Word

0

15

16 bits

0

rs

rd

23 16 15 0

23 8 7 0

15

Unchanged

0

X 8 bits

8 bits

rs

rd

23 8 0

23 16 15 0

7 0

X8 bits

8 bits00000000 00000000

rs

rd

23 16 15 0

S

00000000 S S S S S S S S SSSSSSSS

X

23 16 15

Word

0

15 0

5.10 Conversion Instructions

The 8/16/24/32 data conversion instructions listed below are provided for supporting C compiler.

cv.ab %rd,%rs Converts Byte data (8 bits) into 24-bit data with sign extended.

cv.as %rd,%rs Converts 16-bit data into 24-bit data with sign extended.

cv.al %rd,%rs Extracts the high-order 8 bits to convert 32-bit data into 24-bit data.

cv.la %rd,%rs Extracts the high-order 8 bits to convert 24-bit data into 32-bit data.

cv.ls %rd,%rs Extends the sign to convert 16-bit data into 32-bit data.

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5.11 Coprocessor Instructions

The S1C17 Core incorporates a coprocessor interface and provides the dedicated coprocessor instructions listed below.

ld.cw Transfer data to the coprocessor ld.ca Transfer data and input the results and flag status to/from the coprocessor ld.cf Input flag status from the coprocessor

The ld.cw and ld.ca instructions send two 24-bit data set in the rd (data 0) and rs (data 1) registers to the copro cessor. Data 1 can also be specified in an immediate imm20 or imm24 using the ext instruction. The ld.ca instruction inputs the results from the coprocessor to the rd register. The ld.ca and ld.cf instructions input the flag status from the coprocessor and set it to the PSR (C, V, Z, and N flags). The concrete commands and status of the coprocessor vary with each coprocessor connected to the chip. Refer to the user’s manual for the coprocessor used.

imm7. In this case, the 7-bit immediate can be extended into

-

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6 Functions

Program execution state

Interrupt handling

Debug interrupt handling

SLEEP mode

Reset state

HALT mode

slp

instruction

Interrupt

Debug

interrupt

retd

instruction

Interrupt

reti

instruction

halt

instruction

Interrupt

This chapter describes the processing status of the S1C17 Core and outlines the operation.

6.1 Transition of the Processor Status

The diagram below shows the transition of the operating status in the S1C17 Core.

Figure 6.1.1 Processor Status Transition Diagram

6 FUNCTIONS

6.1.1 Reset State

The processor is initialized when the reset signal is asserted, and then starts processing from the reset vector when the reset signal is deasserted.

6.1.2 Program Execution State

This is a state in which the processor executes the user program sequentially. The processor state transits to another when an interrupt occurs or the slp or halt instruction is executed.

6.1.3 Interrupt Handling

When a software or other interrupt occurs, the processor enters an interrupt handling state. The following are the possible causes of the need for interrupt handling:

(1) External interrupt (2) Software interrupt (3) Address misaligned interrupt (4) NMI

6.1.4 Debug Interrupt

The S1C17 Core incorporates a debugging assistance facility to increase the efficiency of software development. To use this facility, a dedicated mode known as “debug mode” is provided. The processor can be switched from user mode to this mode by the brk instruction or a debug interrupt. The processor does not normally enter this mode.

6.1.5 HALT and SLEEP Modes

The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp instruction in the software (see Section 6.4). Normally the processor can be taken out of HALT or SLEEP mode by NMI or an external interrupt as well as initial reset.

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6-1

6 FUNCTIONS

Instruction fetch

Instruction decode

Instruction execution / Memory access / Register write

F D

E

Clock

PC

PC + 2

PC + 4

6.2 Program Execution

Following initial reset, the processor loads the reset vector (address of the reset handler routine) into the PC and starts executing instructions beginning with the address. As the instructions in the S1C17 Core are fixed to 16 bits in length, the PC is incremented by 2 each time an instruction is fetched from the address indicated by the PC. In this way, instructions are executed successively.

When a branch instruction is executed, the processor checks the PSR flags and whether the branch conditions have been satisfied, and loads the jump address into the PC.

When an interrupt occurs, the processor loads the address for the interrupt handler routine from the vector table into the PC. The vector table contains interrupt vectors beginning with the reset vector and is located from the address set in the TTBR register (0xffff80). The start address can be set to the TTBR in the configuration.

6.2.1 Instruction Fetch and Execution

Internally in the S1C17 Core, instructions are processed in three pipelined stages, so that the basic instructions except for the branch instructions and data transfer instructions with the memory address increment/decrement function can be executed in one clock cycle. Pipelining speeds up instruction processing by executing one instruction while fetching another. In the 3-stage pipeline, each instruction is processed in three stages, with processing of instructions occurring in parallel, for faster instruction execution.

Basic instruction stages

Hereinafter, each stage is represented by the following symbols: F (for D (for E (for

Fetch): Instruction fetch

Decode): Instruction decode

Execute): Instruction execution, memory access, register write

Pipelined operation

Figure 6.2.1.1 Pipelined Operation

Note: The pipelined operation shown above uses the internal memory. If external memory or low-speed

external devices are used, one or more wait cycles may be inserted depending on the devices used, with the E stage kept waiting.

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6 FUNCTIONS

Classification

Data transfer

ld.b

ld.ub

ld

ld.a

%rd,%rs

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]- %rd,-[%rb] %rd,[%sp+imm7

]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb],%rs [%sp+imm7

],%rs

[imm7],%rs

%rd,%rs

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,

[imm7]

%rd,%rs

%rd,sign7

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]- %rd,-[%rb] %rd,[%sp+imm7]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb

],%rs

[%sp+imm7

],%rs

[imm7],%rs

%rd,%rs

%rd,imm7

%rd,

[%rb]

%rd,

[%rb]+

%rd,

[%rb]-

%rd,-

[%rb]

%rd,[%sp+imm7

]

%rd,

[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs

-[%rb

],%rs

[%sp+imm7

],%rs

[imm7],%rs

%rd,%sp %rd,%pc %rd,[%sp] %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp]

Mnemonic

Remark

∗1: 1 cycle when ext is not

used

2 cycles when ext is used

Cycle

1

1–2

∗1

2 2 2 2 1

1–2

∗1

2 2 2 2 1 1

1–2

∗1

2 2 2 2 1 1 1

1–2

∗1

2 2 2 2 1

1–2

∗1

2 2 2 2 1 1 1

1–2

∗1

2 2 2 2 1

1–2

∗1

2 2 2 2 1 1 1

1–2

∗1

2 2 2

C

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

IE

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

IL

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

V

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Z

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

N

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Flag

6.2.2 Execution Cycles and Flags

The following shows the number of cycles required for executing each instruction in a 1-cycle accessible memory connected to the Harvard bus and the flag change status. Depending on the model, clock cycles spent by the external bus arbiter and wait cycles inherent in the external devices may be added.

Table 6.2.2.1 Number of Instruction Execution Cycles and Flag Status

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6-3

6 FUNCTIONS

Classification

Data transfer

Integer arithmetic operation

Logical operation

ld.a

add add/c add/nc add add.a add.a/c add.a/nc add.a

adc adc/c adc/nc adc sub sub/c sub/nc sub sub.a sub.a/c sub.a/nc sub.a

sbc sbc/c sbc/nc sbc cmp cmp/c cmp/nc cmp cmp.a cmp.a/c cmp.a/nc cmp.a cmc cmc/c cmc/nc cmc and and/c and/nc and or or/c or/nc or xor xor/c xor/nc xor not not/c not/nc not

[%sp],%rs [%sp]+,%rs [%sp]-,%rs

-[%sp],%rs %sp,%rs %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,%rs %sp,%rs

%rd,imm7 %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,%rs %sp,%rs

%rd,imm7 %sp,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

%rd,%rs

%rd,sign7

Mnemonic

Remark

∗1: 1 cycle when ext is not

used

2 cycles when ext is used

Cycle

1–2

∗1

2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C

– – – – – –

↔

– –

↔

– – – – – –

↔

– –

↔

– –

↔

– – – – – –

↔

– –

↔

– –

↔

– –

↔

– –

↔

– – – – – – – – – – – – – – – –

IE

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

IL

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

V

– – – – – –

↔

– – – – – –

↔

– – – – – –

↔

– – – –

↔

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Z

– – – – – –

↔

– – – – – –

↔

– – – – – –

↔

N

– – – – – –

↔

– – – – – –

↔

– – – – – –

↔

– – – –

↔

Flag

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6 FUNCTIONS

Classification

Shift and swap

Immediate extension Conversion

Branch

System control

Coprocessor control

sr

sa

sl

swap ext cv.ab cv.as cv.al cv.la cv.ls jpr jpr.d jpa ipa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d int intl reti reti.d brk retd nop halt slp ei di ld.cw

ld.ca

ld.cf

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

imm13

%rd,%rs

sign10

%rb

imm7

%rb

sign7

sign10

%rb

imm7

%rb

imm5

imm5,imm3

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

%rd,%rs

%rd,imm7

Mnemonic

Remark

∗2: 2 cycles when not

jumped

3 cycles when jumped

Cycle

1 1 1 1 1 1 1 1 1 1 1 1 1 3

2(.d)

3

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

2–3

∗2

2(.d)

4

3(.d)

4

3(.d)

3

2(.d)

3 3 3

2(.d)

4 4 1 6 6 1 1 1

1

C

↔

– – – – – – – –

–

– –

↔

–

↔

– – – – – –

↔

IE

– – – – – – – – – – – – – –

–

0 0

↔

0

↔

– – – 1 0 –

–

IL

– – – – – – – – – – – – – –

–

↔

–

↔

– – – – – –

–

V

– – – – – – – – – – – – – –

–

– –

↔

–

↔

– – – – – –

↔

Z

↔

– – – – – – – –

–

– –

↔

–

↔

– – – – – –

↔

N

↔

– – – – – – – –

–

– –

↔

–

↔

– – – – – –

↔

Flag

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6-5

6 FUNCTIONS

Interrupt

Reset Address misaligned interrupt Debug interrupt NMI Software interrupt Maskable external interrupt

Vector address (Hex)

TTBR + 0x00 TTBR + 0x04

(0xfffc00)

TTBR + 0x08

TTBR + 0x00 to

TTBR + 0x7c

TTBR + 0x00 to

TTBR + 0x7c

Priority

High

Low

Address

0xfffc00 DBRAM set value + 0x00 DBRAM set value + 0x04

Content

Debug interrupt handler start address

PC and PSR save area

R0 save area

(DBRAM: See Section 4.2.3)

6.3 Interrupts

When an interrupt occurs during program execution, the processor enters an interrupt handling state. The interrupt handling state is a process by which the processor branches to the corresponding user’s service routine for the interrupt that occurred. The processor returns after branching and starts executing the program from where it left off.

6.3.1 Priority of Interrupts

The interrupts supported by the S1C17 Core, their vector addresses and the priority of these interrupts are listed in the table below.

Table 6.3.1.1 Vector Address and Priority of Interrupts

When two or more interrupts occur simultaneously, they are processed in order of priority beginning with the one that has the highest priority.

When an interrupt occurs, the processor disables interrupts that would occur thereafter and performs interrupt handling. To support multiple interrupts (or another interrupt from within an interrupt), set the IE flag in the PSR to 1 in the interrupt handler routine to enable interrupts during interrupt handling. Basically, even when multiple interrupts are enabled, interrupts whose priorities are below the one set by the IL[2:0] bits in the PSR are not accepted.

The debug interrupt does not use the vector table and the stack. The PC and PSR are saved in a specific area along with R0. The table below shows the addresses that are referenced when a debug interrupt occurs.

During debug interrupt handling, neither other interrupts nor multiple debug interrupts are accepted. They are kept pending until the debug interrupt handling currently underway finishes.

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Table 6.3.1.2 Debug Interrupt Handler Start Address and Register Save Area

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Interrupt

Reset Address misaligned interrupt NMI Maskable external interrupt 3

:

Maskable external interrupt 31

Vector No.

Software interrupt No.

0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03)

:

31 (0x1f)

Vector address

TTBR + 0x00 TTBR + 0x04 TTBR + 0x08 TTBR + 0x0c

:

TTBR + 0x7c

6.3.2 Vector Table

Vector table in the S1C17 Core

The table below lists the interrupts for which the vector table is referenced during interrupt handling.

Table 6.3.2.1 Vector List

The vector address is one that contains a vector (or the jump address) for the user’s interrupt handler routine

that is provided for each interrupt and is executed when the relevant interrupt occurs. Because an address value is stored, each vector address is located at a 16-bit boundary. The memory area in which these vectors are stored is referred to as the “vector table.” The “TTBR” in the Vector Address column represents the base (start) address of the vector table. For the TTBR value, refer to the Technical Manual of each model. The set value can be read from TTBR (trap table base register) located at address 0xffff80.

6.3.3 Interrupt Handling

When an interrupt occurs, the processor starts interrupt handling. (This interrupt handling does not apply for reset and debug interrupts.)

The interrupt handling performed by the processor is outlined below.

(1) Suspends the instructions currently being executed. An interrupt is generated synchronously with the rising edge of the system clock at the end of the cycle of the

currently executed instruction.

(2) Saves the contents of the PC and PSR to the stack (SP), in that order.

(3) Clears the IE (interrupt enable) bit in the PSR to disable maskable interrupts that would occur thereafter. If

the generated interrupt is a maskable interrupt, the IL (interrupt level) in the PSR is rewritten to that of the generated interrupt.

(4) Reads the vector for the generated interrupt from the vector table, and sets it in the PC. The processor thereby

branches to the user’s interrupt handler routine.

After branching to the user’s interrupt handler routine, when the reti instruction is executed at the end of interrupt handling, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the suspended instructions.

6.3.4 Reset

The processor is reset by applying a low-level pulse to its rst_n pin. All the registers are thereby cleared to 0. The processor starts operating at the rising edge of the reset pulse to perform a reset sequence. In this reset sequence, the reset vector is read out from the top of the vector table and set in the PC. The processor thereby branches to the user’s initialization routine, in which it starts executing the program. The reset sequence has priority over all other processing.

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6.3.5 Address Misaligned Interrupt

The load instructions that access memory or I/O areas are characteristic in that the data size to be transferred is predetermined for each instruction used, and that the accessed addresses must be aligned with the respective datasize boundaries.

Instruction Transfer data size Address

ld.b/ld.ub Byte (8 bits) Byte boundary (applies to all addresses) ld 16 bits 16-bit boundary (least significant address bit = 0) ld.a 32 bits 32-bit boundary (two least significant address bits = 00)

If the specified address in a load instruction does not satisfy this condition, the processor assumes an address misaligned interrupt and performs interrupt handling. Even in this case the load instruction is executed as the least significant bit or the two low-order bits of the address set to 0. The PC value saved to the stack in interrupt handling is the address of the load instruction that caused the interrupt.

This interrupt does not occur in the program branch instructions as the least significant bit of the PC is always fixed to 0. The same applies to the vector for interrupt handling.

6.3.6 NMI

An NMI is generated when the nmi_n input on the processor is asserted low. When an NMI occurs, the processor performs interrupt handling after it has finished executing the instruction currently underway.

6.3.7 Maskable External Interrupts

The S1C17 Core can accept up to 32 types of maskable external interrupts (however, the first three interrupt causes use the save vector address as the reset interrupt, address misaligned interrupt, and NMI). It is only when the IE (interrupt enable) flag in the PSR is set that the processor accepts a maskable external interrupt. Furthermore, their acceptable interrupt levels are limited by the IL (interrupt level) field in the PSR. The interrupt levels (0–7) in the IL field dictate the interrupt levels that can be accepted by the processor, and only interrupts with priority levels higher than that are accepted. Interrupts with the same interrupt level as IL cannot be accepted. The IE flag can be set in the software. When an interrupt occurs, the IE flag is cleared to 0 (interrupts disabled) after the PSR is saved to the stack, and the maskable interrupts remain disabled until the IE flag is set in the handler routine or the handler routine is terminated by the field is set to the priority level of the interrupt that occurred. Multiple interrupts or the ability to accept another interrupt during interrupt handling if its priority is higher than that of the currently serviced interrupt can easily be realized by setting the IE flag in the interrupt handler routine. When the processor is reset, the PSR is initialized to 0 and the maskable interrupts are therefore disabled, and the interrupt level is set to 0 (interrupts with priority levels 1–7 enabled).

The following describes how the maskable interrupts are accepted and processed by the processor.

(1) Suspends the instructions currently being executed. The interrupt is accepted synchronously with the rising edge of the system clock at the end of the cycle of the

currently executed instruction.

(2) Saves the contents of the PC (current value) and PSR to the stack (SP), in that order.

(3) Clears the IE flag in the PSR and copy the priority level of the accepted interrupt to the IL field.

(4) Reads the vector for the interrupt from the vector address in the vector table, and sets it in the PC. The processor

then branches to the interrupt handler routine.

In the interrupt handler routine, the instruction, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the suspended instructions.

reti instruction should be executed at the end of processing. In the reti

reti instruction that restores the PSR from the stack. The IL

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6.3.8 Software Interrupts

The S1C17 Core provides the int imm5 and intl imm5,imm3 instructions allowing the software to generate any interrupts. The operand

imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction has the operand imm3 to specify an interrupt level (0–7) to be set to the IL field in the PSR. The processor performs the same interrupt handling as that of a hardware interrupt.

6.3.9 Interrupt Masked Period

Address misaligned interrupts, NMIs, debug interrupts, and external maskable interrupts are masked between the specific instructions listed below and cannot be generated during that period (pending state). When the processor exits the masked period, the pending interrupt can be accepted.

(1) Between the (2) Between a delayed branch ( (3) Between the (4) Between the (5) Between the int, ei, di, slp, or halt instruction and the next instruction (6) Between a conditional jump (jr*) instruction and the next instruction when the condition has not been met

∗1 An interrupt that occurs when the reti.d instruction is being executed will be accepted after the delayed slot

instruction that follows and the next instruction (located at the return address) are executed.

|

reti.d

Delayed slot instruction Interrupt masked state

|

Instruction at return address Interrupt masked state still continues, so the next instruction will be executed

Next instruction Interrupt mask is released.

∗2 The debug interrupt may occur even in the conditions (4) to (6).

ext instruction and the next instruction

.d) instruction and the delayed slot instruction that follows retd instruction and the next instruction (located at the return address) reti or reti.d ∗1 instruction and the next instruction (located at the return address)

∗2

before interrupts can be generated.

∗2

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6.4 Power-Down Mode

The S1C17 Core supports two power-down modes: HALT and SLEEP modes.

HALT mode

Program execution is halted at the same time that the S1C17 Core executes the halt instruction, and the

processor enters HALT mode.

HALT mode commonly turns off only the S1C17 Core operation, note, however that modules to be turned off

depend on the implementation of the clock control circuit outside the core. Refer to the technical manual of each model for details.

SLEEP mode

Program execution is halted at the same time the S1C17 Core executes the slp instruction, and the processor

enters SLEEP mode.

SLEEP mode commonly turns off the S1C17 Core and on-chip peripheral circuit operations, thereby it

significantly reduces the current consumption in comparison to HALT mode. However, modules to be turned off depend on the implementation of the clock control circuit outside the core. Refer to the technical manual of each model for details.

Canceling HALT or SLEEP mode

Initial reset is one cause that can bring the processor out of HALT or SLEEP mode. Other causes depend on the

implementation of the clock control circuit outside the S1C17 Core.

Initial reset, maskable external interrupts, NMI, and debug interrupts are commonly used for canceling HALT

and SLEEP modes.

The interrupt enable/disable status set in the processor does not affect the cancellation of HALT or SLEEP

mode even if an interrupt signal is used as the cancellation. In other words, interrupt signals are able to cancel HALT and SLEEP modes even if the IE flag in PSR or the interrupt enable bits in the interrupt controller (depending on the implementation) are set to disable interrupts.

When the processor is taken out of HALT or SLEEP mode using an interrupt that has been enabled (by the

interrupt controller and IE flag), the corresponding interrupt handler routine is executed. Therefore, when the interrupt handler routine is terminated by the halt or slp.

When the interrupt has been disabled, the processor restarts the program from the instruction next to

slp after the processor is taken out of HALT or SLEEP mode.

reti instruction, the processor returns to the instruction next to

halt or

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6.5 Debug Circuit

The S1C17 Core has a debug circuit to assist in software development by the user.

6.5.1 Debugging Functions

The debug circuit provides the following functions:

• Instruction break

A debug interrupt is generated before the set instruction address is executed. An instruction break can be set at

two addresses.

• Single step

A debug interrupt is generated every instruction executed.

• Forcible break

A debug interrupt is generated by an external input signal.

• Software break

A debug interrupt is generated when the

When a debug interrupt occurs, the processor performs the following processing:

(1) Suspends the instructions currently being executed.

(2) Saves the contents of the PC and PSR, and R0, in that order, to the addresses specified below. PC/PSR R0

→ DBRAM + 0x0 → DBRAM + 0x4 (DBRAM: Start address of the work area for debugging in the user RAM)

brk instruction is executed.

(3) Loads address 0xfffc00 to PC and branches to the debug interrupt handler routine.

In the interrupt handler routine, the suspended instructions. When returning from the interrupt by the data in order of the R0 and the PC and PSR. Neither hardware interrupts nor NMI interrupts are accepted during a debug interrupt.

retd instruction should be executed at the end of processing to return to the

retd instruction, the processor restores the saved

6.5.2 Resource Requirements and Debugging Tools

The on-chip debug function requires a 64-byte work area. For the work area for debugging, refer to the Technical Manual of each model.

Debugging is performed by connecting a serial ICE to the debug pins of the S1C17 Core and entering debug commands from the debugger being run on a personal computer. The tools listed below are required for debugging.

• S1C17 Family Serial ICE (S5U1C17001H)

• S1C17 Family C Compiler Package

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6 FUNCTIONS

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0

0x0–0xFFFDC0

(64 byte units)

– DBRAM23 | DBRAM0

D31–24

D23

|

D0

Unused (fixed at 0) Debug RAM base address DBRAM[5:0] is fixed at 0x0.

0x0

∗

R R

Initial value is set in the C17 RTL-define DBRAM_BASE.

FFFF90

(L)

Debug RAM base register

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

–

– DR IBE1 IBE0 SE DM

D7–5

D4 D3 D2 D1 D0

Reserved Debug request flag Instruction break #1 enable Instruction break #0 enable Single step enable Debug mode

– 0 0 0 0 0

– R/W R/W R/W R/W

R

0 when being read. Reset by writing 1.

FFFFA0

(B)

Debug control register

1

Occurred

0

Not occurred

1

Enable

0

Disable

1

Enable

0

Disable

1

Enable

0

Disable

1

Debug mode

0

User mode

6.5.3 Registers for Debugging

The reserved core I/O area contains the debug registers described below.

0xFFFF90: Debug RAM Base Register (DBRAM)

D[23:0] DBRAM[23:0]: Debug RAM Base Address Bits

This is a read-only register that contains the start address of a work area (64 bytes) for debugging.

0xFFFFA0: Debug Control Register (DCR)

D[7:5] Reserved

D4 DR: Debug Request Flag

Indicates whether an external debug request has occurred or not. 1 (R): Occurred 0 (R): Not occurred (default) 1 (W): Flag is reset 0 (W): Has no effect

This flag is cleared (reset to 0) by writing 1. The flag must be cleared before the debug handler routine

has been terminated by executing the

retd instruction.

D3 IBE1: Instruction Break #1 Enable Bit

Enables/disables instruction break #1. 1 (R/W): Enable 0 (R/W): Disable (default)

When this bit is set to 1, instruction fetch addresses will be compared with the value set in the

Instruction Break Address Register 1 (0xffffb4), and an instruction break will occur if they are matched. Setting this bit to 0 disables the comparison.

D2 IBE0: Instruction Break #0 Enable Bit

Enables/disables instruction break #0. 1 (R/W): Enable 0 (R/W): Disable (default)

When this bit is set to 1, instruction fetch addresses will be compared with the value set in the

Instruction Break Address Register 0 (0xffffb0), and an instruction break will occur if they are matched. Setting this bit to 0 disables the comparison.

D1 SE: Single Step Enable Bit

Enables/disables single-step execution. 1 (R/W): Enable 0 (R/W): Disable (default)

D0 DM: Debug Mode Bit

Indicates the current operation mode of the processor (debug mode or user mode). 1 (R): Debug mode 0 (R): User mode (default)

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0xFFFFB0: Instruction Break Address Register 0 (IBAR0)

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0

0x0–0xFFFDE

– IBAR023 | IBAR00

D31–24

D23

|

D0

Unused (fixed at 0) Instruction break address #0 IBAR00 is fixed at 0.

0x0 0x0

R R/W

FFFFB0

(L)

Instruction break address register 0

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0

0x0–0xFFFDE

– IBAR123 | IBAR10

D31–24

D23

|

D0

Unused (fixed at 0) Instruction break address #1 IBAR10 is fixed at 0.

0x0 0x0

R R/W

FFFFB4

(L)

Instruction break address register 1

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

–

– RXDEN TDBE RDBF

D7–3

D2 D1 D0

Reserved Receive disable Transmit data buffer empty flag Receive data buffer full flag

– 1 1 0

– R/W

R

0 when being read.

FFFFC0

(B)

Serial status register for debugging

1

Disable

0

Enable

1

Empty

0

Not empty

1

Full

0

Not full

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0–0xFF

TXRXD7 | | TXRXD0

D7

| |

D0

Transmit/receive data

0x0

R/W

FFFFC2

(B)

Serial transmit/ receive data register for debugging

D[23:0] IBAR0[23:0]: Instruction Break Address #0

This register is used to set instruction break address #0. (Default: 0x000000)

0xFFFFB4: Instruction Break Address Register 1 (IBAR1)

D[23:0] IBAR1[23:0]: Instruction Break Address #1

This register is used to set instruction break address #1. (Default: 0x000000)

0xFFFFC0: Serial Status Register for Debugging (SSR)

6 FUNCTIONS

D[7:3] Reserved

D2 RXDEN: Receive Disable Bit

Enables/disables receive operation in the serial interface for the on-chip debug monitor. 1 (R/W): Disable (default) 0 (R/W): Enable

D1 TDBE: Transmit Data Buffer Empty Flag

Indicates transmit buffer status in the serial interface for the on-chip debug monitor. 1 (R): Empty (default) 0 (R): Not empty

D0 RDBF: Receive Data Buffer Full Flag

Indicates receive buffer status in the serial interface for the on-chip debug monitor. 1 (R): Full 0 (R): Not full (default)

0xFFFFC2: Serial Transmit/Receive Data Register for Debugging (SDR)

D[7:0] TXRXD[7:0]: Transmit/Receive Data

This is the transmit/receive data register of the serial interface for the on-chip debug monitor used to set

transmit data and to store received data. (Default: 0x00)

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7 DETAILS OF INSTRUCTIONS

7 Details of Instructions

This section explains all the instructions in alphabetical order.

Symbols in the instruction reference

%rd, rd General-purpose registers (R0–R7) or their contents used as the destination %rs, rs General-purpose registers (R0–R7) or their contents used as the source %rb, rb General-purpose registers (R0–R7) or their contents that hold the base address to be accessed in

register indirect addressing

%sp, sp Stack pointer (SP) or its content %pc, pc Program counter (PC) or its content

The register field (rd R0 = 0b000, R1 = 0b001 . . . R7 = 0b111

immX Unsigned immediate X bits in length. The X contains a number representing the bit length of the

immediate.

signX Signed immediate X bits in length. The X contains a number representing the bit length of the

immediate. Furthermore, the most significant bit is handled as the sign bit. IL Interrupt level field IE Interrupt enable flag C Carry flag V Overflow flag Z Zero flag N Negative flag – Indicates that the bit is not changed by instruction execution

↔ Indicates that the bit is set (= 1) or reset (= 0) by instruction execution 1 Indicates that the bit is set (= 1) by instruction execution 0 Indicates that the bit is reset (= 0) by instruction execution

, rs) in the code contains a general-purpose register number.

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7 DETAILS OF INSTRUCTIONS

adc %rd, %rs adc/c %rd, %rs adc/nc %rd, %rs

Function

Standard) rd(15:0) Extension 1) rd(15:0) Extension 2) rd(15:0)

Code

Flag

16-bit addition with carry

← rd(15:0) + rs(15:0) + C, rd(23:16) ← 0 ← rs(15:0) + imm13(zero extended) + C, rd(23:16) ← 0 ← rs(15:0) + imm16 + C, rd(23:16) ← 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 1 1 0

| | | | |

0 0 1 1 1 0

| | | | |

0 0 1 1 1 0

| | | | |

IL IE C V Z N

– –

– – –

↔ ↔ ↔ ↔

| | |

| |

↔ ↔ ↔

| |

r d 1 0 0 1 r s

|

| | | | | |

r d 0 0 0 1 r s

|

| | | | | |

r d 0 1 0 1 r s

|

| | | | | |

adc

adc/c, adc/nc

|

adc

|

adc/c

|

adc/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

adc

(1) Standard

%rd,%rs ; rd ← rd + rs + C

%rd = %r0 to %r7

The content of the rs register and C (carry) flag are added to the rd register. The operation is

performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

(2) Extension 1

ext adc

The 13-bit immediate

imm13 %rd,%rs ; rd ← rs + imm13 + C

imm13 and C (carry) flag are added to the content of the rs register after being zero-extended, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(3) Extension 2

ext ext adc

The 16-bit immediate

imm13 ; imm13(2:0) = imm16(15:13) imm13 ; = imm16(12:0) %rd,%rs ; rd ← rs + imm16 + C

imm16 and C (carry) flag are added to the content of the rs register, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. adc/c Executed as adc when the C flag is 1 or executed as nop when the flag is 0 adc/nc Executed as adc when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) adc %r0,%r1 ; r0 = r0 + r1 + C

(2) Addition of 32-bit data, data 1 = {r2, r1}, data 2 = {r4, r3}, result = {r2, r1} add %r1,%r3 ; Addition of the low-order word

adc %r2,%r4 ; Addition of the high-order word

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adc %rd, imm7

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(15:0) Extension 1) rd(15:0)

16-bit addition with carry

← rd(15:0) + imm7(zero extended) + C, rd(23:16) ← 0 ← rd(15:0) + imm16 + C, rd(23:16) ← 0

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

1 0 0 0 0 1

| | | | | | | | | | | | |

– –

↔ ↔ ↔ ↔

| | |

| |

r d imm7

|

Mode

Src: Immediate data (unsigned)

Dst: Register direct

CLK

One cycle

Description

adc

(1) Standard

%rd,imm7 ; rd ← rd + imm7 + C

The 7-bit immediate imm7

%rd = %r0 to %r7

and C (carry) flag are added to the rd register after being zero-

extended. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

(2) Extension 1

ext adc

The 16-bit immediate

imm13 ; imm13(8:0) = imm16(15:7) %rd,imm7 ; rd ← rd + imm16 + C, imm7 = imm16(6:0)

imm16 and C (carry) flag are added to the rd register. The operation is

performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

(3) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) adc %r0,0x7f ; r0 = r0 + 0x7f + C

ext 0x1ff

adc %r1,0x7f ; r1 = r1 + 0xffff + C

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add %rd, %rs add/c %rd, %rs add/nc %rd, %rs

Function

Standard) rd(15:0) Extension 1) rd(15:0) Extension 2) rd(15:0)

Code

Flag

16-bit addition

← rd(15:0) + rs(15:0), rd(23:16) ← 0 ← rs(15:0) + imm13(zero extended), rd(23:16) ← 0 ← rs(15:0) + imm16, rd(23:16) ← 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 1 1 0

| | | | |

0 0 1 1 1 0

| | | | |

0 0 1 1 1 0

| | | | |

IL IE C V Z N

– –

– – –

↔ ↔ ↔ ↔

| | |

| |

↔ ↔ ↔

| |

r d 1 0 0 0 r s

|

| | | | | |

r d 0 0 0 0 r s

|

| | | | | |

r d 0 1 0 0 r s

|

| | | | | |

add

add/c, add/nc

|

add

|

add/c

|

add/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

add

(1) Standard

%rd,%rs ; rd ← rd + rs

%rd = %r0 to %r7

The content of the rs register is added to the rd register. The operation is performed in 16-bit

size, and bits 23–16 of the rd register are set to 0.

(2) Extension 1

ext add

The 13-bit immediate

imm13 %rd,%rs ; rd ← rs + imm13

imm13 is added to the content of the rs register after being zero-extended, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(3) Extension 2

ext ext add

The 16-bit immediate

imm13 ; imm13(2:0) = imm16(15:13) imm13 ; = imm16(12:0) %rd,%rs ; rd ← rs + imm16

imm16 is added to the content of the rs register, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. add/c Executed as add when the C flag is 1 or executed as nop when the flag is 0 add/nc Executed as add when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add %r0,%r0 ; r0 = r0 + r0

ext 0x1

ext 0x1fff add %r1,%r2 ; r1 = r2 + 0x3fff

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S1C17 FAMILY S1C17 CORE MANUAL

add %rd, imm7

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(15:0) Extension 1) rd(15:0)

16-bit addition

← rd(15:0) + imm7(zero extended), rd(23:16) ← 0 ← rd(15:0) + imm16, rd(23:16) ← 0

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

1 0 0 0 0 0

| | | | | | | | | | | | |

– –

↔ ↔ ↔ ↔

| | |

| |

r d imm7

|

Mode

Src: Immediate data (unsigned)

Dst: Register direct

CLK

One cycle

Description

add

(1) Standard

%rd,imm7 ; rd ← rd + imm7

%rd = %r0 to %r7

The 7-bit immediate imm7 is added to the rd register after being zero-extended. The operation is

performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

(2) Extension 1

ext add

The 16-bit immediate

imm13 ; imm13(8:0) = imm16(15:7) %rd,imm7 ; rd ← rd + imm16, imm7 = imm16(6:0)

imm16 is added to the rd register. The operation is performed in 16-bit

size, and bits 23–16 of the rd register are set to 0.

(3) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add %r0,0x3f ; r0 = r0 + 0x3f

ext 0x1ff

add %r1,0x7f ; r1 = r1 + 0xffff

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-5

7 DETAILS OF INSTRUCTIONS

add.a %rd, %rs add.a/c %rd, %rs add.a/nc %rd, %rs

Function

Standard) rd(23:0) Extension 1) rd(23:0) Extension 2) rd(23:0)

Code

Flag

24-bit addition

← rd(23:0) + rs(23:0) ← rs(23:0) + imm13(zero extended) ← rs(23:0) + imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 1 0 0

| | | | |

0 0 1 1 0 0

| | | | |

0 0 1 1 0 0

| | | | |

IL IE C V Z N

– – – – – –

| | |

| |

r d 1 0 0 0 r s

|

| | | | | |

r d 0 0 0 0 r s

|

| | | | | |

r d 0 1 0 0 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

add.a

%rd = %r0 to %r7

%rd,%rs ; rd ← rd + rs

The content of the rs register is added to the rd register.

(2) Extension 1

ext add.a

The 13-bit immediate

imm13 %rd,%rs ; rd ← rs + imm13

imm13 is added to the content of the rs register after being zero-extended,

and the result is loaded into the rd register. The content of the rs register is not altered.

|

add.a

add.a/c

add.a/nc

(3) Extension 2

ext ext add.a

The 24-bit immediate

imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) %rd,%rs ; rd ← rs + imm24

imm24 is added to the content of the rs register, and the result is loaded

into the rd register. The content of the rs register is not altered.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. add.a/c Executed as add.a when the C flag is 1 or executed as nop when the flag is 0 add.a/nc Executed as add.a when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add.a %r0,%r0 ; r0 = r0 + r0

ext 0x7ff

ext 0x1fff add.a %r1,%r2 ; r1 = r2 + 0xffffff

7-6

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

add.a %rd, imm7

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(23:0) Extension 1) rd(23:0) Extension 2) rd(23:0)

Code

Flag

24-bit addition

← rd(23:0) + imm7(zero extended) ← rd(23:0) + imm20(zero extended) ← rd(23:0) + imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 0 0

| | | | | | | | | | | | |

IL IE C V Z N

– – – – – –

| | |

| |

r d imm7

Mode

Src: Immediate data (unsigned)

Dst: Register direct

CLK

One cycle

Description

(1) Standard

add.a

The 7-bit immediate

%rd = %r0 to %r7

%rd,imm7 ; rd ← rd + imm7

imm7 is added to the rd register after being zero-extended.

(2) Extension 1

ext add.a

The 20-bit immediate

imm13 ; = imm20(19:7) %rd,imm7 ; rd ← rd + imm20, imm7 = imm20(6:0)

imm20 is added to the rd register after being zero-extended.

(3) Extension 2

ext ext add.a

imm13 ; imm13(3:0) = imm24(23:20) imm13 ; = imm24(19:7) %rd,imm7 ; rd ← rd + imm24, imm7 = imm24(6:0)

|

The 24-bit immediate

imm24 is added to the rd register.

(4) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add.a %r0,0x7f ; r0 = r0 + 0x7f

ext 0xf ext 0x1fff add.a %r1,0x7f ; r1 = r1 + 0xffffff

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-7

7 DETAILS OF INSTRUCTIONS

add.a %sp, %rs

Function

Standard) Extension 1) Extension 2)

Code

Flag

24-bit addition

sp(23:0) ← sp(23:0) + rs(23:0) sp(23:0) ← rs(23:0) + imm13(zero extended) sp(23:0) ← rs(23:0) + imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 1 0 0 0 0 0 0 0 0 1 r s

| | | | |

IL IE C V Z N

– – – – – –

| | |

| |

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

add.a %sp,

%sp

%rs ; sp ← sp + rs

The content of the rs register is added to the stack pointer SP.

(2) Extension 1

ext add.a %sp,

The 13-bit immediate

imm13

%rs ; sp ← rs + imm13

imm13 is added to the content of the rs register after being zero-extended,

and the result is loaded into the stack pointer SP. The content of the rs register is not altered.

(3) Extension 2

ext ext add.a %sp,

imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0)

%rs ; sp ← rs + imm24

The 24-bit immediate

imm24 is added to the content of the rs register, and the result is loaded

into the stack pointer SP. The content of the rs register is not altered.

(4) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add.a %sp,%r0 ; sp = sp + r0

ext 0x1 ext 0x1fff add.a %sp,%r2 ; sp = r2 + 0x3fff

7-8

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

add.a %sp, imm7

7 DETAILS OF INSTRUCTIONS

Function

Standard) Extension 1) Extension 2)

Code

Flag

24-bit addition

sp(23:0) ← sp(23:0) + imm7(zero extended) sp(23:0) ← sp(23:0) + imm20(zero extended) sp(23:0) ← sp(23:0) + imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 0 1 0 0 0

| | | | | | | | | | | | |

IL IE C V Z N

– – – – – –

| | |

| |

imm7

Mode

Src: Immediate data (unsigned)

Dst: Register direct

CLK

One cycle

Description

(1) Standard

add.a %sp,

The 7-bit immediate

%sp

imm7 ; sp ← sp + imm7

imm7 is added to the stack pointer SP after being zero-extended.

(2) Extension 1

ext add.a %sp,

The 20-bit immediate

imm13 ; = imm20(19:7)

imm7 ; sp ← sp + imm20, imm7 = imm20(6:0)

imm20 is added to the stack pointer SP after being zero-extended.

(3) Extension 2

ext ext add.a %sp,

imm13 ; imm13(3:0) = imm24(23:20) imm13 ; = imm24(19:7)

imm7 ; sp ← sp + imm24, imm7 = imm24(6:0)

|

The 24-bit immediate

imm24 is added to the stack pointer SP.

(4) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) add.a %sp,0x7f ; sp = sp + 0x7f

ext 0x1fff

add.a %sp,0x7f ; sp = sp + 0xfffff

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-9

7 DETAILS OF INSTRUCTIONS

and %rd, %rs and/c %rd, %rs and/nc %rd, %rs

Function

Standard) rd(15:0) Extension 1) rd(15:0) Extension 2) rd(15:0)

Code

Flag

16-bit logical AND

← rd(15:0) & rs(15:0), rd(23:16) ← 0 ← rs(15:0) & imm13(zero extended), rd(23:16) ← 0 ← rs(15:0) & imm16, rd(23:16) ← 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 0 1 1

| | | | |

0 0 1 0 1 1

| | | | |

0 0 1 0 1 1

| | | | |

IL IE C V Z N

– – – 0

| | |

↔ ↔

| |

r d 1 0 0 0 r s

|

| | | | | |

r d 0 0 0 0 r s

|

| | | | | |

r d 0 1 0 0 r s

|

| | | | | |

|

and

|

and/c

|

and/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

and

(1) Standard

%rd,%rs ; rd ← rd & rs

%rd = %r0 to %r7

The content of the rs register and that of the rd register are logically AND’ed, and the result is

loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd

register are set to 0.

(2) Extension 1

ext and

imm13 %rd,%rs ; rd ← rs & imm13

The content of the rs register and the zero-extended 13-bit immediate imm13 are logically

AND’ed, and the result is loaded into the rd register. The operation is performed in 16-bit size,

and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(3) Extension 2

ext ext and

The content of the rs register and the 16-bit immediate

imm13 ; imm13(2:0) = imm16(15:13) imm13 ; = imm16(12:0) %rd,%rs ; rd ← rs & imm16

imm16 are logically AND’ed, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0. The content of the rs register is not altered.

(4) Conditional execution The /c or /nc suffix on the opcode specifies conditional execution.

In this case, the

and/c Executed as and when the C flag is 1 or executed as nop when the flag is 0 and/nc Executed as and when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) and %r0,%r0 ; r0 = r0 & r0

ext 0x1

ext 0x1fff and %r1,%r2 ; r1 = r2 & 0x3fff

7-10

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

and %rd, sign7

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(15:0) Extension 1) rd(15:0)

16-bit logical AND

← rd(15:0) & sign7(sign extended), rd(23:16) ← 0 ← rd(15:0) & sign16, rd(23:16) ← 0

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

1 0 1 0 0 0

| | | | | | | | | | | | |

– – – 0

| | |

↔ ↔

| |

r d sign7

|

Mode

Src: Immediate data (signed)

Dst: Register direct

CLK

One cycle

Description

and

(1) Standard

%rd,sign7 ; rd ← rd & sign7

%rd = %r0 to %r7

The content of the rd register and the sign-extended 7-bit immediate

ed, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

(2) Extension 1

ext imm13 ; imm13(8:0) = sign16(15:7) and

The content of the rd register and the 16-bit immediate

%rd,sign7 ; rd ← rd & sign16, sign7 = sign16(6:0)

sign16 are logically AND’ed, and the result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of the rd register are set to 0.

sign7 are logically AND’

(3) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(2)

(1) and %r0,0x3e ; r0 = r0 & 0xfffe

ext 0x7ff

and %r1,0x3f ; r1 = r1 & 0x1fff

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-11

7 DETAILS OF INSTRUCTIONS

brk

Function

Standard) A[DBRAM ]

Debugging interrupt

← {psr, pc + 2}, A[DBRAM + 0x4] ← r0, pc ← 0xfffc00 Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0

| | | | | | | | | | | | |

– 0 – – – –

| | |

| |

|

Mode

–

CLK

Four cycles

Description

The

Calls a debugging handler routine.

brk instruction stores the address (PC + 2) that follows this instruction, the contents of the PSR, and the contents of the R0 register into the work area for debugging (DBRAM), then sets the mini-monitor start address (0xfffc00) to the PC. Thus the program branches to the debug-handler routine. Furthermore the processor enters the debug mode.

The

retd instruction must be used for return from the debug-handler routine.

This instruction is provided for debug firmware. Do not use it in the user program.

Example

brk ; Executes the debug-handler routine

7-12

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

call %rb call.d %rb

7 DETAILS OF INSTRUCTIONS

Function

Standard) sp

PC relative subroutine call

← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + rb Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 1 0 0 0 0 0 r b

| | | | |

0 0 0 0 0 0 0 1 1 0 0 0 0 r b

| | | | |

– – – – – –

| | |

| |

|

| | | | | |

|

| | | | | |

|

call

|

call.d

|

Mode

Register direct %rb = %r0 to %r7

CLK

call Four cycles

call.d Three cycles

Description

(1) Standard

call %rb

Stores the address of the following instruction into the stack, then adds the contents of the

register to the PC (PC + 2) for calling the subroutine that starts from the address set to the PC. The LSB of the rb register is invalid and is always handled as 0. When the ret instruction is executed in the subroutine, the program flow returns to the instruction following the call instruction.

(2) Delayed branch (d bit (bit 7) = 1)

call.d %rb

rb

When cal l.d %rb is specified, the d bit (bit 7) in the instruction code is set and the

following instruction becomes a delayed slot instruction.

The delayed slot instruction is executed before branching to the subroutine. Therefore the

address (PC + 4) of the instruction that follows the delayed slot instruction is stored into the stack as the return address.

When the

call.d instruction is executed, interrupts cannot occur because traps are masked

between the call.d and delayed slot instructions.

Example

Caution

call %r0 ; Calls the subroutine that starts from pc + 2 + r0.

When the call.d i nstru ction (delayed branch) is used, be careful to ensure that the next

instruction is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-13

7 DETAILS OF INSTRUCTIONS

call sign10 call.d sign10

Function

Standard) sp Extension 1) sp

PC relative subroutine call

← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + sign10 × 2 ← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + sign24

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 1 1 0 sign10

| | | | | | | | | | | | |

0 0 0 1 1 1 sign10

| | | | | | | | | | | | |

– – – – – –

| | |

| |

|

call

|

call.d

|

Mode

Signed PC relative

CLK

call Four cycles

call.d Three cycles

Description

call ;

(1) Standard

sign10 ; = "call sign11"

sign10 = sign11(10:1), sign11(0) = 0

Stores the address of the following instruction into the stack, then doubles the signed 10-bit

immediate sign10 and adds it to the PC (PC + 2) for calling the subroutine that starts from the address. The

sign10 specifies a word address in 16-bit units. When the ret instruction is executed in the subroutine, the program flow returns to the instruction following the call instruction.

The

sign10 (×2) allows branches within the range of PC - 1,022 to PC + 1,024.

(2) Extension 1

ext call

imm13 ; = sign24(23:11) sign10 ;

= "call sign24"

; sign10 = sign24(10:1), sign24(0) = 0

The ext instruction extends the displacement into 24 bits using its 13-bit immediate imm13.

The 24-bit displacement is added to the PC.

The

sign24 allows branches within the range of PC - 8,388,606 to PC + 8,388,608.

(3) Delayed branch (d bit (bit 10) = 1)

call.d sign10

When call.d sign10 is specified, the d bit (bit 10) in the instruction code is set and

the following instruction becomes a delayed slot instruction. The delayed slot instruction is executed before branching to the subroutine. Therefore the address (PC + 4) of the instruction that follows the delayed slot instruction is stored into the stack as the return address.

When the

call.d instruction is executed, interrupts cannot occur because traps are masked

between the call.d and delayed slot instructions.

Example

ext 0x1fff

call 0x0 ; Calls the subroutine that starts from the ; address specified by pc + 2 - 0x400.

Caution

When the call.d i nstru ction (delayed branch) is used, be careful to ensure that the next

instruction is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

7-14

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

calla %rb calla.d %rb

7 DETAILS OF INSTRUCTIONS

Function

Standard) sp

PC absolute subroutine call

← sp - 4, A[sp] ← pc + 2, pc ← rb Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 1 0 0 0 0 1 r b

| | | | |

0 0 0 0 0 0 0 1 1 0 0 0 1 r b

| | | | |

– – – – – –

| | |

| |

|

| | | | | |

|

| | | | | |

|

calla

calla.d

|

Mode

PC absolute

CLK

calla Four cycles

calla.d Three cycles

Description

Stores the address of the following instruction into the stack, then sets the contents of the

(1) Standard

calla %rb

rb

register to the PC for calling the subroutine that starts from the address set to the PC. The LSB

rb register is invalid and is always handled as 0. When the ret instruction is executed in

of the the subroutine, the program flow returns to the instruction following the

calla instruction.

(2) Delayed branch (d bit (bit 7) = 1)

When

calla.d %rb

calla.d is specified, the d bit (bit 7) in the instruction code is set and the following

instruction becomes a delayed slot instruction.

The delayed slot instruction is executed before branching to the subroutine. Therefore the

address (PC + 4) of the instruction that follows the delayed slot instruction is stored into the stack as the return address.

When the

calla.d instruction is executed, interrupts cannot occur because traps are masked

between the calla.d and delayed slot instructions.

Example

calla %r0 ; Calls the subroutine that starts from the

; address stored in the r0 register.

Caution

When the calla.d instruction (delayed branch) is used, be careful to ensure that the next

instruction is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

7-15

7 DETAILS OF INSTRUCTIONS

calla imm7 calla.d imm7

Function

Standard) sp Extension 1) sp Extension 2) sp

Code

Flag

PC absolute subroutine call

← sp - 4, A[sp] ← pc + 2, pc ← imm7 ← sp - 4, A[sp] ← pc + 2, pc ← imm20 ← sp - 4, A[sp] ← pc + 2, pc ← imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 1 0 1 0

| | | | | | | | | | | | |

0 0 0 0 0 1 0 1 1

| | | | | | | | | | | | |

IL IE C V Z N

– – – – – –

| | |

| |

imm7

|

calla

|

calla.d

|

Mode

PC absolute

CLK

calla Four cycles

calla.d Three cycles

Description

calla

(1) Standard

imm7

Stores the address of the following instruction into the stack, then sets the 7-bit immediate

imm7 to the PC for calling the subroutine that starts from the address set to the PC. The LSB

imm7 is invalid and is always handled as 0. When the ret instruction is executed in the

of the subroutine, the program flow returns to the instruction following the

calla instruction.

(2) Extension 1

ext call

imm13 ; = imm20(19:7) imm7 ;

= "call imm20",

imm7 = imm20(6:0)

The ext instruction extends the destination address into 20 bits using its 13-bit immediate

imm13. The 20-bit destination address is set to the PC.

(3) Extension 2

ext ext call

imm13 ; imm13(3:0) = imm24(23:20) imm13 ; = imm24(19:7) imm7 ;

= "call imm24"

, imm7 = imm24(6:0)

The 24-bit destination address is set to the PC.

(4) Delayed branch (d bit (bit 7) = 1)

When

calla.d imm7

calla.d is specified, the d bit (bit 7) in the instruction code is set and the following

instruction becomes a delayed slot instruction. The delayed slot instruction is executed before branching to the subroutine. Therefore the address (PC + 4) of the instruction that follows the delayed slot instruction is stored into the stack as the return address.

When the

calla.d instruction is executed, interrupts cannot occur because traps are masked

between the calla.d and delayed slot instructions.

Example

ext 0x1fff

calla 0x0 ; Calls the subroutine that starts from ; address 0xfff80.

Caution

When the calla.d instruction (delayed branch) is used, be careful to ensure that the next

instruction is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

7-16

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S1C17 FAMILY S1C17 CORE MANUAL

cmc %rd, %rs cmc/c %rd, %rs cmc/nc %rd, %rs

7 DETAILS OF INSTRUCTIONS

Function

16-bit comparison with carry

Standard) rd(15:0) - rs(15:0) - C Extension 1) rs(15:0) - Extension 2) rs(15:0) -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 1 1 1

| | | | |

0 0 1 1 1 1

| | | | |

0 0 1 1 1 1

| | | | |

– –

– – –

↔ ↔ ↔ ↔

| | |

| |

↔ ↔ ↔

| |

imm13(zero extended) - C imm16 - C

r d 1 0 0 1 r s

|

| | | | | |

r d 0 0 0 1 r s

|

| | | | | |

r d 0 1 0 1 r s

|

| | | | | |

cmc

cmc/c, cmc/nc

|

cmc

|

cmc/c

|

cmc/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

cmc

(1) Standard

%rd,%rs ; rd - rs - C

%rd = %r0 to %r7

Subtracts the contents of the rs register and C (carry) flag from the contents of the rd register,

and sets or resets the flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(2) Extension 1

ext cmc

Subtracts the contents of the 13-bit immediate

imm13 %rd,%rs ; rs - imm13 - C

imm13 and C (carry) flag from the contents of

the rs register, and sets or resets the flags (C, V, Z and N) according to the results. The imm13 is zero-extended into 16 bits prior to the operation. The operation is performed in 16-bit size. It does not change the contents of the rd and rs registers.

(3) Extension 2

ext ext cmc

Subtracts the contents of the 16-bit immediate

imm13 ; imm13(2:0) = imm16(15:13) imm13 ; = imm16(12:0) %rd,%rs ; rs - imm16 - C

imm16 and C (carry) flag from the contents of the rs register, and sets or resets the flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd and rs registers.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. cmc/c Executed as cmc when the C flag is 1 or executed as nop when the flag is 0 cmc/nc Executed as cmc when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmc %r0,%r1 ; Changes the flags according to the results of

; r0 - r1 - C.

(2)

ext 0x1fff

cmc %r1,%r2 ; Changes the flags according to the results of ; r2 - 0x1fff - C.

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7 DETAILS OF INSTRUCTIONS

cmc %rd, sign7

Function

Standard) rd(15:0) Extension 1) rd(15:0) -

16-bit comparison with carry

sign7(sign extended) - C sign16 - C

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

1 0 0 1 0 1

| | | | | | | | | | | | |

– –

↔ ↔ ↔ ↔

| | |

| |

r d sign7

|

Mode

Src: Immediate data (signed)

Dst: Register direct

CLK

One cycle

Description

cmc

(1) Standard

%rd,sign7 ; rd - sign7 - C

Subtracts the contents of the signed 7-bit immediate

of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. The

%rd = %r0 to %r7

sign7 and C (carry) flag from the contents

sign7

is sign-extended into 16 bits prior to the operation. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(2) Extension 1

ext cmc

imm13 ; imm13(8:0) = sign16(15:7) %rd,sign7 ; rd - sign16 - C, sign7 = sign16(6:0)

Subtracts the contents of the signed 16-bit immediate sign16 and C (carry) flag from the

contents of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(3) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmc %r0,0x7f ; Changes the flags according to the results of

; r0 - 0x7f - C.

(2)

ext 0x1ff cmc %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffff - C.

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S1C17 FAMILY S1C17 CORE MANUAL

cmp %rd, %rs cmp/c %rd, %rs cmp/nc %rd, %rs

7 DETAILS OF INSTRUCTIONS

Function

16-bit comparison

Standard) rd(15:0) - rs(15:0) Extension 1) rs(15:0) - Extension 2) rs(15:0) -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 1 1 1

| | | | |

0 0 1 1 1 1

| | | | |

0 0 1 1 1 1

| | | | |

– –

– – –

↔ ↔ ↔ ↔

| | |

| |

↔ ↔ ↔

| |

imm13(zero extended) imm16

r d 1 0 0 0 r s

|

| | | | | |

r d 0 0 0 0 r s

|

| | | | | |

r d 0 1 0 0 r s

|

| | | | | |

cmp

cmp/c, cmp/nc

|

cmp

|

cmp/c

|

cmp/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

cmp

(1) Standard

%rd,%rs ; rd - rs

%rd = %r0 to %r7

Subtracts the contents of the rs register from the contents of the rd register, and sets or resets the

flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(2) Extension 1

ext cmp

Subtracts the 13-bit immediate

imm13 %rd,%rs ; rs - imm13

imm13 from the contents of the rs register, and sets or resets the

flags (C, V, Z and N) according to the results. The

imm13 is zero-extended into 16 bits prior to

the operation. The operation is performed in 16-bit size. It does not change the contents of the

rd

and rs registers.

(3) Extension 2

ext ext cmp

Subtracts the 16-bit immediate

imm13 ; imm13(2:0) = imm16(15:13) imm13 ; = imm16(12:0) %rd,%rs ; rs - imm16

imm16 from the contents of the rs register, and sets or resets the flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd and rs registers.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. cmp/c Executed as cmp when the C flag is 1 or executed as nop when the flag is 0 cmp/nc Executed as cmp when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmp %r0,%r1 ; Changes the flags according to the results of

; r0 - r1.

(2)

ext 0x1

ext 0x1fff ; Changes the flags according to the results of cmp %r1,%r2 ; r2 - 0x3fff.

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

cmp %rd, sign7

Function

Standard) rd(15:0) Extension 1) rd(15:0) -

16-bit comparison

sign7(sign extended) sign16

Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

1 0 0 1 0 0

| | | | | | | | | | | | |

– –

↔ ↔ ↔ ↔

| | |

| |

r d sign7

|

Mode

Src: Immediate data (signed)

Dst: Register direct

CLK

One cycle

Description

cmp

(1) Standard

%rd,sign7 ; rd - sign7

%rd = %r0 to %r7

Subtracts the signed 7-bit immediate sign7 from the contents of the rd register, and sets or resets

the flags (C, V, Z and N) according to the results. The

sign7 is sign-extended into 16 bits prior to the operation. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(2) Extension 1

ext cmp

Subtracts the signed 16-bit immediate

imm13 ; imm13(8:0) = sign16(15:7) %rd,sign7 ; rd - sign16, sign7 = sign16(6:0)

sign16 from the contents of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. The operation is performed in 16-bit size. It does not change the contents of the rd register.

(3) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmp %r0,0x3f ; Changes the flags according to the results of

; r0 - 0x3f.

(2)

ext 0x1ff

cmp %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffff.

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S1C17 FAMILY S1C17 CORE MANUAL

cmp.a %rd, %rs cmp.a/c %rd, %rs cmp.a/nc %rd, %rs

7 DETAILS OF INSTRUCTIONS

Function

24-bit comparison

Standard) rd(23:0) - rs(23:0) Extension 1) rs(23:0) - Extension 2) rs(23:0) -

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 1 0 1

| | | | |

0 0 1 1 0 1

| | | | |

0 0 1 1 0 1

| | | | |

– –

– – – –

↔ – ↔ –

| | |

| | | |

imm13(zero extended) imm24

r d 1 0 0 0 r s

|

| | | | | |

r d 0 0 0 0 r s

|

| | | | | |

r d 0 1 0 0 r s

|

| | | | | |

cmp.a

↔ –

cmp.a/c, cmp.a/nc

|

cmp.a

cmp.a/c

cmp.a/nc

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

cmp.a

%rd = %r0 to %r7

%rd,%rs ; rd - rs

Subtracts the contents of the rs register from the contents of the rd register, and sets or resets the

flags (C, V, Z and N) according to the results. It does not change the contents of the rd register.

(2) Extension 1

ext cmp.a

Subtracts the 13-bit immediate

flags (C, V, Z and N) according to the results. The

imm13 %rd,%rs ; rs - imm13

imm13 from the contents of the rs register, and sets or resets the

imm13 is zero-extended into 24 bits prior to

the operation. It does not change the contents of the rd and rs registers.

(3) Extension 2

ext ext cmp.a

Subtracts the 24-bit immediate

imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) %rd,%rs ; rs - imm24

imm24 from the contents of the rs register, and sets or resets the flags (C, V, Z and N) according to the results. It does not change the contents of the rd and rs registers.

(4) Conditional execution The

In this case, the

/c or /nc suffix on the opcode specifies conditional execution. cmp.a/c Executed as cmp.a when the C flag is 1 or executed as nop when the flag is 0 cmp.a/nc Executed as cmp.a when the C flag is 0 or executed as nop when the flag is 1

ext instruction can be used to extend the operand.

(5) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmp.a %r0,%r1 ; Changes the flags according to the results of

; r0 - r1.

(2)

ext 0x1

ext 0x1fff cmp.a %r1,%r2 ; Changes the flags according to the results of ; r2 - 0x3fff.

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

cmp.a %rd, imm7

Function

Standard) rd(23:0) Extension 1) rd(23:0) - Extension 2) rd(23:0) -

Code

Flag

24-bit comparison

imm7(zero extended) imm20(zero extended) imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 1 0 0

| | | | | | | | | | | | |

IL IE C V Z N

– –

↔ – ↔ –

| | |

| |

r d imm7

Mode

Src: Immediate data (unsigned)

Dst: Register direct

CLK

One cycle

Description

(1) Standard

cmp.a

Subtracts the 7-bit immediate

%rd = %r0 to %r7

%rd,imm7 ; rd - imm7

imm7 from the contents of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. The the operation. It does not change the contents of the rd register.

(2) Extension 1

ext cmp.a

Subtracts the 20-bit immediate

imm13 ; = imm20(19:7) %rd,imm7 ; rd - imm20, imm7 = imm20(6:0)

imm20 from the contents of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. The the operation. It does not change the contents of the rd register.

|

imm7 is zero-extended into 24 bits prior to

imm20 is zero-extended into 24 bits prior to

(3) Extension 2

ext ext cmp.a

Subtracts the 24-bit immediate

imm13 ; imm13(3:0) = imm24(23:20) imm13 ; = imm24(19:7) %rd,imm7 ; rd - imm24, imm7 = imm24(6:0)

imm24 from the contents of the rd register, and sets or resets the flags (C, V, Z and N) according to the results. It does not change the contents of the rd register.

(4) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after

a branch instruction with the “d” bit. In this case, extension of the immediate by the ext instruction cannot be performed.

Example

(1) cmp.a %r0,0x7f ; Changes the flags according to the results of

; r0 - 0x7f.

(2)

ext 0xf

ext 0x1fff cmp.a %r1,0x7f ; Changes the flags according to the results of ; r1 - 0xffffff.

7-22

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

cv.ab %rd, %rs

rs

rd

X

23 8 7 0

23 8

8 bits

7 0

SSSSSSSSSSSSSSSSSS

Byte

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(23:8)

Data conversion from byte to 24 bits

← rs(7), rd(7:0) ← rs(7:0) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 0 1 0

| | | | |

– – – – – –

| | |

| |

r d 0 1 1 1 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

%rd = %r0 to %r7

The eight low-order bits of the rs register are transferred to the rd register after being sign-

extended to 24 bits.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

When the R1 register contains 0x80

cv.ab %r0,%r1 ; r0 = 0xffff80

S1C17 FAMILY S1C17 CORE MANUAL

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7-23

7 DETAILS OF INSTRUCTIONS

rs

rd

23 16 15 0

23 8 7 0

15

Unchanged

0

X 8 bits

8 bits

cv.al %rd, %rs

Function

Standard) rd(23:16)

Data conversion from 32 bits to 24 bits

← rs(7:0), rd(15:0) ← rd(15:0) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 0 1 0

| | | | |

– – – – – –

| | |

| |

r d 1 1 1 1 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

%rd = %r0 to %r7

The eight low-order bits of the rs register are transferred to the eight high-order bits of the rd

register.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

When the R1 register contains 0xff and the R0 register contains 0x0

cv.al %r0,%r1 ; r0 = 0xff0000

7-24

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S1C17 FAMILY S1C17 CORE MANUAL

cv.as %rd, %rs

rs

rd

23 16 15 0

S

SSSSSSSSS

X

23 16 15

Word

0

15

16 bits

0

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(23:16)

Data conversion from 16 bits to 24 bits

← rs(15), rd(15:0) ← rs(15:0) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 0 1 0

| | | | |

– – – – – –

| | |

| |

r d 1 0 1 1 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

%rd = %r0 to %r7

The 16 low-order bits of the rs register are transferred to the rd register after being sign-

extended to 24 bits.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

When the R1 register contains 0x8000

cv.as %r0,%r1 ; r0 = 0xff8000

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

rs

rd

23 8 0

23 16 15 0

7 0

X8 bits

8 bits00000000 00000000

cv.la %rd, %rs

Function

Standard) rd(23:8)

Data conversion from 24 bits to 32 bits

← 0, rd(7:0) ← rs(23:16) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 0 1 0

| | | | |

– – – – – –

| | |

| |

r d 0 1 1 0 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

%rd = %r0 to %r7

The eight high-order bits of the rs register are transferred to the eight low-order bits of the rd

register. The 16 high-order bits of the rd register are set to 0.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

When the R1 register contains 0x800000

cv.la %r0,%r1 ; r0 = 0x000080

7-26

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

cv.ls %rd, %rs

rs

rd

23 16 15 0

S

00000000 S S S S S S S S SSSSSSSS

X

23 16 15

Word

0

15 0

7 DETAILS OF INSTRUCTIONS

Function

Standard) rd(23:16)

Data conversion from 16 bits to 32 bits

← 0, rd(15:0) ← rs(15) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 1 0 1 0

| | | | |

– – – – – –

| | |

| |

r d 1 0 1 0 r s

|

| | | | | |

|

Mode

Src: Register direct %rs = %r0 to %r7

Dst: Register direct

CLK

One cycle

Description

(1) Standard

%rd = %r0 to %r7

Bit 15 (sign bit of 16-bit data) of the rs register is transferred to the 16 low-order bits of the rd

register. The eight high-order bits of the rd register are set to 0.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

When the R1 register contains 0x008000

cv.ls %r0,%r1 ; r0 = 0x00ffff

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

di

Function

Standard) psr(IE)

Disable interrupts

← 0 Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

| | | | | | | | | | | | |

– 0 – – – –

| | |

| |

|

Mode

–

CLK

One cycle

Description

(1) Standard Resets the IE bit in the PSR to disable external maskable interrupts. The reset interrupt, address misaligned interrupt, and NMI will be accepted even if the IE bit is

set to 0.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

di ; Disables external maskable interrupts.

7-28

EPSON

S1C17 FAMILY S1C17 CORE MANUAL

ei

7 DETAILS OF INSTRUCTIONS

Function

Standard) psr(IE)

Enable interrupts

← 1 Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

| | | | | | | | | | | | |

– 1 – – – –

| | |

| |

|

Mode

–

CLK

One cycle

Description

(1) Standard

Sets the IE bit in the PSR to enable external maskable interrupts.

(2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a

branch instruction with the “d” bit.

Example

ei ; Enables external maskable interrupts.

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

ext imm13

Function

Immediate extension Standard) Extends the immediate data/operand of the following instruction Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 1 0

| | | | | | | | | | | | |

– – – – – –

| | |

| |

imm13

|

Mode

Immediate data (unsigned)

CLK

One cycle

Description

When extending an immediate data, the immediate data in the

Extends the immediate data or operand of the following instruction.

ext instruction will be placed on the high-order side and the immediate data in the target instruction to be extended is placed on the loworder side.

Up to two

first

ext imm3 instructions can be used sequentially. In this case, the immediate data in the

ext instruction is placed on the most upper part. When three or more ext instructions have

been described sequentially, the last two are effective and others are ignored.

See descriptions of each instruction for the extension contents and the usage.

Interrupts for the ext instruction (not including reset and debug break) are masked in the hardware,

and interrupt handling is determined when the target instruction to be extended is executed. In this

Example

case, the return address from interrupt handling is the beginning of the

ext 0x7ff

ext instruction.

ext 0x1fff add.a %r1,%r2 ; r1 = r2 + 0xffffff

Caution

When a load instruction that transfers data between memory and a register follows the ext

instruction, an address misaligned interrupt may occur before executing the load instruction (if the address that is specified with the immediate data in the

ext instruction as the displacement is not a boundary address according to the transfer data size). When an address misaligned interrupt occurs, the trap handling saves the address of the load instruction into the stack as the return address. If the trap handler routine is returned by simply executing the reti instruction, the previous ext instruction is invalidated. Therefore, it is necessary to modify the return address in that case.

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S1C17 FAMILY S1C17 CORE MANUAL

halt

7 DETAILS OF INSTRUCTIONS

Function

HALT Standard) Sets the processor to HALT mode Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

| | | | | | | | | | | | |

– – – – – –

| | |

| |

|

Mode

–

CLK

Six cycles

Description

Program execution is halted at the same time that the S1C17 Core executes the

Sets the processor to HALT mode for power saving.

halt instruction,

and the processor enters HALT mode.

HALT mode commonly turns off only the S1C17 Core operation, note, however that modules to be

turned off depend on the implementation of the clock control circuit outside the core.

Initial reset is one cause that can bring the processor out of HALT mode. Other causes depend on

the implementation of the clock control circuit outside the S1C17 Core.

Initial reset, maskable external interrupts, NMI, and debug interrupts are commonly used for

canceling HALT mode.

The interrupt enable/disable status set in the processor does not affect the cancellation of HALT

mode even if an interrupt signal is used as the cancellation. In other words, interrupt signals are able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller (depending on the implementation) are set to disable interrupts.

When the processor is taken out of HALT mode using an interrupt that has been enabled (by the

interrupt controller and IE flag), the corresponding interrupt handler routine is executed. Therefore, when the interrupt handler routine is terminated by the the instruction next to

halt.

reti instruction, the processor returns to

When the interrupt has been disabled, the processor restarts the program from the instruction next

to halt after the processor is taken out of HALT mode.

Refer to the technical manual of each model for details of HALT mode.

Example

S1C17 FAMILY S1C17 CORE MANUAL

halt ; Sets the processor in HALT mode.

EPSON

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7 DETAILS OF INSTRUCTIONS

int imm5

Function

Standard) sp

Software interrupt

← sp - 4, A[sp] ← {psr, pc + 2}, pc ← vector (vector No. = imm5) Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 1 1 1 0 1 0 0 0 imm5 0 1

| | | | | | | | | | | | |

– 0 – – – –

| | |

| |

|

Mode

Immediate data (unsigned)

CLK

Three cycles

Description

The

Generates the interrupt of the vector number specified with the imm5.

int instruction saves the address of the next instruction and the contents of the PSR into the stack, then reads the specified interrupt vector from the trap table and sets it to the PC. By this processing, the program flow branches to the specified interrupt handler routine.

imm5 Vector No. Vector address Cause of interrupt 0x00 0 TTBR + 0x00 Reset interrupt 0x01 1 TTBR + 0x04 Address misaligned interrupt 0x02 2 TTBR + 0x08 NMI 0x03 3 TTBR + 0x0c External maskable interrupt 0x03 : : : : 0x1f 31 TTBR + 0x7c External maskable interrupt 0x1f

The TTBR is the trap table base address. The

Example

int 2 ; Generates an NMI.

reti instruction should be used for return from the handler routine.

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S1C17 FAMILY S1C17 CORE MANUAL

intl imm5, imm3

7 DETAILS OF INSTRUCTIONS

Function

Standard) sp psr(IL)

Software interrupt with interrupt level setting

← sp - 4, A[sp] ← {psr, pc + 2}, pc ← vector (vector No. = imm5),

← imm3

Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 1 1 1 0 1

| | | | | | | | | | | | |

↔ 0 – – – –

| | |

| |

imm3 imm5 1 1

|

Mode

Immediate data (unsigned)

CLK

Three cycles

Description

The

Generates the interrupt of the vector number specified with the imm5.

intl instruction saves the address of the next instruction and the contents of the PSR into the stack, then reads the specified interrupt vector from the trap table and sets it to the PC. By this processing, the program flow branches to the specified interrupt handler routine. In addition to this, the imm3 value is set to the IL bits in the PSR (interrupt level) to disable interrupts of which the interrupt level is lower than the

imm3 while the interrupt handler routine is executed.

The altered IL bits are restored to the value before the intl instruction is executed when the

reti instruction.

Example

interrupt handler routine is terminated by the

intl 0x3,0x2 ; Generates an external maskable interrupt 0x3

; and set the IL bits to 0x2.

S1C17 FAMILY S1C17 CORE MANUAL

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7 DETAILS OF INSTRUCTIONS

jpa %rb jpa.d %rb

Function

Standard) pc

Unconditional PC absolute jump

← rb Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 1 0 1 0 0 1 r b

| | | | |

0 0 0 0 0 0 0 1 1 1 0 0 1 r b

| | | | |

– – – – – –

| | |

| |

|

| | | | | |

|

| | | | | |

Mode

PC absolute

CLK

jpa Three cycles

jpa.d Two cycles

Description

The content of the

(1) Standard

jpa %rb

rb register is loaded to the PC, and the program branches to that address. The

LSB of the rb register is ignored and is always handled as 0.

(2) Delayed branch (d bit (bit 7) = 1)

For the

jpa.d %rb

jpa.d instruction, the next instruction becomes a delayed slot instruction. A delayed

slot instruction is executed before the program branches. Interrupts are masked in intervals between the jpa.d instruction and the next instruction, so no interrupts occur.

Example

Caution

jpa %r0 ; Jumps to the address specified by the r0 register.

When the jpa.d instruction (delayed branch) is used, be careful to ensure that the next instruction

is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

|

jpa

|

jpa.d

|

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S1C17 FAMILY S1C17 CORE MANUAL

jpa imm7 jpa.d imm7

7 DETAILS OF INSTRUCTIONS

Function

Standard) pc Extension 1) pc Extension 2) pc

Code

Flag

Unconditional PC absolute jump

← imm7 ← imm20 ← imm24

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 1 1 0

| | | | | | | | | | | | |

0 0 0 0 0 0 1 1 1

| | | | | | | | | | | | |

IL IE C V Z N

– – – – – –

| | |

| |

imm7

|

jpa

|

jpa.d

|

Mode

PC absolute

CLK

jpa Three cycles

jpa.d Two cycles

Description

jpa

The 7-bit immediate

(1) Standard

imm7

imm7 is loaded to the PC, and the program branches to that address. The

LSB of the imm7 is ignored and is always handled as 0.

(2) Extension 1

ext jpa

imm13 ; = imm20(19:7) imm7 ;

= "jpa imm20",

imm7 = imm20(6:0)

The ext instruction extends the destination address into 20 bits using its 13-bit immediate

imm13. The 20-bit destination address is set to the PC.

(3) Extension 2

ext ext jpa

imm13 ; imm13(3:0) = imm24(23:20) imm13 ; = imm24(19:7) imm7 ;

= "jpa imm24"

, imm7 = imm24(6:0)

The 24-bit destination address is set to the PC.

(4) Delayed branch (d bit (bit 7) = 1)

For the

jpa.d imm7

jpa.d instruction, the next instruction becomes a delayed slot instruction. A delayed

slot instruction is executed before the program branches. Interrupts are masked in intervals between the jpa.d instruction and the next instruction, so no interrupts occur.

Example

ext 0x30

jpa 0x00 ; Jumps to the address 0x18000.

Caution

When the jpa.d instruction (delayed branch) is used, be careful to ensure that the next instruction

is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

S1C17 FAMILY S1C17 CORE MANUAL

EPSON

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7 DETAILS OF INSTRUCTIONS

jpr %rb jpr.d

Function

Standard) pc

%rb

Unconditional PC relative jump

← pc + 2 + rb Extension 1) Unusable Extension 2) Unusable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Code

IL IE C V Z N

Flag

0 0 0 0 0 0 0 1 0 1 0 0 0 r b

| | | | |

0 0 0 0 0 0 0 1 1 1 0 0 0 r b

| | | | |

– – – – – –

| | |

| |

|

| | | | | |

|

| | | | | |

Mode

Signed PC relative

CLK

jpr Three cycles

jpr.d Two cycles

Description

The content of the

(1) Standard

jpr %rb

rb register is added to the PC (PC + 2), and the program branches to that

address.

(2) Delayed branch (d bit (bit 7) = 1)

For the

jpr.d %rb

jpr.d instruction, the next instruction becomes a delayed slot instruction. A delayed

slot instruction is executed before the program branches. Interrupts are masked in intervals between the jpr.d instruction and the next instruction, so no interrupts occur.

Example

Caution

jpr %r0 ; pc ← pc + 2 + r0

When the jpr.d instruction (delayed branch) is used, be careful to ensure that the next instruction

is limited to those that can be used as a delayed slot instruction. If any other instruction is executed, the program may operate indeterminately. For the usable instructions, refer to the instruction list in the Appendix.

|

jpr

|

jpr.d

|

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S1C17 FAMILY S1C17 CORE MANUAL

Seiko Epson S1C17 Series Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 SUMMARY

1.1 Features

2 REGISTERS

2.2 Program Counter (PC)

2.3 Processor Status Register (PSR)

2.4 Stack Pointer (SP)

2.4.1 About the Stack Area

2.4.2 SP Operation at Subroutine Call/Return

2.4.3 SP Operation when an Interrupt Occurs

2.4.4 Saving/Restoring Register Data Using a Load Instruction

2.5 Register Notation and Register Numbers

2.5.1 General-Purpose Registers

2.5.2 Special Registers

3 DATA FORMATS

3.1 Data Formats Handled in Operations Between Registers

3.1.1 Unsigned 8-Bit Transfer (Register → Register)

3.1.2 Signed 8-Bit Transfer (Register → Register)

3.1.3 16-Bit Transfer (Register → Register)

3.1.4 24-Bit Transfer (Register → Register)

3.2 Data Formats Handled in Operations Between Memory and a Register

3.2.1 Unsigned 8-Bit Transfer (Memory → Register)

3.2.2 Signed 8-Bit Transfer (Memory → Register)

3.2.3 8-Bit Transfer (Register → Memory)

3.2.4 16-Bit Transfer (Memory → Register)

3.2.5 16-Bit Transfer (Register → Memory)

3.2.6 32-Bit Transfer (Memory → Register)

3.2.7 32-Bit Transfer (Register → Memory)

4 ADDRESS MAP

4.1 Address Space

4.2 Processor Information in the Core I/O Area

4.2.1 Trap Table Base Register (TTBR, 0xffff80)

4.2.2 Processor ID Register (IDIR, 0xffff84)

4.2.3 Debug RAM Base Register (DBRAM, 0xffff90)

5 INSTRUCTION SET

5.1 List of Instructions

5.2 Addressing Modes (without ext extension)

5.2.1 Immediate Addressing

5.2.2 Register Direct Addressing

5.2.3 Register Indirect Addressing

5.2.4 Register Indirect Addressing with Post-increment/decrement or Pre-decrement

5.2.5 Register Indirect Addressing with Displacement

5.2.6 Signed PC Relative Addressing

5.2.7 PC Absolute Addressing

5.3 Addressing Modes with ext

5.3.1 Extension of Immediate Addressing

5.3.2 Extension of Register Direct Addressing

5.3.3 Extension of Register Indirect Addressing

5.3.4 Extension of Register Indirect Addressing with Displacement

5.3.5 Extension of Signed PC Relative Addressing

5.3.6 Extension of PC Absolute Addressing

5.4 Data Transfer Instructions

5.5 Logical Operation Instructions

5.6 Arithmetic Operation Instructions

5.7 Shift and Swap Instructions

5.8 Branch and Delayed Branch Instructions

5.8.1 Types of Branch Instructions

5.8.2 Delayed Branch Instructions

5.9 System Control Instructions

5.10 Conversion Instructions

5.11 Coprocessor Instructions

6 Functions

6.1 Transition of the Processor Status

6.1.1 Reset State

6.1.2 Program Execution State

6.1.3 Interrupt Handling

6.1.4 Debug Interrupt

6.1.5 HALT and SLEEP Modes

6.2 Program Execution

6.2.1 Instruction Fetch and Execution

6.2.2 Execution Cycles and Flags

6.3 Interrupts

6.3.1 Priority of Interrupts

6.3.2 Vector Table

6.3.3 Interrupt Handling

6.3.4 Reset

6.3.5 Address Misaligned Interrupt