Segger J-Link Series, J-Trace Series, J-Link ARM, J-Trace for Cortex-M, J-Trace ARM User Manual

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J-Link / J-Trace

User Guide

Software Version V4.51a

Manual Rev. 0

Date: June 6, 2012

Document: UM08001

A product of SEGGER Microcontroller GmbH & Co. KG

www.segger.com

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Disclaimer

Specifications written in this document are believed to be accurate, but are not guaranteed to be entirely free of error. The information in this manual is subject to change for functional or performance improvements without notice. Please make sure your manual is the latest edition. While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no responsibility for any errors or omissions. The manufacturer makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you. The manufacturer specifically disclaims any implied warranty of merchantability or fitness for a particular purpose.

You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of the manufacturer. The software described in this document is furnished under a license and may only be used or copied in accordance with the terms of such a license.

Trademarks

Names mentioned in this manual may be trademarks of their respective companies.

Brand and product names are trademarks or registered trademarks of their respective holders.

Contact address

SEGGER Microcontroller GmbH & Co. KG

In den Weiden 11 D-40721 Hilden

Germany

Tel.+49 2103-2878-0 Fax.+49 2103-2878-28 Email: support@segger.com Internet: http://www.segger.com

Revisions

This manual describes the J-Link and J-Trace device.

For further information on topics or routines not yet specified, please contact us.

Revision Date By Explanation

Chapter "Device specifics" * Section "ST", subsection "ETM init"

V4.51a 120606 EL

V4.47a Rev. 0 120419 AG

V4.46 Rev. 0 120416 EL Chapter "Support" updated.

V4.42 Rev. 0 120214 EL

for some STM32 devices added.. * Section "Texas Instruments" updated. Chapter "Target interfaces and adapters" * Section "Pinout for SWD" updated.

Chapter "Device specifics" * Section "Texas Instruments" updated.

Chapter "Working with J-Link" * Section "J-Link script files" updated.

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Revision Date By Explanation

Chapter "Flash download" added. Chapter "Flash breakpoints" added. Chapter "Target interfaces and adapters"

V4.36 Rev. 1 110927 EL

* Section "20-pin JTAG/SWD connector" updated. Chapter "RDI" added. Chapter "Setup" updated. Chapter "Device specifics" updated. Several corrections / updates.

V4.36 Rev. 0 110909 AG

V4.26 Rev. 1 110513 KN

Chapter "Working with J-Link" * Section "J-Link script files" updated.

Chapter "Introduction" * Section "J-Link / J-Trace models" corrected.

V4.26 Rev. 0 110427 KN Several corrections.

Chapter "Introduction"

V4.24 Rev. 1 110228 AG

* Section "J-Link / J-Trace models" corrected. Chapter "Device specifics" * Section "ST Microelectronics" updated.

Chapter "Device specifics" * Section "Samsung" added.

V4.24 Rev. 0 110216 AG

Chapter "Working with J-Link" * Section "Reset strategies" updated. Chapter "Target interfaces and adapters" * Section "9-pin JTAG/SWD connector" added.

Chapter "J-Link and J-Trace related software" * Section "J-Link software and documentation

V4.23d 110202 AG

package in detail" updated. Chapter "Introduction" * Section "Built-in intelligence for supported CPU-cores" added.

Chapter "Working with J-Link" * Section "Reset strategies" updated. Chapter "Device specifics"

V4.21g 101130 AG

* Section "Freescale" updated. Chapter "Flash download and flash breakpoints * Section "Supported devices" updated * Section "Setup for different debuggers (CFI flash)" updated.

V4.21 101025 AG

V4.20j 101019 AG

V4.20b 100923 AG

Chapter "Device specifics" * Section "Freescale" updated.

Chapter "Working with J-Link" * Section "Reset strategies" updated.

Chapter "Working with J-Link" * Section "J-Link script files" updated. * Section "Command strings" upadted.

90 100818 AG

Chapter "Target interfaces and adapters" * Section "19-pin JTAG/SWD and Trace connector" corrected. Chapter "Setup" * Section "J-Link configurator added."

89 100630 AG Several corrections.

88 100622 AG

Chapter "J-Link and J-Trace related software" * Section "SWO Analyzer" added.

87 100617 AG Several corrections.

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Revision Date By Explanation

Chapter "Introduction"

86 100504 AG

* Section "J-Link / J-Trace models" updated. Chapter "Target interfaces and adapters" * Section "Adapters" updated.

85 100428 AG

Chapter "Introduction" * Section "J-Link / J-Trace models" updated.

Chapter "Working with J-Link and J-Trace"

84 100324 KN

* Several corrections Chapter Flash download & flash breakpoints * Section "Supported devices" updated

83 100223 KN

82 100215 AG

Chapter "Introduction" * Section "J-Link / J-Trace models" updated.

Chapter "Working with J-Link" * Section "J-Link script files" added.

Chapter "Device Specifics"

81 100202 KN

* Section "Luminary Micro" updated. Chapter "Flash download and flash breakpoints" * Section "Supported devices" updated.

80 100104 KN

Chapter "Flash download and flash breakpoints * Section "Supported devices" updated

Chapter "Working with J-Link and J-Trace"

79 091201 AG

* Section "Reset strategies" updated. Chapter "Licensing" * Section "J-Link OEM versions" updated.

78 091023 AG

77 090910 AG

Chapter "Licensing" * Section "J-Link OEM versions" updated.

Chapter "Introduction" * Section "J-Link / J-Trace models" updated.

Chapter "Introduction" * Section" Specifications" updated * Section "Hardware versions" updated

76 090828 KN

* Section "Common features of the J-Link product family" updated Chapter "Target interfaces and adapters" * Section "5 Volt adapter" updated

Chapter "Introduction"

75 090729 AG

* Section "J-Link / J-Trace models" updated. Chapter "Working with J-Link and J-Trace" * Section "SWD interface" updated.

Chapter "Introduction" * Section "Supported IDEs" added * Section "Supported CPU cores" updated

74 090722 KN

* Section "Model comparison chart" renamed to "Model comparison" * Section "J-Link bundle comparison chart" removed

Chapter "Introduction" * Section "J-Link and J-Trace models" added * Sections "Model comparison chart" & "J-Link bundle comparison chart"added Chapter "J-Link and J-Trace models" removed

73 090701 KN

Chapter "Hardware" renamed to "Target interfaces & adapters" * Section "JTAG Isolator" added Chapter "Target interfaces and adapters" * Section "Target board design" updated Several corrections

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Revision Date By Explanation

Chapter "Working with J-Link" * Section "J-Link control panel" updated.

72 090618 AG

Chapter "Flash download and flash breakpoints" * Section "Supported devices" updated. Chapter "Device specifics" * Section "NXP" updated.

71 090616 AG

Chapter "Device specifics" * Section "NXP" updated.

Chapter "Introduction"

70 090605 AG

* Section "Common features of the J-Link product family" updated.

Chapter "Working with J-Link" * Section "Reset strategies" updated.

69 090515 AG

* Section "Indicators" updated. Chapter "Flash download and flash breakpoints" * Section "Supported devices" updated.

Chapter "J-Link and J-Trace related software"

68 090428 AG

* Section "J-Link STM32 Commander" added. Chapter "Working with J-Link" * Section "Reset strategies" updated.

67 090402 AG

Chapter "Working with J-Link" * Section "Reset strategies" updated.

Chapter "Background information" * Section "Embedded Trace Macrocell (ETM)"

66 090327 AG

updated. Chapter "J-Link and J-Trace related software" * Section "Dedicated flash programming utilities for J-Link" updated.

65 090320 AG Several changes in the manual structure.

64 090313 AG

Chapter "Working with J-Link" * Section "Indicators" added.

Chapter "Hardware"

63 090212 AG

* Several corrections. * Section "Hardware Versions" Version 8.0 added.

Chapter "Working with J-Link and J-Trace" * Section "Reset strategies" updated. Chapter J-Link and J-Trace related software

62 090211 AG

* Section "J-Link STR91x Commander (Command line tool)" updated. Chapter "Device specifics" * Section "ST Microelectronics" updated. Chapter "Hardware" updated.

61 090120 TQ

60 090114 AG

Chapter "Working with J-Link" * Section "Cortex-M3 specific reset strategies"

Chapter Hardware

59 090108 KN

* Section "Target board design for JTAG" updated. * Section "Target board design for SWD" added.

Chapter "Working with J-Link Pro"

58 090105 AG

* Section "Connecting J-Link Pro the first time" updated.

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Revision Date By Explanation

Chapter "Working with J-Link Pro" * Section "Introduction" updated.

57 081222 AG

* Section "Configuring J-Link Pro via web interface" updated. Chapter "Introduction" * Section "J-Link Pro overview" updated.

Chapter "Working with J-Link Pro"

56 081219 AG

* Section "FAQs" added. Chapter "Support and FAQs" * Section "Frequently Asked Questions" updated.

55 081218 AG Chapter "Hardware" updated.

54 081217 AG

Chapter "Working with J-Link and J-Trace" * Section "Command strings" updated.

53 081216 AG Chapter "Working with J-Link Pro" updated.

Chapter "Working with J-Link Pro" added.

52 081212 AG

Chapter "Licensing" * Section "Original SEGGER products" updated.

51 081202 KN Several corrections.

50 081030 AG

Chapter "Flash download and flash breakpoints" * Section "Supported devices" corrected.

49 081029 AG Several corrections.

Chapter "Working with J-Link and J-Trace"

48 080916 AG

* Section "Connecting multiple J-Links / J-Traces to your PC" updated.

47 080910 AG Chapter "Licensing" updated.

Chapter "Licensing" added.

46 080904 AG

Chapter "Hardware" Section "J-Link OEM versions" moved to chapter "Licensing"

Chapter "Hardware"

45 080902 AG

Section "JTAG+Trace connector" JTAG+Trace connector pinout corrected. Section "J-Link OEM versions" updated.

Chapter "J-Link control panel" moved to chapter

44 080827 AG

"Working with J-Link". Several corrections.

43 080826 AG

42 080820 AG

Chapter "Flash download and flash breakpoints" Section "Supported devices" updated.

Chapter "Flash download and flash breakpoints"

41 080811 AG

updated. Chapter "Flash download and flash breakpoints", section "Supported devices" updated.

Chapter "Flash download and flash breakpoints" updated.

40 080630 AG

Chapter "J-Link status window" renamed to "J-Link control panel" Various corrections.

Chapter "Flash download and flash breakpoints" Section "Licensing" updated.

39 080627 AG

Section "Using flash download and flash breakpoints with different debuggers" updated. Chapter "J-Link status window" added.

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Revision Date By Explanation

Chapter "Support and FAQs" Section "Frequently Asked Questions" updated

38 080618 AG

Chapter "Reset strategies" Section "Cortex-M3 specific reset strategies" updated.

Chapter "Reset strategies"

37 080617 AG

Section "Cortex-M3 specific reset strategies" updated.

Chapter "Hardware" Section "Differences between different versions"

36 080530 AG

updated. Chapter "Working with J-Link and J-Trace" Section "Cortex-M3 specific reset strategies" added.

Chapter "J-Link and J-Trace related software"

35 080215 AG

Section "J-Link software and documentation package in detail" updated.

Chapter "J-Link and J-Trace related software" Section "J-Link TCP/IP Server (Remote J-Link / J-Trace use)" updated. Chapter "Working with J-Link and J-Trace"

34 080212 AG

Section "Command strings" updated. Chapter "Flash download and flash breakpoints" Section "Introduction" updated. Section "Licensing" updated. Section "Using flash download and flash breakpoints with different debuggers" updated.

Chapter "Flash download and flash breakpoints" added

33 080207 AG

Chapter "Device specifics:" Section "ATMEL - AT91SAM7 - Recommended init sequence" added.

Chapter "Device specifics":

32 0080129 SK

Section "NXP - LPC - Fast GPIO bug" list of device enhanced.

31 0080103 SK

Chapter "Device specifics": Section "NXP - LPC - Fast GPIO bug" updated.

Chapter "Device specifics": Section "Analog Devices" updated. Section "ATMEL" updated. Section "Freescale" added. Section "Luminary Micro" added.

30 071211 AG

Section "NXP" updated. Section "OKI" added. Section "ST Microelectronics" updated. Section "Texas Instruments" updated. Chapter "Related software": Section "J-Link STR91x Commander" updated

29 070912 SK

Chapter "Hardware", section "Target board design" updated.

Chapter "Related software": Section "J-LinkSTR91x Commander" added.

28 070912 SK

Chapter "Device specifics": Section "ST Microelectronics" added. Section "Texas Instruments" added. Subsection "AT91SAM9" added.

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Revision Date By Explanation

28 070912 AG

27 070827 TQ

Chapter "Working with J-Link/J-Trace": Section "Command strings" updated.

Chapter "Introduction": Section "Features of J-Link" updated.

26 070710 SK

Chapter "Background Information": Section "Embedded Trace Macrocell" added. Section "Embedded Trace Buffer" added.

Chapter "Working with J-Link/J-Trace": Section "Reset strategies in detail"

- "Software, for Analog Devices ADuC7xxx MCUs" updated

25 070516 SK

- "Software, for ATMEL AT91SAM7 MCUs" added. Chapter "Device specifics" Section "Analog Devices" added. Section "ATMEL" added.

Chapter "Setup":

24 070323 SK

"Uninstalling the J-Link driver" updated. "Supported ARM cores" updated.

23 070320 SK

22 070316 SK

Chapter "Hardware": "Using the JTAG connector with SWD" updated.

Chapter "Hardware": "Using the JTAG connector with SWD" added.

Chapter "Hardware":

21 070312 SK

"Differences between different versions" supplemented.

20 070307 SK

Chapter "J-Link / J-Trace related software": "J-Link GDB Server" licensing updated.

Chapter "J-Link / J-Trace related software" updated

19 070226 SK

and reorganized. Chapter "Hardware" "List of OEM products" updated

18 070221 SK

Chapter "Device specifics" added Subchapter "Command strings" added

Chapter "Hardware": "Version 5.3": Current limits added "Version 5.4" added Chapter "Setup":

17 070131 SK

"Installating the J-Link USB driver" removed. "Installing the J-Link software and documentation pack" added. Subchapter "List of OEM products" updated. "OS support" updated

16 061222 SK

Chapter "Preface": "Company description" added. J-Link picture changed.

Subchapter 1.5.1: Added target supply voltage and

15 060914 OO

target supply current to specifications. Subchapter 5.2.1: Pictures of ways to connect JTrac e.

14 060818 TQ

13 060711 OO

12 060628 OO

Subchapter 4.7 "Using DCC for memory reads" added.

Subchapter 5.2.2: Corrected JTAG+Trace connector pinout table.

Subchapter 4.1: Added ARM966E-S to List of supported ARM cores.

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Revision Date By Explanation

11 060607 SK

Subchapter 5.5.2.2 changed. Subchapter 5.5.2.3 added.

ARM9 download speed updated. Subchapter 8.2.1: Screenshot "Start sequence"

10 060526 SK

updated. Subchapter 8.2.2 "ID sequence" removed. Chapter "Support" and "FAQ" merged. Various improvements

Chapter "Literature and references" added. Chapter "Hardware":

9 060324 OO

Added common information trace signals. Added timing diagram for trace. Chapter "Designing the target board for trace" added.

8 060117 OO

Chapter "Related Software": Added JLinkARM.dll. Screenshots updated.

7 051208 OO Chapter Working with J-Link: Sketch added.

Chapter Working with J-Link: "Connecting multiple J-Links to your PC" added.

6 051118 OO

Chapter Working with J-Link: "Multi core debugging" added. Chapter Background information: "J-Link firmware" added.

5 051103 TQ Chapter Setup: "JTAG Speed" added.

Chapter Background information: "Flash program-

4 051025 OO

ming" added. Chapter Setup: "Scan chain configuration" added.

Some smaller changes. 3 051021 TQ Performance values updated. 2 051011 TQ Chapter "Working with J-Link" added. 1 050818 TW Initial version.

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About this document

This document describes J-Link and J-Trace. It provides an overview over the major features of J-Link and J-Trace, gives you some background information about JTAG, ARM and Tracing in general and describes J-Link and J-Trace related software packages available from Segger. Finally, the chapter Support and FAQs on page 259 helps to troubleshoot common problems.

For simplicity, we will refer to J-Link ARM as J-Link in this manual.

For simplicity, we will refer to J-Link ARM Pro as J-Link Pro in this manual.

Typographic conventions

This manual uses the following typographic conventions:

Style Used for

Body Body text.

Keyword

Reference Reference to chapters, tables and figures or other documents.

GUIElement Buttons, dialog boxes, menu names, menu commands.

Table 1.1: Typographic conventions

Text that you enter at the command-prompt or that appears on the display (that is system functions, file- or pathnames).

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SEGGER Microcontroller GmbH & Co. KG develops and distributes software development tools and ANSI C software components (middleware) for embedded systems in several industries such as telecom, medical technology, consumer electronics, automotive industry and industrial automation.

SEGGER’s intention is to cut software development time for embedded applications by offering compact flexible and easy to use middleware, allowing developers to concentrate on their application.

Our most popular products are emWin, a universal graphic software package for embedded applications, and embOS, a small yet efficient real-time kernel. emWin, written entirely in ANSI C, can easily be used on any CPU and most any display. It is complemented by the available PC tools: Bitmap Converter, Font Converter, Simulator and Viewer. embOS supports most 8/16/32-bit CPUs. Its small memory footprint makes it suitable for single-chip applications.

Apart from its main focus on software tools, SEGGER develops and produces programming tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in development, debugging and production, which has rapidly become the industry standard for debug access to ARM cores.

Corporate Office:

http://www.segger.com

EMBEDDED SOFTWARE (Middleware)

emWin

Graphics software and GUI

emWin is designed to provide an efficient, processor- and display controller-independent graphical user interface (GUI) for any application that operates with a graphical display. Starterkits, eval- and trial-versions are available.

embOS

Real Time Operating System

embOS is an RTOS designed to offer the benefits of a complete multitasking system for hard real time applications with minimal resources. The profiling PC tool embOSView is included.

emFile

File system

emFile is an embedded file system with FAT12, FAT16 and FAT32 support. emFile has been optimized for minimum memory consumption in RAM and ROM while maintaining high speed. Various Device drivers, e.g. for NAND and NOR flashes, SD/MMC and CompactFlash cards, are available.

United States Office:

http://www.segger-us.com

SEGGER TOOLS

Flasher

Flash programmer

Flash Programming tool primarily for microcontrollers.

J-Link

JTAG emulator for ARM cores

USB driven JTAG interface for ARM cores.

J-Trace

JTAG emulator with trace

USB driven JTAG interface for ARM cores with Trace memory. supporting the ARM ETM (Embedded Trace Macrocell).

J-Link / J-Trace Related Software

Add-on software to be used with SEGGER’s industry standard JTAG emulator, this includes flash programming software and flash breakpoints.

emUSB

USB device stack

A USB stack designed to work on any embedded system with a USB client controller. Bulk communication and most standard device classes are supported.

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1 Introduction....................................................................................................................19

1.1 Requirements.......................................................................................... 20

1.2 Supported OS .........................................................................................21

1.3 J-Link / J-Trace models ............................................................................ 22

1.3.1 Model comparison .................................................................................... 23

1.3.2 J-Link ARM .............................................................................................24

1.3.3 J-Link Ultra .............................................................................................27

1.3.4 J-Link ARM Pro ........................................................................................ 28

1.3.5 J-Link ARM Lite .......................................................................................29

1.3.6 J-Link Lite Cortex-M .................................................................................30

1.3.7 J-Trace ARM ...........................................................................................32

1.3.8 J-Trace for Cortex-M ................................................................................ 34

1.3.9 Flasher ARM............................................................................................36

1.3.10 J-Link ColdFire ........................................................................................37

1.4 Common features of the J-Link product family ............................................. 38

1.5 Supported CPU cores ...............................................................................39

1.6 Built-in intelligence for supported CPU-cores ...............................................40

1.6.1 Intelligence in the J-Link firmware .............................................................40

1.6.2 Intelligence on the PC-side (DLL) ...............................................................40

1.6.3 Firmware intelligence per model ................................................................42

1.7 Supported IDEs .......................................................................................44

2 Licensing........................................................................................................................45

2.1 Introduction............................................................................................46

2.2 Software components requiring a license .................................................... 47

2.3 License types ..........................................................................................48

2.3.1 Built-in license ........................................................................................48

2.3.2 Key-based license .................................................................................... 48

2.3.3 Device-based license................................................................................ 49

2.4 Legal use of SEGGER J-Link software.......................................................... 52

2.4.1 Use of the software with 3rd party tools...................................................... 52

2.5 Original SEGGER products.........................................................................53

2.5.1 J-Link ....................................................................................................53

2.5.2 J-Link Ultra .............................................................................................53

2.5.3 J-Link Pro ............................................................................................... 54

2.5.4 J-Trace................................................................................................... 54

2.5.5 J-Trace for Cortex-M ................................................................................ 55

2.5.6 Flasher ARM............................................................................................55

2.6 J-Link OEM versions................................................................................. 56

2.6.1 Analog Devices: mIDASLink ......................................................................56

2.6.2 Atmel: SAM-ICE ...................................................................................... 56

2.6.3 Digi: JTAG Link........................................................................................57

2.6.4 IAR: J-Link / J-Link KS ............................................................................. 57

2.6.5 IAR: J-Link Lite .......................................................................................57

2.6.6 IAR: J-Trace ...........................................................................................58

2.6.7 NXP: J-Link Lite LPC Edition ......................................................................58

2.6.8 SEGGER: J-Link Lite .................................................................................58

2.7 J-Link OBs ..............................................................................................59

2.8 Illegal Clones .......................................................................................... 60

3 J-Link and J-Trace related software...............................................................................61

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3.1 J-Link related software............................................................................. 62

3.1.1 J-Link software and documentation package ............................................... 62

3.1.2 List of additional software packages........................................................... 63

3.2 J-Link software and documentation package in detail ................................... 64

3.2.1 J-Link Commander (Command line tool)..................................................... 64

3.2.2 SWO Analyzer......................................................................................... 65

3.2.3 J-Link STR91x Commander (Command line tool) ......................................... 65

3.2.4 J-Link STM32 Commander (Command line tool) .......................................... 67

3.2.5 J-Link TCP/IP Server (Remote J-Link / J-Trace use) ..................................... 68

3.2.6 J-Mem Memory Viewer............................................................................. 69

3.2.7 J-Flash ARM (Program flash memory via JTAG) ........................................... 70

3.2.8 J-Link RDI (Remote Debug Interface)......................................................... 71

3.2.9 J-Link GDB Server ................................................................................... 72

3.3 Dedicated flash programming utilities for J-Link........................................... 73

3.3.1 Introduction ........................................................................................... 73

3.3.2 Supported Eval boards ............................................................................. 73

3.3.3 Supported flash memories ........................................................................ 74

3.3.4 How to use the dedicated flash programming utilities ................................... 74

3.3.5 Using the dedicated flash programming utilities for production and commercial purposes 74

3.3.6 F.A.Q..................................................................................................... 75

3.4 Additional software packages in detail ........................................................ 76

3.4.1 JTAGLoad (Command line tool) ................................................................. 76

3.4.2 J-Link Software Developer Kit (SDK) .......................................................... 76

3.4.3 J-Link Flash Software Developer Kit (SDK).................................................. 76

3.5 Using the J-LinkARM.dll............................................................................ 77

3.5.1 What is the JLinkARM.dll? ......................................................................... 77

3.5.2 Updating the DLL in third-party programs................................................... 77

3.5.3 Determining the version of JLinkARM.dll ..................................................... 78

3.5.4 Determining which DLL is used by a program .............................................. 78

4 Setup..............................................................................................................................79

4.1 Installing the J-Link ARM software and documentation pack .......................... 80

4.1.1 Setup procedure ..................................................................................... 80

4.2 Setting up the USB interface..................................................................... 83

4.2.1 Verifying correct driver installation ............................................................ 83

4.2.2 Uninstalling the J-Link USB driver .............................................................. 84

4.3 Setting up the IP interface........................................................................ 86

4.3.1 Configuring J-Link using J-Link Configurator................................................ 86

4.3.2 Configuring J-Link using the webinterface ................................................... 86

4.4 FAQs ..................................................................................................... 88

4.5 J-Link Configurator.................................................................................. 89

4.5.1 Configure J-Links using the J-Link Configurator ........................................... 89

4.6 J-Link USB identification........................................................................... 91

4.6.1 Connecting to different J-Links connected to the same host PC via USB .......... 91

5 Working with J-Link and J-Trace....................................................................................93

5.1 Connecting the target system ................................................................... 94

5.1.1 Power-on sequence ................................................................................. 94

5.1.2 Verifying target device connection ............................................................. 94

5.1.3 Problems................................................................................................ 94

5.2 Indicators .............................................................................................. 95

5.2.1 Main indicator ......................................................................................... 95

5.2.2 Input indicator ........................................................................................ 97

5.2.3 Output indicator ...................................................................................... 97

5.3 JTAG interface ........................................................................................ 98

5.3.1 Multiple devices in the scan chain .............................................................. 98

5.3.2 Sample configuration dialog boxes............................................................. 98

5.3.3 Determining values for scan chain configuration .........................................101

5.3.4 JTAG Speed ...........................................................................................102

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5.4 SWD interface ....................................................................................... 103

5.4.1 SWD speed ........................................................................................... 103

5.4.2 SWO .................................................................................................... 103

5.5 Multi-core debugging ............................................................................. 105

5.5.1 How multi-core debugging works ............................................................. 105

5.5.2 Using multi-core debugging in detail ........................................................ 106

5.5.3 Things you should be aware of ................................................................ 107

5.6 Connecting multiple J-Links / J-Traces to your PC ...................................... 109

5.6.1 How does it work? ................................................................................. 109

5.7 J-Link control panel................................................................................ 111

5.7.1 Tabs .................................................................................................... 111

5.8 Reset strategies .................................................................................... 117

5.8.1 Strategies for ARM 7/9 devices ................................................................ 117

5.8.2 Strategies for Cortex-M devices ............................................................... 119

5.9 Using DCC for memory access ................................................................. 121

5.9.1 What is required? .................................................................................. 121

5.9.2 Target DCC handler ............................................................................... 121

5.9.3 Target DCC abort handler ....................................................................... 121

5.10 J-Link script files ................................................................................... 122

5.10.1 Actions that can be customized ............................................................... 122

5.10.2 Script file API functions .......................................................................... 122

5.10.3 Global DLL variables .............................................................................. 126

5.10.4 Global DLL constants.............................................................................. 129

5.10.5 Script file language ................................................................................ 130

5.10.6 Script file writing example ...................................................................... 131

5.10.7 Executing J-Link script files ..................................................................... 131

5.11 Command strings .................................................................................. 133

5.11.1 List of available commands ..................................................................... 133

5.11.2 Using command strings .......................................................................... 139

5.12 Switching off CPU clock during debug ....................................................... 141

5.13 Cache handling...................................................................................... 142

5.13.1 Cache coherency ................................................................................... 142

5.13.2 Cache clean area ................................................................................... 142

5.13.3 Cache handling of ARM7 cores................................................................. 142

5.13.4 Cache handling of ARM9 cores................................................................. 142

6 Flash download............................................................................................................143

6.1 Introduction.......................................................................................... 144

6.2 Licensing .............................................................................................. 145

6.3 Supported devices ................................................................................. 146

6.4 Setup for various debuggers (internal flash).............................................. 147

6.4.1 IAR Embedded Workbench ...................................................................... 147

6.4.2 Keil MDK .............................................................................................. 147

6.4.3 J-Link GDB Server ................................................................................. 149

6.4.4 J-Link Commander................................................................................. 150

6.4.5 J-Link RDI ............................................................................................ 150

6.5 Setup for various debuggers (CFI flash).................................................... 151

6.5.1 IAR Embedded Workbench / Keil MDK ...................................................... 151

6.5.2 J-Link GDB Server ................................................................................. 152

6.5.3 J-Link commander ................................................................................. 152

6.6 Using the DLL flash loaders in custom applications ..................................... 153

7 Flash breakpoints.........................................................................................................155

7.1 Introduction.......................................................................................... 156

7.2 Licensing .............................................................................................. 157

7.2.1 24h flash breakpoint trial license ............................................................. 157

7.3 Supported devices ................................................................................. 158

7.4 Setup & compatibility with various debuggers............................................ 159

7.4.1 Setup................................................................................................... 159

7.4.2 Compatibility with various debuggers ....................................................... 159

Page 16

7.5 FAQ......................................................................................................160

8 RDI...............................................................................................................................161

8.1 Introduction ..........................................................................................162

8.1.1 Features ...............................................................................................162

8.2 Licensing...............................................................................................163

8.3 Setup for various debuggers ....................................................................164

8.3.1 IAR Embedded Workbench IDE ................................................................164

8.3.2 ARM AXD (ARM Developer Suite, ADS) ......................................................167

8.3.3 ARM RVDS (RealView developer suite) ......................................................169

8.3.4 GHS MULTI ...........................................................................................174

8.3.5 KEIL MDK (µVision IDE) ..........................................................................177

8.4 Configuration.........................................................................................180

8.4.1 Configuration file JLinkRDI.ini ..................................................................180

8.4.2 Using different configurations ..................................................................180

8.4.3 Using mutliple J-Links simulatenously .......................................................180

8.4.4 Configuration dialog ...............................................................................180

8.5 Semihosting ..........................................................................................189

8.5.1 Overview ..............................................................................................189

8.5.2 The SWI interface ..................................................................................189

8.5.3 Implementation of semihosting in J-Link RDI .............................................190

8.5.4 Semihosting with AXD.............................................................................190

8.5.5 Unexpected / unhandled SWIs .................................................................191

9 Device specifics...........................................................................................................193

9.1 Analog Devices ......................................................................................194

9.1.1 ADuC7xxx .............................................................................................194

9.2 ATMEL ..................................................................................................196

9.2.1 AT91SAM7 ............................................................................................197

9.2.2 AT91SAM9 ............................................................................................199

9.3 DSPGroup .............................................................................................200

9.4 Ember ..................................................................................................201

9.5 Energy Micro .........................................................................................202

9.6 Freescale ..............................................................................................203

9.6.1 Kinetis family.........................................................................................203

9.6.2 Unlocking ..............................................................................................203

9.6.3 Tracing .................................................................................................204

9.7 Fujitsu ..................................................................................................205

9.8 Itron ....................................................................................................206

9.9 Luminary Micro ......................................................................................207

9.9.1 Unlocking LM3Sxxx devices .....................................................................208

9.10 NXP......................................................................................................209

9.10.1 LPC ARM7-based devices.........................................................................210

9.10.2 Reset (Cortex-M3 based devices) .............................................................211

9.10.3 LPC288x flash programming ....................................................................211

9.10.4 LPC43xx: ..............................................................................................211

9.11 OKI ......................................................................................................212

9.12 Renesas................................................................................................213

9.13 Samsung ..............................................................................................214

9.13.1 S3FN60D ..............................................................................................214

9.14 ST Microelectronics.................................................................................215

9.14.1 STR91x.................................................................................................216

9.14.2 STM32F10xxx ........................................................................................216

9.14.3 STM32F2xxx..........................................................................................218

9.14.4 STM32F4xxx..........................................................................................218

9.15 Texas Instruments .................................................................................220

9.15.1 AM335x ................................................................................................220

9.15.2 AM35xx / AM37xx ..................................................................................221

9.15.3 OMAP4430 ............................................................................................221

9.15.4 OMAP-L138 ...........................................................................................221

Page 17

9.15.5 TMS470M ............................................................................................. 221

9.15.6 OMAP3530............................................................................................ 222

9.15.7 OMAP3550............................................................................................ 222

9.16 Toshiba ................................................................................................ 223

10 Target interfaces and adapters..................................................................................225

10.1 20-pin JTAG/SWD connector ................................................................... 226

10.1.1 Pinout for JTAG ..................................................................................... 226

10.1.2 Pinout for SWD...................................................................................... 229

10.2 38-pin Mictor JTAG and Trace connector ................................................... 231

10.2.1 Connecting the target board.................................................................... 231

10.2.2 Pinout .................................................................................................. 232

10.2.3 Assignment of trace information pins between ETM architecture versions ...... 234

10.2.4 Trace signals......................................................................................... 234

10.3 19-pin JTAG/SWD and Trace connector..................................................... 236

10.3.1 Target power supply .............................................................................. 237

10.4 9-pin JTAG/SWD connector ..................................................................... 238

10.5 Adapters .............................................................................................. 239

11 Background information.............................................................................................241

11.1 JTAG.................................................................................................... 242

11.1.1 Test access port (TAP)............................................................................ 242

11.1.2 Data registers ....................................................................................... 242

11.1.3 Instruction register ................................................................................ 242

11.1.4 The TAP controller ................................................................................. 243

11.2 Embedded Trace Macrocell (ETM)............................................................. 245

11.2.1 Trigger condition ................................................................................... 245

11.2.2 Code tracing and data tracing.................................................................. 245

11.2.3 J-Trace integration example - IAR Embedded Workbench for ARM ................ 245

11.3 Embedded Trace Buffer (ETB) ................................................................. 249

11.4 Flash programming ................................................................................ 250

11.4.1 How does flash programming via J-Link / J-Trace work?.............................. 250

11.4.2 Data download to RAM ........................................................................... 250

11.4.3 Data download via DCC .......................................................................... 250

11.4.4 Available options for flash programming ................................................... 250

11.5 J-Link / J-Trace firmware ........................................................................ 252

11.5.1 Firmware update ................................................................................... 252

11.5.2 Invalidating the firmware........................................................................ 252

12 Designing the target board for trace ..........................................................................255

12.1 Overview of high-speed board design ....................................................... 256

12.1.1 Avoiding stubs ...................................................................................... 256

12.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)............................... 256

12.1.3 Minimizing Crosstalk .............................................................................. 256

12.1.4 Using impedance matching and termination .............................................. 256

12.2 Terminating the trace signal.................................................................... 257

12.2.1 Rules for series terminators .................................................................... 257

12.3 Signal requirements............................................................................... 258

13 Support and FAQs.....................................................................................................259

13.1 Measuring download speed ..................................................................... 260

13.1.1 Test environment .................................................................................. 260

13.2 Troubleshooting .................................................................................... 261

13.2.1 General procedure ................................................................................. 261

13.2.2 Typical problem scenarios....................................................................... 261

13.3 Contacting support ................................................................................ 263

13.4 Frequently Asked Questions .................................................................... 264

14 Glossary.....................................................................................................................265

Page 18

15 Literature and references...........................................................................................271

Page 19

Chapter 1

Introduction

This chapter gives a short overview about J-Link and J-Trace.

Page 20

20 CHAPTER 1 Introduction

1.1 Requirements

Host System

To use J-Link or J-Trace you need a host system running Windows 2000 or later. For a list of all operating systems which are supported by J-Link, please refer to Supported OS on page 21.

Target System

A target system with a supported CPU is required. You should make sure that the emulator you are looking at supports your target CPU. For more information about which J-Link features are supported by each emulator, please refer to Model comparison on page 23.

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1.2 Supported OS

J-Link/J-Trace can be used on the following operating systems:

• Microsoft Windows 2000

• Microsoft Windows XP

• Microsoft Windows XP x64

• Microsoft Windows Vista

• Microsoft Windows Vista x64

•Windows 7

•Windows 7 x64

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22 CHAPTER 1 Introduction

1.3 J-Link / J-Trace models

J-Link / J-Trace is available in different variations, each designed for different purposes / target devices. Currently, the following models of J-Link / J-Trace are available:

•J-Link ARM

•J-Link Ultra

•J-Link ARM Pro

•J-Trace ARM

•J-Trace for Cortex-M

In the following, the different J-Link / J-Trace models are described and the changes between the different hardware versions of each model are listed. To determine the hardware version of your J-Link / J-Trace, the first step should be to look at the label at the bottom side of the unit. J-Links / J-Traces have the hardware version printed on the back label.

If this is not the case with your J-Link / J-Trace, start JLink.exe. As part of the initial message, the hardware version is displayed.

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1.3.1 Model comparison

The following tables show the features which are included in each J-Link / J-Trace model.

Hardware features

J-Link J-Link Pro

J-Trace

for Cortex-M

J-Trace

USB yes yes yes yes Ethernet no yes no no

ARM7/9/11, Cortex-A5/A8, Cortex-M0/M1/ M3/M4, Cortex-A5/A8/A9/ R4

ARM 7/9 (no tracing), Cortex-M0/M1/ M3/M4

ARM 7/9

Supported cores

ARM7/9/11, Cortex-A5/A8, Cortex-M0/M1/ M3/M4, Cortex-A5/A8/A9/

R4 JTAG yes yes yes yes SWD yes yes yes no SWO yes yes yes no ETM Tracenonoyesyes

Software features

Software features are features implemented in the software primarily on the host. Software features can either come with the J-Link or be added later using a license string from Segger.

J-Link J-Link Pro

J-Trace

for Cortex-M

J-Trace

J-Flash yes(opt) yes yes(opt) yes(opt)

Flash breakpoints

Flash download

yes(opt) yes yes(opt) yes(opt)

GDB Server yes(opt) yes yes(opt) yes(opt) RDI yes(opt) yes yes(opt) yes(opt)

Most IDEs come with its own flashloaders, so in most cases this feature is not essential for debugging your applications in flash. The J-Link flash download (FlashDL) feature is mainly used in debug environments where the debugger does not come with an own flashloader (for example, the GNU Debugger). For more information about how flash download via FlashDL works, please refer to Flash download on page 143.

In order to use the flash breakpoints with J-Link no additional license for flash download is required. The flash breakpoint feature allows setting an unlimited number of breakpoints even if the application program is not located in RAM, but in flash memory. Without this feature, the number of breakpoints which can be set in flash is limited to the number of hardware breakpoints (typically two for ARM 7/9, up to six for Cortex-M) For more information about flash breakpoints, please refer to Flash breakpoints on page 155.

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24 CHAPTER 1 Introduction

1.3.2 J-Link ARM

J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC running Microsoft Windows 2000 or later. For a complete list of all operating systems which are supported, please refer to Supported OS on page 21. J-Link has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM.

1.3.2.1 Additional features

• Direct download into flash memory of most popular microcontrollers supported

• Full-speed USB 2.0 interface

• Serial Wire Debug supported *

• Serial Wire Viewer supported *

• Download speed up to 720 KBytes/second **

• JTAG speed up to 12 MHz

• RDI interface available, which allows using J-Link with RDI compliant software

* = Supported since J-Link hardware version 6

** = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed.

1.3.2.2 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link ARM. All values are valid for J-Link ARM hardware version 8.

General

For a complete list of all operating sys-

Supported OS

Electromagnetic compatibility (EMC) EN 55022, EN 55024 Operating temperature +5°C ... +60°C Storage temperature -20°C ... +65 °C Relative humidity (non-condensing) Max. 90% rH

Mechanical

Size (without cables) 100mm x 53mm x 27mm Weight (without cables) 70g

Available interfaces

USB interface USB 2.0, full speed

Target interface

JTAG/SWD Interface, Electrical

Power supply

Target interface voltage (V

Target supply voltage 4.5V ... 5V (if powered with 5V on USB) Target supply current Max. 300mA

Reset Type

Reset low level output voltage (V

For the whole target voltage range (1.2V <= VIF <= 5V)

Table 1.1: J-Link ARM specifications

)

tems which are supported, please refer to Supported OS on page 21.

JTAG 20-pin (14-pin adapter available)

USB powered Max. 50mA + Target Supply current.

1.2V ... 5V

Open drain. Can be pulled low or tristated.

<= 10% of V

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2004-2012 SEGGER Microcontroller GmbH & Co. KG

Page 25

LOW level input voltage (V

HIGH level input voltage (VIH)V

<= 40% of V

>= 60% of V

For 1.8V <= VIF <= 3.6V

LOW level output voltage (V load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

) with a

<= 10% of V

>= 90% of V

For 3.6 <= VIF <= 5V

LOW level output voltage (V load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

) with a

<= 20% of V

>= 80% of V

JTAG/SWD Interface, Timing

SWO sampling frequency Max. 6 MHz Data input rise time (T

Data input fall time (T

Data output rise time (T

Data output fall time (T

Clock rise time (T

Clock fall time (T

Table 1.1: J-Link ARM specifications

rdi

fdi

rdo

fdo

<= 20ns

rdi

<= 20ns

fdi

<= 10ns

rdo

<= 10ns

fdo

<= 10ns

1.3.2.3 Download speed

The following table lists performance values (Kbytes/s) for writing to memory (RAM):

Hardware

J-Link Rev. 6 — 8

Table 1.2: Download speed differences between hardware revisions

720 Kbytes/s (12MHz JTAG)

ARM7

via JTAG

550 Kbytes/s (12MHz JTAG)

ARM9

via JTAG

Cortex-M3

via SWD

180 Kbytes/s (12 MHz SWD)

All tests have been performed in the testing environment which is described on Mea- suring download speed on page 260.

The actual speed depends on various factors, such as JTAG/SWD, clock speed, host CPU core etc.

1.3.2.4 Hardware versions

Versions 1-4

Obsolete.

Version 5.0

Identical to version 4.0 with the following exception:

• Uses a 32-bit RISC CPU.

• Maximum download speed (using DCC) is over 700 Kbytes/second.

• JTAG speed: Maximum JTAG frequency is 12 MHz; possible JTAG speeds are: 48 MHz / n, where n is 4, 5, ..., resulting in speeds of:

12.000 MHz (n = 4)

9.600 MHz (n = 5)

8.000 MHz (n = 6)

6.857 MHz (n = 7)

6.000 MHz (n = 8)

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26 CHAPTER 1 Introduction

5.333 MHz (n = 9)

4.800 MHz (n = 10)

• Supports adaptive clocking.

Version 5.2

Identical to version 5.0 with the following exception:

• Target interface: RESET is open drain

Version 5.3

Identical to version 5.2 with the following exception:

• 5V target supply current limited 5V target supply (pin 19) of Kick-Start versions of J-Link is current monitored and limited. J-Link automatically switches off 5V supply in case of over-current to protect both J-Link and host computer. Peak current (<= 10 ms) limit is 1A, operating current limit is 300mA.

Version 5.4

Identical to version 5.3 with the following exception:

• Supports 5V target interfaces.

Version 6.0

Identical to version 5.4 with the following exception:

• Outputs can be tristated (Effectively disabling the JTAG interface)

• Supports SWD interface.

• SWD speed: Software implementation. 4 MHz maximum SWD speed.

• J-Link supports SWV (Speed limited to 500 kHz)

Version 7.0

Identical to version 6.0 with the following exception:

• Uses an additional pin to the UART unit of the target hardware for SWV support (Speed limited to 6 MHz).

Version 8.0

Identical to version 7.0 with the following exception:

• SWD support for non-3.3V targets.

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2004-2012 SEGGER Microcontroller GmbH & Co. KG

Page 27

1.3.3 J-Link Ultra

J-Link Ultra is a JTAG/SWD emulator designed for ARM/Cortex and other supported CPUs. It is fully compatible to the standard J-Link and works with the same PC software. Based on the highly optimized and proven J-Link, it offers even higher speed as well as target power measurement capabilities due to the faster CPU, built-in FPGA and High speed USB interface. It connects via USB to a PC running Microsoft Windows 2000 or later. For a complete list of all operating systems which are supported, please refer to Supported OS on page 19.. J-Link Ultra has a built-in 20-pin JTAG/SWD connector.

1.3.3.1 Additional features

• Fully compatible to the standard J-Link

• Very high performance for all supported CPU cores

• Hi-Speed USB 2.0 interface

• JTAG speed up to 25 MHz

• Serial Wire Debug (SWD) supported

• Serial Wire Viewer (SWV) supported

• SWV: UART and Manchester encoding supported

• SWO sampling frequencies up to 25 MHz

• Target power can be supplied

• Target power consumption can be measured with high accuracy. External ADC can be connected via SPI

1.3.3.2 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link Ultra. All values are valid for J-Link Ultra hardware version 1.

Note: Some specifications, especially speed, are likely to be improved in the future with newer versions of the J-Link software (freely available).

General

For a complete list of all operating sys-

Supported OS

Electromagnetic compatibility (EMC) EN 55022, EN 55024 Operating temperature +5°C ... +60°C Storage temperature -20°C ... +65 °C Relative humidity (non-condensing) Max. 90% rH

Mechanical

Size (without cables) 100mm x 53mm x 27mm Weight (without cables) 73g

Available interfaces

USB interface USB 2.0, Hi-Speed Target interface JTAG/SWD 20-pin External (SPI) analog power measure-

ment interface

JTAG/SWD Interface, Electrical

Target interface voltage (V

Target supply voltage 4.5V ... 5V Target supply current Max. 300mA

Reset Type

Table 1.3: J-Link Ultra specifications

)

tems which are supported, please refer to Supported OS on page 21.

4-pin (Pins 14, 16, 18 and 20 of the 20pin JTAG/SWD interface)

1.8V ... 5V

Open drain. Can be pulled low or tristated.

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28 CHAPTER 1 Introduction

Reset low level output voltage (V

<= 10% of V

For the whole target voltage range (1.8V <= VIF <= 5V)

LOW level input voltage (V

HIGH level input voltage (VIH)V

<= 40% of V

>= 60% of V

For 1.8V <= VIF <= 3.6V

LOW level output voltage (V load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

) with a

<= 10% of V

>= 90% of V

For 3.6 <= VIF <= 5V

LOW level output voltage (V load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

) with a

<= 20% of V

>= 80% of V

JTAG/SWD Interface, Timing

SWO sampling frequency Max. 25 MHz Data input rise time (T

Data input fall time (T

Data output rise time (T

Data output fall time (T

Clock rise time (T

Clock fall time (T

rdi

fdi

rdo

fdo

<= 20ns

rdi

<= 20ns

fdi

<= 10ns

rdo

<= 10ns

fdo

<= 10ns

Analog power measurement interface

Sampling frequency 50 kHz Resolution 1 mA

External (SPI) analog interface

SPI frequency Max. 4 MHz Samples/sec Max. 50000 Resolution Max. 16-bit

Table 1.3: J-Link Ultra specifications

1.3.4 J-Link ARM Pro

J-Link Pro is a JTAG emulator designed for ARM cores. It is fully compatible to J-Link and connects via Ethernet/USB to a PC running Microsoft Windows 2000 or later. For a complete list of all operating systems which are supported, please refer to Supported OS on page 19. Additional support for Cortex-R4 and Cortex-R8 cores will be available in the near future. J-Link Pro comes with licenses for all J-Link related SEGGER software products which allows using J-Link Pro "out-of-the-box".

1.3.4.1 Additional features

• Fully compatible to J-Link ARM

• More memory for future firmware extensions (ARM11, XScale, Cortex R4 and Cortex A8)

• Additional LEDs for power and RESET indication

• Comes with web interface for easy TCP/IP configuration (built-in web server)

• Built-in GDB Server (planned to be implemented in the near future)

• Serial Wire Debug supported

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2004-2012 SEGGER Microcontroller GmbH & Co. KG

Page 29

• Serial Wire Viewer supported

• Download speed up to 720 KBytes/second ** (higher download speeds will be available in the near future)

• DCC speed up to 800 Kbytes/second **

• Comes with licenses for: J-Link ARM RDI, J-Link ARM FlashBP, J-Link ARM FlashDL, J-Link ARM GDB Server and J-Flash ARM.

• Embedded Trace Buffer (ETB) support

• Galvanic isolation from host via Ethernet

• RDI interface available, which allows using J-Link with RDI compliant software

** = Measured with J-Link Pro Rev. 1.1, ARM7 @ 50 MHz, 12MHz JTAG speed.

1.3.4.2 Download speed

The following table lists performance values (Kbytes/s) for writing to memory (RAM):

Hardware

Rev. 1 via USB

Rev. 1 via TCP/IP

Table 1.4: Download speed differences between hardware revisions

All tests have been performed in the testing environment which is described on Measuring download speed on page 260.

The actual speed depends on various factors, such as JTAG/SWD, clock speed, host CPU core etc.

720 Kbytes/s (12 MHz JTAG)

ARM7

via JTAG

550 Kbytes/s (12 MHz JTAG)

ARM9

via JTAG

Cortex-M3

via SWD

190 Kbytes/s (12 MHz SWD)

190 Kbytes (12 MHz SWD)

1.3.4.3 Hardware versions

Version 1.1

Compatible to J-Link ARM.

• Provides an additional Ethernet interface which allows to communicate with JLink via TCP/IP.

1.3.5 J-Link ARM Lite

J-Link ARM Lite is a fully functional OEM-version of J-Link ARM. If you are selling evaluation-boards, J-Link ARM Lite is an inexpensive emulator solution for you. Your customer receives a widely acknowledged JTAG-emulator which allows him to start right away with his development.

1.3.5.1 Additional features

• Very small form factor

• Fully software compatible to J-Link ARM

• Any ARM7/9/11, Cortex-A5/A8, Cortex-M0/M1/M3/M4, Cortex-R4 core supported

•JTAG clock up to 4 MHz

• SWD, SWO supported for Cortex-M devices

• Flash download into supported MCUs

• Standard 20-pin 0.1 inch JTAG connector (compatible to J-Link ARM)

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30 CHAPTER 1 Introduction

1.3.5.2 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link ARM Lite. All values are valid for J-Link ARM hardware version 8.

General

For a complete list of all operating sys-

Supported OS

Electromagnetic compatibility (EMC) EN 55022, EN 55024 Operating temperature +5°C ... +60°C Storage temperature -20°C ... +65 °C Relative humidity (non-condensing) Max. 90% rH Size (without cables) 28mm x 26mm x 7mm Weight (without cables) 6g

Mechanical

USB interface USB 2.0, full speed

Target interface

JTAG/SWD Interface, Electrical

Power supply

Target interface voltage (V

)

Target supply voltage 4.5V ... 5V (if powered with 5V on USB) Target supply current Max. 300mA LOW level input voltage (V

) Max. 40% of V

HIGH level input voltage (VIH) Min. 60% of V

JTAG/SWD Interface, Timing

Data input rise time (T

Data input fall time (T

Data output rise time (T

Data output fall time (T

Clock rise time (T

Clock fall time (T

Table 1.5: J-Link ARM Lite specifications

)

rdi

fdi

)

rdo

fdo

)

tems which are supported, please refer to Supported OS on page 21.

JTAG 20-pin (14-pin adapter available)

USB powered Max. 50mA + Target Supply current.

3.3V

Max. 20ns

Max. 10ns

1.3.6 J-Link Lite Cortex-M

J-Link Lite Cortex-M is a specific OEM-version of SEGGER J-Link Lite which is designed to be used with Cortex-M devices. If you are selling evaluation-boards, J-Link Lite CortexM is an inexpensive emulator solution for you. Your customer receives a widely acknowledged JTAG/SWD-emulator which allows him to start right away with his development.

• Very small form factor

• Fully software compatible to J-Link

• Any Cortex-M0/M1/M3/M4 core supported

•JTAG clock up to 4 MHz

• SWD, SWO supported

• Flash download into supported MCUs

• Standard 9- & 19-pin 0.05'' Samtec FTSH connector

• 3.3V target interface voltage

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1.3.6.1 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link Lite Cortex-M.

General

For a complete list of all operating sys-

Supported OS

Mechanical

USB interface USB 2.0, full speed

Tar g e t i nt e rf a ce

JTAG/SWD Interface, Electrical

Power supply

Target interface voltage (V

)

Target supply voltage 4.5V ... 5V Target supply current Max. 300mA LOW level input voltage (V

) Max. 40% of V

HIGH level input voltage (VIH) Min. 60% of V

JTAG/SWD Interface, Timing

Data input rise time (T

Data input fall time (T

Data output rise time (T

Data output fall time (T

Clock rise time (T

Clock fall time (T

Table 1.6: J-Link Lite Cortex-M specifications

)

fdi

rdi

)

rdo

fdo

)

tems which are supported, please refer to Supported OS on page 21.

19-pin 0.05'' Samtec FTSH connector 9-pin 0.05'' Samtec FTSH connector

USB powered Max. 50mA + Target Supply current.

3.3V

Max. 20ns

Max. 10ns

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32 CHAPTER 1 Introduction

1.3.7 J-Trace ARM

J-Trace is a JTAG emulator designed for ARM cores which includes trace (ETM) support. It connects via USB to a PC running Microsoft Windows 2000 or later. For a complete list of all operating systems which are supported, please refer to Supported OS on page 19. J-Trace has a built-in 20-pin JTAG connector and a built in 38-pin JTAG+Trace connector, which are compatible to the standard 20-pin connector and 38-pin connector defined by ARM.

1.3.7.1 Additional features

• Supports tracing on ARM7/9 targets

• JTAG speed up to 12 MHz

• Download speed up to 420 Kbytes/second *

• DCC speed up to 600 Kbytes/second *

* = Measured with J-Trace, ARM7 @ 50 MHz, 12MHz JTAG speed.

1.3.7.2 Specifications for J-Trace

General

For a complete list of all operating sys-

Supported OS

Electromagnetic Compatibility (EMC) EN 55022, EN 55024 Operating Temperature +5°C ... +40°C Storage Temperature -20°C ... +65 °C Relative Humidity (non-condensing) <90% rH Size (without cables) 123mm x 68mm x 30mm Weight (without cables) 120g

Mechanical

USB Interface USB 2.0, full speed

Target Interface

JTAG/SWD Interface, Electrical

Power Supply USB powered < 300mA Supported Target interface voltage 3.0 - 3.6 V (5V adapter available)

Table 1.7: J-Trace specifications

tems which are supported, please refer to Supported OS on page 21.

JTAG 20-pin (14-pin adapter available) JTAG+Trace: Mictor, 38-pin

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1.3.7.3 Download speed

The following table lists performance values (Kbytes/s) for writing to memory (RAM):

Hardware ARM7 via JTAG ARM9 via JTAG

J-Trace Rev. 1

Table 1.8: Download speed differences between hardware revisions

All tests have been performed in the testing environment which is described on Measuring download speed on page 260.

The actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

420.0 Kbytes/s (12MHz JTAG)

280.0 Kbytes/s (12MHz JTAG)

1.3.7.4 Hardware versions

Version 1

This J-Trace uses a 32-bit RISC CPU. Maximum download speed is approximately 420 KBytes/second (600 KBytes/second using DCC).

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34 CHAPTER 1 Introduction

1.3.8 J-Trace for Cortex-M

J-Trace for Cortex-M is a JTAG/SWD emulator designed for Cortex-M cores which includes trace (ETM) support. J-Trace for Cortex-M can also be used as a J-Link and it also supports ARM7/9 cores. Tracing on ARM7/9 targets is not supported.

1.3.8.1 Additional features

• Has all the J-Link functionality

• Supports tracing on Cortex-M targets

1.3.8.2 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for J-Trace for Cortex-M. All values are valid for the latest hardware version of J-Trace for Cortex-M.

General

For a complete list of all operating sys-

Supported OS

tems which are supported, please refer

to Supported OS on page 19. Electromagnetic compatibility (EMC) EN 55022, EN 55024 Operating temperature +5°C ... +60°C Storage temperature -20°C ... +65 °C Relative humidity (non-condensing) Max. 90% rH Size (without cables) 123mm x 68mm x 30mm Weight (without cables) 120g

Mechanical

USB interface USB 2.0, Hi-Speed

JTAG/SWD 20-pin Target interface

(14-pin adapter available)

JTAG/SWD + Trace 19-pin

JTAG/SWD Interface, Electrical

Power supply

Target interface voltage (V

)

USB powered

Max. 50mA + Target Supply current.

1.2V ... 5V Target supply voltage 4.5V ... 5V (if powered with 5V on USB) Target supply current Max. 300mA LOW level input voltage (V

HIGH level input voltage (VIH) Min. 60% of V

) Max. 40% of V

JTAG/SWD Interface, Timing

Data input rise time (T

Data input fall time (T

Data output rise time (T

Data output fall time (T

Clock rise time (T

Table 1.9: J-Trace for Cortex-M3 specifications

)

rdi

fdi

)

rdo

fdo

)

Max. 20ns

)

Max. 10ns

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2004-2012 SEGGER Microcontroller GmbH & Co. KG

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Clock fall time (T

)

Power supply

Target interface voltage (V

Voltage interface low pulse (V

Voltage interface high pulse (VIH) Min. 60% of V

TRACECLK low pulse width (T

TRACECLK high pulse width (T

)

Data rise time (T

Data fall time (T

Clock rise time (T

Clock fall time (T

Data setup time (T

Data hold time (T

Table 1.9: J-Trace for Cortex-M3 specifications

1.3.8.3 Download speed

Max. 10ns

Trace Interface, Electrical

USB powered Max. 50mA + Target Supply current.

)

) Max. 40% of V

1.2V ... 5V

Trace Interface, Timing

)

Min. 2ns

Max. 3ns

Min. 3ns

Min. 2ns

The following table lists performance values (Kbytes/s) for writing to memory (RAM):

Hardware Cortex-M3

J-Trace for Cortex-M3 V2

J-Trace for Cortex-M V3.1

Table 1.10: Download speed differences between hardware revisions

190 Kbytes/s (12MHz SWD) 760 KB/s (12 MHz JTAG)

190 Kbytes/s (12MHz SWD) 1440 KB/s (25 MHz JTAG)

The actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

1.3.8.4 Hardware versions

Version 2

Obsolete.

Version 3.1

Identical to version 2.0 with the following exceptions:

•Hi-Speed USB

• Voltage range for trace signals extended to 1.2 - 3.3 V

•Higher download speed

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36 CHAPTER 1 Introduction

1.3.9 Flasher ARM

1.3.9.1 Specifications

The following table gives an overview about the specifications (general, mechanical, electrical) for Flasher ARM.

General

For a complete list of all operating sys-

Supported OS

Mechanical

USB interface USB 2.0, full speed Target interface JTAG/SWD 20-pin

JTAG Interface, Electrical

Power supply

Target interface voltage (V

)

Target supply voltage 4.5V ... 5V (if powered with 5V on USB) Target supply current Max. 300mA

For the whole target voltage range (1.8V <= V

LOW level input voltage (V

) Max. 40% of V

HIGH level input voltage (VIH) Min. 60% of V

For 1.8V <= VIF <= 3.6V

tems which are supported, please refer to Supported OS on page 19.

USB powered Max. 50mA + Target Supply current.

1.2V ... 5V

<= 5V)

LOW level output voltage (V

) with a

load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

For 3.6 <= VIF <= 5V

LOW level output voltage (V

) with a

load of 10 kOhm HIGH level output voltage (VOH) with a load of 10 kOhm

SWD Interface, Electrical

Power supply

Target interface voltage (V

)

Target supply voltage 4.5V ... 5V (if powered with 5V on USB)

Table 1.11: Flasher ARM specifications

J-Link / J-Trace (UM08001) ©

Max. 10% of V

Min. 90% of V

Max. 20% of V

Min. 80% of V

USB powered Max. 50mA + Target Supply current.

1.2V ... 5V (SWD interface is 5V tolerant

but can output a maximum of 3.3V SWD signals)

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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Target supply current Max. 300mA LOW level input voltage (V

HIGH level input voltage (V

LOW level output voltage (V load of 10 kOhm HIGH level output voltage (V load of 10 kOhm

Table 1.11: Flasher ARM specifications

)

) with a

Max. 0.8V

Min. 2.0V

Max. 0.5V

Min. 2.85V

1.3.10 J-Link ColdFire

J-Link ColdFire is a BDM emulator designed for ColdFire® cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, or Windows Vista. J-Link ColdFire has a built-in 26-pin BDM connector, which is compatible to the standard 26-pin connector defined by Freescale. For more information about J-Link ColdFire BDM 26, please refer to UM08009, J-Link ColdFire BDM26 User’s Guide.

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38 CHAPTER 1 Introduction

1.4 Common features of the J-Link product family

• USB 2.0 interface (Full-Speed/Hi-Speed, depends on J-Link model)

• Any ARM7/9/11 (including thumb mode), Cortex-A5/A8, Cortex-M0/M1/M3/M4, Cortex-R4 core supported

• Automatic core recognition

• Maximum JTAG speed 12/25 MHz (depends on J-Link model)

• Seamless integration into the IAR Embedded Workbench® IDE

• No power supply required, powered through USB

• Support for adaptive clocking

• All JTAG signals can be monitored, target voltage can be measured

• Support for multiple devices

• Fully plug and play compatible

• Standard 20-pin JTAG/SWD connector, 19-pin JTAG/SWD and Trace connector, standard 38-pin JTAG+Trace connector

• USB and 20-pin ribbon cable included

• Memory viewer (J-Mem) included

• TCP/IP server included, which allows using J-Trace via TCP/IP networks

• RDI interface available, which allows using J-Link with RDI compliant software

• Flash programming software (J-Flash) available

• Flash DLL available, which allows using flash functionality in custom applications

• Software Developer Kit (SDK) available

• Full integration with the IAR C-SPY® debugger; advanced debugging features available from IAR C-SPY debugger.

• 14-pin JTAG adapter available

• J-Link 19-pin Cortex-M Adapter available

• J-Link 9-pin Cortex-M Adapter available

• Adapter for 5V JTAG targets available for hardware revisions up to 5.3

• Optical isolation adapter for JTAG/SWD interface available

• Target power supply via pin 19 of the JTAG/SWD interface (up to 300 mA to target with overload protection), alternatively on pins 11 and 13 of the Cortex-M 19-pin trace connector

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1.5 Supported CPU cores

J-Link / J-Trace has been tested with the following cores, but should work with any ARM7/9/11, Cortex-M0/M1/M3/M4 and Cortex-A5/A8/A9/R4 core. If you experience problems with a particular core, do not hesitate to contact Segger.

• ARM7TDMI (Rev 1)

• ARM7TDMI (Rev 3)

• ARM7TDMI-S (Rev 4)

• ARM720T

• ARM920T

• ARM922T

• ARM926EJ-S

• ARM946E-S

• ARM966E-S

• ARM1136JF-S

• ARM1136J-S

• ARM1156T2-S

• ARM1156T2F-S

• ARM1176JZ-S

• ARM1176JZF

• ARM1176JZF-S

•Cortex-A5

•Cortex-A8

•Cortex-A9

•Cortex-M0

•Cortex-M1

•Cortex-M3

•Cortex-M4

•Cortex-R4

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40 CHAPTER 1 Introduction

1.6 Built-in intelligence for supported CPU-cores

In general, there are two ways to support a CPU-core in the J-Link software:

1. Intelligence in the J-Link firmware

2. Intelligence on the PC-side (DLL)

Having the intelligence in the firmware is ideal since it is much more powerful and robust. The J-Link PC software automatically detects which implementation level is supported for the connected CPU-core. If Intelligence in the firmware is available, it is used. If you are using a J-Link that does not have intelligence in the firmware and only PC-side intelligence is available for the connected CPU, a warning message is shown.

1.6.1 Intelligence in the J-Link firmware

On newer J-Links, the intelligence for a new CPU-core is also available in the J-Link firmware which means, for these J-Links the target sequences are no longer generated on the PC-side but directly inside the J-Link. Having the intelligence in the firmware leads to improved stability and higher performance.

1.6.2 Intelligence on the PC-side (DLL)

This is the basic implementation level for support of a CPU-core. This implementation is not J-Link model dependend, since no intelligence for the CPU-core is necessary in the J-Link firmware. This means, all target sequences (JTAG/SWD/...) are generated on the PC-side and the J-Link simply sends out these sequences and sends the result back to the DLL. Using this way of implementation also allows old J-Links to be used with new CPU cores as long as a DLL-Version is used which has intelligence for the CPU.

But there is one big disadvantage of implementing the CPU core support on the DLLside: For every sequence which shall be send to the target a USB or Ethernet transaction is triggered. The long latency especially on a USB connection significantly affects the performance of J-Link. This is true especially, when performing actions where J-Link has to wait for the CPU frequently. An example is a memory read/write operation which needs to be followed by status read operations or repeated until the memory operation is completed. Performing this kind of task with only PC-side intelligence will have to either make some assumption like: Operation is completed after a given number of cycles or will have to make a lot of USB/Ethernet transactions. The first option (fast mode) will not work under some circumstances such as low CPU speeds, the second (slow mode) will be more reliable but very slow due to the high number of USB/Ethernet transactions. It simply boils down to: The best solution is having intelligence in the emulator itself!

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1.6.2.1 Limitations of PC-side implementations

• Instability, especially on slow targets Due to the fact that a lot of USB transactions would cause a very bad performance of J-Link, on PC-side implementations the assumption is made that the CPU/Debug interface is fast enough to handle the commands/requests without the need of waiting. So, when using the PC-side-intelligence, stability can not be guaranteed in all cases, especially if the target interface speed (JTAG/SWD/...) is significantly higher than the CPU speed.

• Poor performance Since a lot more data has to be transferred over the host interface (typ. USB), the resulting download speed is typically much lower than for implementations with intelligence in the firmware, even if the number of transactions over the host interface is limited to a minimum (fast mode).

• No support Please understand that we can not give any support if you are running into problems when using a PC-side implementation.

Note: Due to these limitations, we recommend to use PC-side implementations for evaluation only.

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42 CHAPTER 1 Introduction

1.6.3 Firmware intelligence per model

There are different models of J-Link / J-Trace which have built-in intelligence for different CPU-cores. In the following, we will give you an overview about which model of J-Link / J-Trace has intelligence for which CPU-core.

1.6.3.1 Current models

The table below lists the firmware CPU support for J-Link & J-Trace models currently available.

Version

J-Link / J-Trace

model

J-Link 8

J-Link Pro 3

J-Link Ultra 1

J-Link Lite 8

J-Link Lite Cortex-M 8

J-Link Lite RX 8

ARM

7/9

JTAG JTAG JTAG JTAG SWD JTAG

ARM11Cortex-

A/R

Cortex-M

Renesas

RX600

! ! ! ! ! !

" " "

" " " " "

! !

J-Trace ARM 1

J-Trace for Cortex-M 3

Table 1.12: Built-in intelligence of current J-Links

" " "

" " " " "

! !

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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1.6.3.2 Older models

The table below lists the firmware CPU support for older J-Link & J-Trace models which are not sold anymore.

Version

J-Link / J-Trace

model

J-Link 3

J-Link 4

J-Link 5

J-Link 6

J-Link 7

J-Link Pro 1

ARM

7/9

JTAG JTAG JTAG JTAG SWD JTAG

" " " " "

ARM11Cortex-

A/R

" " " "

" " "

Cortex-M

not supported

Renesas

RX600

! ! ! ! ! !

J-Trace for Cortex-M 1

Table 1.13: Built-in intelligence of older J-Link models

" "

! ! !

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44 CHAPTER 1 Introduction

1.7 Supported IDEs

J-Link / J-Trace can be used with different IDEs. Some IDEs support J-Link directly, for other ones additional software (such as J-Link RDI) is necessary in order to use JLink. The following tables list which features of J-Link / J-Trace can be used with the different IDEs.

ARM7/9

IDE

Debug

support

download

Flash

breakpoints

Trace

support

IAR EWARM yes yes yes yes Keil MDK yes yes yes no Rowley yes yes no no CodeSourceryyesnonono Yargato (GDB) yes yes yes no RDI compliant

toolchains such as

yes

RVDS/ADS

ARM Cortex-M3

IDE

Debug

support

Flash

download

Flash

breakpoints

IAR EWARM yes yes yes yes yes Keil MDK yes yes yes yes yes Rowley yes yes no no no CodeSourcery yes no no no no Yargato (GDB) yes yes yes no no

Trace

support

SWO

ARM11

ARM11 has currently been tested with IAR EWARM only.

IDE

Debug

support

IAR EWARM yes

Rowley yes

Yargato ( GD B ) yes

Requires J-Link RDI license for download of more than 32KBytes

Coming soon

Requires emulator with trace support

Debug support includes the following: Download to RAM, memory read/write, CPU

Flash

download

Flash

breakpoints

no no no

Trace

support

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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Chapter 2

Licensing

This chapter describes the different license types of J-Link related software and the legal use of the J-Link software with original SEGGER and OEM products.

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46 CHAPTER 2 Licensing

2.1 Introduction

J-Link functionality can be enhanced by the features J-Flash, RDI, flash download and flash breakpoints (FlashBP). The flash breakpoint feature does not come with J-Link and need an additional license. In the following the licensing options of the software will be explained.

J-Link / J-Trace (UM08001) ©

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2.2 Software components requiring a license

There are different software components which need an additional license:

•J-Flash

•J-Link RDI

• Flash breakpoints (FlashBP)

For more information about J-Link RDI licensing procedure / license types, please refer to the J-Link RDI User Guide (UM08004), chapter Licensing.

For more information about J-Flash licensing procedure / license types, please refer to the J-Flash User Guide (UM08003), chapter Licensing.

In the following the licensing procedure and license types of the flash breakpoint feature are explained.

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48 CHAPTER 2 Licensing

2.3 License types

For each of the software components which require an additional license, there are three types of licenses:

Built-in License

This type of license is easiest to use. The customer does not need to deal with a license key. The software automatically finds out that the connected J-Link contains the built-in license(s). This is the type of license you get if you order J-Link and the license at the same time, typically in a bundle.

Key-based license

This type of license is used if you already have a J-Link, but want to enhance its functionality by using flash breakpoints. In addition to that, the key-based license is used for trial licenses. To enable this type of license you need to obtain a license key from SEGGER. Free trial licenses are available upon request from www.segger.com. This license key has to be added to the J-Link license management. How to enter a license key is described in detail in Licensing on page 157. Every license can be used on different PCs, but only with the J-Link the license is for. This means that if you want to use flash breakpoints with other J-Links, every J-Link needs a license.

Device-based license

The device-based license comes with the J-Link software and is available for some devices. For a complete list of devices which have built-in licenses, please refer to Device list on page 50. The device-based license has to be activated via the debugger. How to activate a device-based license is described in detail in the section Acti- vating a device-based license on page 50.

2.3.1 Built-in license

This type of license is easiest to use. The customer does not need to deal with a license key. The software automatically finds out that the connected J-Link contains the built-in license(s). To check what licenses the used J-Link have, simply open the J-Link commander (JLink.exe). The J-Link commander finds and lists all of the JLink’s licenses automatically, as can be seen in the screenshot below.

This J-Link for example, has built-in licenses for RDI, J-Link ARM FlashDL and FlashBP.

2.3.2 Key-based license

When using a key-based license, a license key is required in order to enable the JLink flash breakpoint feature. License keys can be added via the license manager. How to enter a license via the license manager is described in Licensing on page 157. Like the built-in license, the key-based license is only valid for one J-Link, so if another J-Link is used it needs a separate license.

J-Link / J-Trace (UM08001) ©

2004-2012 SEGGER Microcontroller GmbH & Co. KG

Page 49

2.3.2.1 Entering a key-based license

The easiest way to enter a license is the following:

Open the J-Link control panel window, go to the General tab and choose License.

Now the J-Link license manager will open and show all licenses, both key-based and built-in licenses of J-Link.

Now choose Add license to add one or more new licenses. Enter your license(s) and choose OK. Now the licenses should have been added.

2.3.3 Device-based license

The device-based license is a free license, available for some devices. It’s already included in J-Link, so no keys are necessary to enable this license type. To activate a device based license, the debugger needs to select a supported device.

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50 CHAPTER 2 Licensing

2.3.3.1 Activating a device-based license

In order to activate a device-based license, the debugger needs to select a supported device. To check if the debugger has selected the right device, simply open the J-Link control panel and check the device section in the General tab.

2.3.3.2 Device list

The following list contains all devices which are supported by the device-based license

Manufacturer Name Licenses

NXP LPC2101

NXP LPC2102

NXP LPC2103

NXP LPC2104

NXP LPC2105

NXP LPC2106,

NXP LPC2109

NXP LPC2114

NXP LPC2119

NXP LPC2124

NXP LPC2129

NXP LPC2131

NXP LPC2132

NXP LPC2134

NXP LPC2136

Table 2.1: Device list

J-Link ARM FlashDL, J-Link ARM FlashBP

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Manufacturer Name Licenses

NXP LPC2138

NXP LPC2141

NXP LPC2142

NXP LPC2144

NXP LPC2146

NXP LPC2148

NXP LPC2194

NXP LPC2212

NXP LPC2214

NXP LPC2292

NXP LPC2294

NXP LPC2364

NXP LPC2366

NXP LPC2368

NXP LPC2378

NXP LPC2468

NXP LPC2478

Table 2.1: Device list

J-Link ARM FlashDL, J-Link ARM FlashBP

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52 CHAPTER 2 Licensing

2.4 Legal use of SEGGER J-Link software

The software consists of proprietary programs of SEGGER, protected under copyright and trade secret laws. All rights, title and interest in the software are and shall remain with SEGGER. For details, please refer to the license agreement which needs to be accepted when installing the software. The text of the license agreement is also available as entry in the start menu after installing the software.

Use of software

SEGGER J-Link software may only be used with original SEGGER products and authorized OEM products. The use of the licensed software to operate SEGGER product clones is prohibited and illegal.

2.4.1 Use of the software with 3rd party tools

For simplicity, some components of the J-Link software are also distributed from partners with software tools designed to use J-Link. These tools are primarily debugging tools, but also memory viewers, flash programming utilities but also software for other purposes. Distribution of the software components is legal for our partners, but the same rules as described above apply for their usage: They may only be used with original SEGGER products and authorized OEM products. The use of the licensed software to operate SEGGER product clones is prohibited and illegal.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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2.5 Original SEGGER products

The following products are original SEGGER products for which the use of the J-Link software is allowed:

2.5.1 J-Link

J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Link has a builtin 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM.

Licenses

Comes with built-in licenses for flash download and flash breakpoints for some devices. For a complete list of devices which are supported by the built-in licenses, please refer to Device list on page 50.

2.5.2 J-Link Ultra

J-Link Ultra is a JTAG/SWD emulator designed for ARM/Cortex and other supported CPUs. It is fully compatible to the standard J-Link and works with the same PC software. Based on the highly optimized and proven J-Link, it offers even higher speed as well as target power measurement capabilities due to the faster CPU, built-in FPGA and High speed USB interface. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Link Ultra has a built-in 20-pin JTAG/SWD connector.

Licenses

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54 CHAPTER 2 Licensing

2.5.3 J-Link Pro

J-Link Pro is a JTAG emulator designed for ARM cores. It connects via USB or Ethernet to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows

7. J-Link has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM.

Licenses

Comes with built-in licenses for all J-Link related software products: J-Link ARM FlashDL, FlashBP, RDI, J-Link GDB Server and J-Flash.

2.5.4 J-Trace

J-Trace is a JTAG emulator designed for ARM cores which includes trace (ETM) support. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Trace has a built-in 20-pin JTAG connector and a built in 38-pin JTAG+Trace connector, which is compatible with the standard 20-pin connector and 38-pin connector defined by ARM.

Licenses

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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2.5.5 J-Trace for Cortex-M

J-Trace for Cortex-M is a JTAG/SWD emulator designed for Cortex-M cores which include trace (ETM) support. J-Trace for Cortex-M can also be used as a regular J-Link and it also supports ARM7/9 cores. Please note that tracing on ARM7/9 targets is not supported by J-Trace for Cortex-M. In order to use ETM trace on ARM7/9 targets, a J-Trace is needed.

Licenses

2.5.6 Flasher ARM

Flasher ARM is a programming tool for microcontrollers with onchip or external Flash memory and ARM core. Flasher ARM is designed for programming flash targets with the J-Flash software or stand-alone. In addition to that Flasher ARM has all of the J- Link functionality. Flasher ARM connects via USB or via RS232 interface to a PC, running Microsoft Windows 2000, Windows XP, Windows 2003 or Windows Vista. Flasher ARM has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM.

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56 CHAPTER 2 Licensing

2.6 J-Link OEM versions

There are several different OEM versions of J-Link on the market. The OEM versions look different, but use basically identical hardware. Some of these OEM versions are limited in speed, some of these can only be used with certain chips and some of these have certain add-on features enabled, which normally requires license. In any case, it should be possible to use the J-Link software with these OEM versions. However, proper function cannot be guaranteed for OEM versions. SEGGER Microcontroller does not support OEM versions; support is provided by the respective OEM.

2.6.1 Analog Devices: mIDASLink

mIDASLink is an OEM version of J-Link, sold by Analog Devices.

Limitations

mIDASLink works with Analog Devices chips only. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link.

Licenses

Licenses for RDI, J-Link ARM FlashDL and FlashBP are included. Other licenses can be added.

2.6.2 Atmel: SAM-ICE

SAM-ICE is an OEM version of J-Link, sold by Atmel.

Limitations

SAM-ICE works with Atmel devices only. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link.

Licenses

Licenses for RDI and GDB Server are included. Other licenses can be added.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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2.6.3 Digi: JTAG Link

Digi JTAG Link is an OEM version of J-Link, sold by Digi International.

Limitations

Digi JTAG Link works with Digi devices only. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link.

Licenses

License for GDB Server is included. Other licenses can be added.

2.6.4 IAR: J-Link / J-Link KS

IAR J-Link / IAR J-Link KS are OEM versions of J-Link, sold by IAR.

Limitations

IAR J-Link / IAR J-Link KS can not be used with Keil MDK. This limitation can NOT be lifted; if you would like to use J-Link with Keil MDK, you need to buy a separate J-Link. IAR J-Link does not support kickstart power.

Licenses

No licenses are included. All licenses can be added.

2.6.5 IAR: J-Link Lite

IAR J-Link Lite is an OEM version of J-Link, sold by IAR.

Limitations

IAR J-Link Lite can not be used with Keil MDK. This limitation can NOT be lifted; if you would like to use J-Link with Keil MDK, you need to buy a separate J-Link.

JTAG speed is limited to 4 MHz.

Licenses

No licenses are included. All licenses can be added.

Note: IAR J-Link is only delivered and supported as part of Starter-Kits. It is not sold to end customer directly and not guaranteed to work with custom hardware.

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2.6.6 IAR: J-Trace

IAR J-Trace is an OEM version of J-Trace, sold by IAR.

Limitations

IAR J-Trace can not be used with Keil MDK. This limitation can NOT be lifted; if you would like to use J-Trace with Keil MDK, you need to buy a separate J-Trace.

Licenses

No licenses are included. All licenses can be added.

2.6.7 NXP: J-Link Lite LPC Edition

J-Link Lite LPC Edition is an OEM version of J-Link, sold by NXP.

Limitations

J-Link Lite LPC Edition only works with NXP devices. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link.

Licenses

No licenses are included.

2.6.8 SEGGER: J-Link Lite

J-Link ARM Lite is a fully functional OEM-version of SEGGER J-Link ARM. If you are selling evaluation-boards, J-Link ARM Lite is an inexpensive emulator solution for you. Your customer receives a widely acknowledged JTAG-emulator which allows him to start right away with his development.

Limitations

JTAG speed is limited to 4 MHz

Licenses

No licenses are included. All licenses can be added.

Note

J-Link ARM Lite is only delivered and supported as part of Starter Kits. It is not sold to end customer and not guaranteed to work with custom hardware.

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2.7 J-Link OBs

J-Link OBs (J-Link On Board) are single chip versions of J-Link which are used on various evalboards. It is legal to use J-Link software with these boards, provided that the eval board manufacturer has obtained a license from SEGGER. The following list shows the eval board manufacturer which are allowed to use J-Link OBs:

•IAR Systems

• Embedded Artists

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2.8 Illegal Clones

Clones are copies of SEGGER products which use the copyrighted SEGGER Firmware without a license. It is strictly prohibited to use SEGGER J-Link software with illegal clones of SEGGER products. Manufacturing and selling these clones is an illegal act for various reasons, amongst them trademark, copyright and unfair business practise issues.

The use of illegal J-Link clones with this software is a violation of US, European and other international laws and is prohibited.

If you are in doubt if your unit may be legally used with SEGGER J-Link software, please get in touch with us.

End users may be liable for illegal use of J-Link software with clones.

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Chapter 3

J-Link and J-Trace related software

This chapter describes Segger’s J-Link / J-Trace related software portfolio, which covers nearly all phases of the development of embedded applications. The support of the remote debug interface (RDI) and the J-Link GDBServer allows an easy J-Link integration in all relevant toolchains.

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3.1 J-Link related software

3.1.1 J-Link software and documentation package

J-Link is shipped with a bundle of applications. Some of the applications require an additional license, free trial licenses are available upon request from www.seg- ger.com.

Software Description

JLinkARM.dll DLL for using J-Link / J-Trace with third-party programs.

JLink.exe

JLinkSTR91x

JLinkSTM32

J-Link TCP/IP Server

J-Mem memory viewer

J-Flash

RDI support

Free command-line tool with basic functionality for target analysis.

Free command-line tool to configure the ST STR91x cores. For more information please refer to J-Link STR91x Commander (Command line tool) on page 65

Free command-line tool for STM32 devices. Can be used to disable the hardware watchdog and to unsecure STM32 devices (override read-protection).

Free utility which provides the possibility to use J-Link / J-Trace remotely via TCP/IP.

Free target memory viewer. Shows the memory content of a running target and allows editing as well.

Stand-alone flash programming application. Requires an additional license. For more information about J-Flash please refer to J-Flash ARM User’s Guide (UM08003).

Provides Remote Debug Interface (RDI) support. This allows the user to use J-Link with any RDI-compliant debugger. (Additional license required)

GUI-based configuration tool for J-Link. Allows configuration of

J-Link Configurator

J-Link GDB Server

J-Link GDB Server command line version

Dedicated flash programming utilities

Table 3.1: J-Link / J-Trace related software

USB identification as well as TCP/IP identification of J-Link. For more information about the J-Link Configurator, please refer to J-Link Configurator on page 89.

The J-Link GDB Server is a remote server for the GNU Debugger (GDB). For more information about J-Link GDB Server, please refer to J-Link GDB Server User’s Guide (UM08005).

Command line version of the J-Link GDB Server. Same functionality as the GUI version.

Free dedicated flash programming utilities for the following eval boards: Cogent CSB737, ST MB525, Toshiba TOPAS 910.

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3.1.2 List of additional software packages

The software packages listed below are available upon request from www.segger.com.

Software Description

JTAGLoad

J-Link Software Developer Kit (SDK)

J-Link Flash Software Developer Kit (SDK)

Table 3.2: J-Link / J-Trace additional software packages

Command line tool that opens an svf file and sends the data in it via J-Link / J-Trace to the target.

The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace.

An enhanced version of the JLinkARM.DLL, which contains additional API functions for flash programming.

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3.2 J-Link software and documentation package in detail

The J-Link / J-Trace software documentation package is supplied together with J-Link / J-Trace and may also be downloaded from www.segger.com.

3.2.1 J-Link Commander (Command line tool)

J-Link Commander (JLink.exe) is a tool that can be used for verifying proper installation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system. It permits some simple commands, such as memory dump, halt, step, go and ID-check, as well as some more in-depths analysis of the state of the ARM core and the ICE breaker module.

3.2.1.1 Using command script files

J-Link commander can also be used in script mode which allows the user to use JLink commander for batch processing and without user interaction. When using JLink commander in script mode, the path to a script file is passed to it. The syntax in the script file is the same as when using regular commands in J-Link commander (one line per command).

Example

JLink.exe C:\script.jlink

Contents of script.jlink:

r h exec device = STM32F103ZE loadbin C:\firmware.bin,0x08000000

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3.2.2 SWO Analyzer

SWO Analyzer (SWOAnalyzer.exe) is a tool that analyzes SWO output. Status and summary of the analysis are output to standard out, the details of the analysis are stored in a file.

Usage

SWOAnalyzer.exe <SWOfile>

This can be achieved by simply dragging the SWO output file created by the J-Link DLL onto the executable.

Creating an SWO output file

In order to create the SWO output file, which is th input file for the SWO Analyzer, the J-Link config file needs to be modified.

It should contain the following lines:

[SWO]

SWOLogFile="C:\TestSWO.dat"

3.2.3 J-Link STR91x Commander (Command line tool)

J-Link STR91x Commander (JLinkSTR91x.exe) is a tool that can be used to configure STR91x cores. It permits some STR9 specific commands like:

• Set the configuration register to boot from bank 0 or 1

• Erase flash sectors

• Read and write the OTP sector of the flash

• Write-protect single flash sectors by setting the sector protection bits

• Prevent flash from communicate via JTAG by setting the security bit

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All of the actions performed by the commands, excluding writing the OTP sector and erasing the flash, can be undone. This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall.

When starting the STR91x commander, a command sequence will be performed which brings MCU into Turbo Mode.

"While enabling the Turbo Mode, a dedicated test mode signal is set and controls the GPIOs in output. The IOs are maintained in this state until a next JTAG instruction is send." (ST Microelectronics)

Enabling Turbo Mode is necessary to guarantee proper function of all commands in the STR91x Commander.

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3.2.4 J-Link STM32 Commander (Command line tool)

J-Link STM32 Commander (JLinkSTM32.exe) is a free command line tool which can be used to disable the hardware watchdog of STM32 devices which can be activated by programming the option bytes. Moreover the J-Link STM32 Commander unsecures a read-protected STM32 device by re-programming the option bytes.

Note: Unprotecting a secured device or will cause a mass erase of the flash memory.

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3.2.5 J-Link TCP/IP Server (Remote J-Link / J-Trace use)

The J-Link TCP/IP Server allows using J-Link / J-Trace remotely via TCP/IP. This enables you to connect to and fully use a J-Link / J-Trace from another computer. Performance is just slightly (about 10%) lower than with direct USB connection.

The J-Link TCP/IP Server also accepts commands which are passed to the J-Link TCP/ IP Server via the command line.

3.2.5.1 List of available commands

The table below lists the commands accepted by the J-Link TCP/IP Server

Command Description

port

usb Selects a usb port for communication with J-Link.

Table 3.3: Available commands

Selects the IP port on which the J-Link TCP/IP Server is listening.

3.2.5.2 port

Syntax

-port <Portno.>

Example

To start the J-Link TCP/IP Server listening on port 19021 the command should look as follows:

-port 19021

3.2.5.3 usb

Syntax

-usb <USBIndex>

Example

Currently usb 0-3 are supported, so if the J-Link TCP/IP Server should connect to the J-Link on usb port 2 the command should look as follows:

-usb 2

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3.2.6 J-Mem Memory Viewer

J-Mem displays memory contents of ARM-systems and allows modifications of RAM and SFRs (Special Function Registers) while the target is running. This makes it possible to look into the memory of an ARM chip at run-time; RAM can be modified and SFRs can be written. You can choose between 8/16/32-bit size for read and write accesses. J-Mem works nicely when modifying SFRs, especially because it writes the SFR only after the complete value has been entered.

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3.2.7 J-Flash ARM (Program flash memory via JTAG)

J-Flash ARM is a software running on Windows 2000, Windows XP, Windows 2003 or Windows Vista systems and enables you to program your flash EEPROM devices via the JTAG connector on your target system.

J-Flash ARM works with any ARM7/9 system and supports all common external flashes, as well as the programming of internal flash of ARM microcontrollers. It allows you to erase, fill, program, blank check, upload flash content, and view memory functions of the software with your flash devices.

J-Flash requires a additional license from Segger. Even without a license key you can still use J-Flash ARM to open project files, read from connected devices, blank check target memory, verify data files and so on. However, to actually program devices via J-Flash ARM and J-Link / J-Trace you are required to obtain a license key from us. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.

Features

•Works with any ARM7/ARM9 chip

• ARM microcontrollers (internal flash) supported

• Most external flash chips can be programmed

• High-speed programming: up to 300 Kbytes/second (depends on flash device)

• Very high-speed blank check: Up to 16 Mbytes/sec (depends on target)

• Smart read-back: Only non-blank portions of flash transferred and saved

• Easy to use, comes with projects for standard eval boards.

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3.2.8 J-Link RDI (Remote Debug Interface)

The J-Link RDI software is an remote debug interface for J-Link. It makes it possible to use J-Link with any RDI compliant debugger. The main part of the software is an RDI-compliant DLL, which needs to be selected in the debugger. There are two additional features available which build on the RDI software foundation. Each additional features requires an RDI license in addition to its own license. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.

Note: The RDI software (as well as flash breakpoints and flash downloads) do not require a license if the target device is an LPC2xxx. In this case the software verifies that the target device is actually an LPC 2xxx and have a device-based license.

3.2.8.1 Flash download and flash breakpoints

Flash download and flash breakpoints are supported by J-Link RDI. For more information about flash download and flash breakpoints, please refer to J-Link RDI User’s Guide (UM08004), chapter Flash download and chapter Breakpoints in flash memory.

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3.2.9 J-Link GDB Server

GDB Server is a remote server for the GNU Debugger GDB. GDB and GDB Server communicate via a TCP/IP connection, using the standard GDB remote serial protocol. The GDB Server translates the GDB monitor commands into J-Link commands.

The GNU Project Debugger (GDB) is a freely available debugger, distributed under the terms of the GPL. It connects to an emulator via a TCP/IP connection. It can connect to every emulator for which a GDB Server software is available. The latest Unix version of the GDB is freely available from the GNU committee under:

http://www.gnu.org/software/gdb/download/

J-Link GDB Server is distributed free of charge.

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3.3 Dedicated flash programming utilities for J-Link

The SEGGER J-Link comes with dedicated flash programming utilities (DFPU) for a number of popular Eval boards. These utilities are designed to program a .bin file into the flash memory of the target hardware, with J-Link. Each dedicated flash programming utility works only with the Eval board it was designed for.

Data

File

USB

JTAG

J-Link

CPU

Target

Flash

Memory

3.3.1 Introduction

Using the dedicated flash programming utilities which come with J-Link, is permitted for development purposes only. As long as the dedicated flash programming tools are used for development purposes only, no additional license is required. If you want to use the dedicated flash programming utilities for commercial and production purposes, you need to obtain a license from SEGGER. SEGGER also offers to create dedicated flash programming utilities for custom hardware. When starting a dedicated flash programming utility, a message box appears which tells the user about the purpose of the dedicated flash programming utility:

3.3.2 Supported Eval boards

The list below shows the Eval boards for which dedicated flash programming utilities have been already developed. Simple flash programming utilities for other, popular Eval boards are on the schedule.

CPU / MCU

Atmel AT91SAM9263 Cogent CSB737

ST STM32F103RBT6

Tos hi ba TMPA910CRXBG

NXP LPC3250 Phytec PCM-967

Table 3.4:

Eval board

manufacturer

ST Microelectronics

Toshiba TOPAS910

Eval board

name

MB525

Flash memory

Typically 65 MB external NOR flash

Typically 128 KB internal flash

Typically 32 MB external NOR flash

Typically 32 MB external NAND flash (ST NAND256R3A)

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3.3.3 Supported flash memories

The dedicated flash programming utilities for J-Link can be created for the following flash memories:

• External NOR flash

• Internal flash

• NAND flash

• Data flash

• SPI flash

In order to use external NOR flash, a CFI compliant flash memory has to be used because the flash programming utilities use the CFI information to detect the flash size and sectorization.

3.3.4 How to use the dedicated flash programming utilities

The dedicated flash programming utilities are very simple to use. Every tool expects a path to a data file (*.bin) passed as a command line parameter, on startup. If no path is passed the flash programming utility searches for a data in the Samples\ directory. This .bin file has to be named as shown in the table above. For example, for the Cogent CSB737 Eval board this file is named: CogentCSB737.bin.

3.3.5 Using the dedicated flash programming utilities for pro-

duction and commercial purposes

If you want to use dedicated flash programming utilities for production and commercial purposes you need to obtain a license from SEGGER. In order to obtain a license for a dedicated flash programming utility, there are two options:

• Purchasing the source code of an existing dedicated flash programming utility

• Purchasing the source code of a dedicated flash programming utility for custom hardware

The source code can be compiled using a Microsoft Visual C++ V6 or newer compiler. It contains code which is executed on the target device (RAMCODE). This RAMCODE may not be used with debug probes other than J-Link.

3.3.5.1 Purchasing the source code of an existing dedicated flash programming utility

Purchasing the source code of an existing dedicated flash programming utility (described above) allows you to use the dedicated flash programming utility for production and commercial purposes. Making the resulting executable publicly available is not permitted.

For more information about the pricing for the source code of existing dedicated flash programming utilities, please refer to the price list on our website http://www.segger.com/pricelist_jlink.html#8.20.01.

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3.3.5.2 Purchasing the source code of a dedicated flash programming utility for custom hardware

SEGGER also offers to design dedicated flash programming utilities for custom hardware for which you will also need to obtain a license. The resulting executable may be used for organization internal purposes only.

3.3.6 F.A.Q.

Q: Q: Can the dedicated flash programming utilities be used for commercial pur-

poses?

A: A: Yes, you can buy the source code of one or more of the flash programming util-

ities which makes it possible to use them for commercial and production purposes.

Q: Q: I want to use the dedicated flash programming utilities with my own hardware.

Is that possible?

A: A: The free dedicated flash programming utilities which come with J-Link do not

support custom hardware.mIn order to use your own hardware with a dedicated flash programming utility, SEGGER offers to create dedicated flash programming utilities for custom hardware

Q: Q: Do I need a license to use the dedicated flash programming utilities? A: A: As long as you use the dedicated flash programming utilities, which come with

J-Link, for development purposes only, you do not need an additional license. In order to use them for commercial and/or production purposes you need to obtain a license from SEGGER.

Q: Q: Which file types are supported by the dedicated flash programming utilities? A: A: Currently, the dedicated flash programming utilities support *.bin files.

Q: Q: Can I use the dedicated flash programming utilities with other debug probes

than J-Link?

A: A: No, the dedicated flash programming utilities only work with J-Link

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3.4 Additional software packages in detail

The packages described in this section are not available for download. If you wish to use one of them, contact SEGGER Microcontroller Systeme directly.

3.4.1 JTAGLoad (Command line tool)

JTAGLoad is a tool that can be used to open an svf (Serial vector format) file. The data in the file will be sent to the target via J-Link / J-Trace.

3.4.2 J-Link Software Developer Kit (SDK)

The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace. The J-Link DLL is a standard Windows DLL typically used from C programs (Visual Basic or Delphi projects are also possible). It makes the entire functionality of J-Link / J-Trace available through its exported functions, such as halting/stepping the ARM core, reading/writing CPU and ICE registers and reading/writing memory. Therefore it can be used in any kind of application accessing an ARM core. The standard DLL does not have API functions for flash programming. However, the functionality offered can be used to program flash. In this case, a flash loader is required. The table below lists some of the included files and their respective purpose.

Files Contents

GLOBAL.h JLinkARMDLL.h

JLinkARM.lib A Library that contains the exports of the JLink DLL. JLinkARM.dll The DLL itself. Main.c Sample application, which calls some JLinkARM DLL functions. JLink.dsp

JLink.dsw JLinkARMDLL.pdf Extensive documentation (API, sample projects etc.).

Table 3.5: J-Link SDK

Header files that must be included to use the DLL functions. These files contain the defines, typedef names, and function declarations.

Project files of the sample application. Double click JLink.dsw to open the project.

3.4.3 J-Link Flash Software Developer Kit (SDK)

This is an enhanced version of the JLinkARM.DLL which contains additional API functions for flash programming. The additional API functions (prefixed JLINKARM_FLASH_) allow erasing and programming of flash memory. This DLL comes with a sample executable, as well as with source code of this executable and a Microsoft Visual C/C++ project file. It can be an interesting option if you want to write your own programs for production purposes.

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3.5 Using the J-LinkARM.dll

3.5.1 What is the JLinkARM.dll?

The J-LinkARM.dll is a standard Windows DLL typically used from C or C++, but also Visual Basic or Delphi projects. It makes the entire functionality of the J-Link / JTrace available through the exported functions.

The functionality includes things such as halting/stepping the ARM core, reading/ writing CPU and ICE registers and reading/writing memory. Therefore, it can be used in any kind of application accessing an ARM core.

3.5.2 Updating the DLL in third-party programs

The JLinkARM.dll can be used by any debugger that is designed to work with it. Some

debuggers, like the IAR C-SPY already installed. Anyhow it may make sense to replace the included DLL with the latest one available, to take advantage of improvements in the newer version.

3.5.2.1 Updating the JLinkARM.dll in the IAR Embedded Workbench for ARM (EWARM)

debugger, are usually shipped with the JLinkARM.dll

It’s recommended to use the J-Link DLL updater to update the JLinkARM.dll in the IAR Embedded Workbench. The IAR Embedded Workbench IDE is a high-performance integrated development environment with an editor, compiler, linker, debugger. The compiler generates very efficient code and is widely used. It comes with the J- LinkARM.dll in the arm\bin subdirectory of the installation directory. To update this DLL, you should backup your original DLL and then replace it with the new one.

Typically, the DLL is located in C:\Program Files\IAR Systems\Embedded Work- bench 6.n\arm\bin\.

After updating the DLL, it is recommended to verify that the new DLL is loaded as described in Determining which DLL is used by a program on page 78.

J-Link DLL updater

The J-Link DLL updater is a tool which comes with the J-Link software and allows the user to update the JLinkARM.dll in all installations of the IAR Embedded Workbench, in a simple way. The updater is automatically started after the installation of a J-Link software version and asks for updating old DLLs used by IAR. The J-Link DLL updater can also be started manually. Simply enable the checkbox left to the IAR installation which has been found. Click Ok in order to update the JLinkARM.dll used by the IAR installation.

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3.5.3 Determining the version of JLinkARM.dll

To determine which version of the JLinkARM.dll you are facing, the DLL version can be viewed by right clicking the DLL in explorer and choosing Properties from the context menu. Click the Version tab to display information about the product version.

3.5.4 Determining which DLL is used by a program

To verify that the program you are working with is using the DLL you expect it to use, you can investigate which DLLs are loaded by your program with tools like Sysinternals’ Process Explorer. It shows you details about the DLLs, used by your program, such as manufacturer and version.

Process Explorer is - at the time of writing - a free utility which can be downloaded from www.sysinternals.com.

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Chapter 4

Setup

This chapter describes the setup procedure required in order to work with J-Link / JTrace. Primarily this includes the installation of the J-Link software and documentation package, which also includes a kernel mode J-Link USB driver in your host system.

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4.1 Installing the J-Link ARM software and documentation pack

J-Link is shipped with a bundle of applications, corresponding manuals and some example projects and the kernel mode J-Link USB driver. Some of the applications require an additional license, free trial licenses are available upon request from www.segger.com.

Refer to chapter J-Link and J-Trace related software on page 61 for an overview about the J-Link software and documentation pack.

4.1.1 Setup procedure

To install the J-Link ARM software and documentation pack, follow this procedure:

Note: We recommend to check if a newer version of the J-Link software and documentation pack is available for download before starting the installation. Check therefore the J-Link related download section of our website:

http://www.segger.com/download_jlink.html

1. Before you plug your J-Link / J-Trace into your computer's USB port, extract the setup tool Setup_JLinkARM_V<VersionNumber>.zip. The setup wizard will install the software and documentation pack that also includes the certified JLink USB driver. Start the setup by double clicking Setup_JLinkARM_V<Version- Number>.exe. The license Agreement dialog box will be opened. Accept the terms with the Yes button.

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2. The Welcome dialog box is opened. Click Next > to open the Choose Destination Location dialog box.

3. Accept the default installation path C:\Program Files\SEGGER\JLinkARM_V<VersionNumber> or choose an alternative location. Confirm

your choice with the Next > button.

4. The Choose options dialog is opened. The Create entry in start menu and the Add shortcuts to desktop option are preselected. Accept or deselect the options and confirm the selection with the Next > button.

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5. The installation process will be started.

6. The Installation Complete dialog box appears after the copy process. Close the installation wizard with the Finish > button.

The J-Link software and documentation pack is successfully installed on your PC.

7. Connect your J-Link via USB with your PC. The J-Link will be identified and after a short period the J-Link LED stops rapidly flashing and stays on permanently.

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4.2 Setting up the USB interface

After installing the J-Link ARM software and documentation package it should not be necessary to perform any additional setup sequences in order to configure the USB interface of J-Link.

4.2.1 Verifying correct driver installation

To verify the correct installation of the driver, disconnect and reconnect J-Link / JTrace to the USB port. During the enumeration process which takes about 2 seconds, the LED on J-Link / J-Trace is flashing. After successful enumeration, the LED stays on permanently.

Start the provided sample application JLink.exe, which should display the compilation time of the J-Link firmware, the serial number, a target voltage of 0.000V, a complementary error message, which says that the supply voltage is too low if no target is connected to J-Link / J-Trace, and the speed selection. The screenshot below shows an example.

In addition you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your computer, the device manager should list the J-Link USB driver as a node below "Universal Serial Bus controllers" as shown in the following screenshot:

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Right-click on the driver to open a context menu which contains the command Properties. If you select this command, a J-Link driver Properties dialog box is opened

and should report: This device is working properly.

If you experience problems, refer to the chapter Support and FAQs on page 259 for help. You can select the Driver tab for detailed information about driver provider, version, date and digital signer.

4.2.2 Uninstalling the J-Link USB driver

If J-Link / J-Trace is not properly recognized by Windows and therefore does not enumerate, it makes sense to uninstall the J-Link USB driver.

This might be the case when:

• The LED on the J-Link / J-Trace is rapidly flashing.

• The J-Link / J-Trace is recognized as Unknown Device by Windows.

To have a clean system and help Windows to reinstall the J-Link driver, follow this procedure:

1. Disconnect J-Link / J-Trace from your PC.

2. Open the Add/Remove Programs dialog (Start > Settings > Control Panel > Add/Remove Programs) and select Windows Driver Package - Segger

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(jlink) USB and click the Change/Remove button.

3. Confirm the uninstallation process.

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4.3 Setting up the IP interface

Some emulators of the J-Link family have (or future members will have) an additional Ethernet interface, to communicate with the host system. These emulators will also come with a built-in web server which allows configuration of the emulator via web interface. In addition to that, you can set a default gateway for the emulator which allows using it even in large intranets. For simplicity the setup process of J-Link Pro (referred to as J-Link) is described in this section.

4.3.1 Configuring J-Link using J-Link Configurator

The J-Link software and documentation package comes with a free GUI-based utility called J-Link Configurator which auto-detects all J-Links that are connected to the host PC via USB & Ethernet. The J-Link Configurator allows the user to setup the IP interface of J-Link. For more information about how to use the J-Link Configurator, please refer to J-Link Configurator on page 89.

4.3.2 Configuring J-Link using the webinterface

All emulators of the J-Link family which come with an Ethernet interface also come with a built-in web server, which provides a web interface for configuration. This enables the user to configure J-Link without additional tools, just with a simple web browser. The Home page of the web interface shows the serial number, the current IP address and the MAC address of the J-Link.

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The Network configuration page allows configuration of network related settings (IP address, subnet mask, default gateway) of J-Link. The user can choose between automatic IP assignment (settings are provided by a DHCP server in the network) and manual IP assignment by selecting the appropriate radio button.

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4.4 FAQs

Q: How can I use J-Link with GDB and Ethernet? A: You have to use the J-Link GDB Server in order to connect to J-Link via GDB and

Ethernet.

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4.5 J-Link Configurator

Normally, no configuration is required, especially when using J-Link via USB. For special cases like: having multiple older J-Links connected to the same host PC in parallel, they need to be re-configured to be identified by their real serial number when enumerating on the host PC. This is the default identification method for current JLinks (J-Link with hardware version 8 or later). For re-configuration of old J-Links or for configuration of the IP settings (use DHCP, IP address, subnet mask, ...) of a JLink supporting the Ethernet interface, SEGGER provides a GUI-based tool, called JLink Configurator. The J-Link Configurator is part of the J-Link software and documentation package and can be used free of charge.

4.5.1 Configure J-Links using the J-Link Configurator

A J-Link can be easily configured by selecting the appropriate J-Link from the emulator list and using right click -> Configure.

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In order to configure a J-Link to use the new USB identification method (reporting the real serial number) simply select "Real SN" as USB identification method and click the OK button. The same dialog also allows configuration of the IP settings of the connected J-Link if it supports the Ethernet interface.

Note: When re-configuring older J-Links which use the old enumeration method (USB identification: USB 0 - USB 3) you can only have 1 J-Link connected which uses the old method at the same time. So re-configuration has to be done one at a time.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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4.6 J-Link USB identification

In general, when using USB, there are two ways in which a J-Link can be identified:

•By serial number

• By USB address

Default configuration of J-Link is: Identification by serial number. Identification via USB address is used for compatibility and not recommended.

Background information

"USB address" really means changing the USB-Product Id (PID).

The following table shows how J-Links enumerate in the different identification modes.

Identification PID Serial number

Serial number (default) 0x0101

USB address 0 (Deprecated) 0x0101 123456 USB address 1 (Deprecated) 0x0102 123456 USB address 2 (Deprecated) 0x0103 123456 USB address 3 (Deprecated) 0x0104 123456

Table 4.1: J-Link enumeration in different identification modes

Serial number is real serial number of the J-Link or user assigned.

4.6.1 Connecting to different J-Links connected to the same host PC via USB

In general, when having multiple J-Links connected to the same PC, the J-Link to connect to is explicitly selected by its serial number. Most software/debuggers provide an extra field to type-in the serial number of the J-Link to connect to:

The following screenshot shows the connection dialog of the J-Flash software:

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The following screenshot shows the connection dialog of IAR EWARM:

For debuggers / software which does not provide such a functionality, the J-Link DLL automatically detects that mutliple J-Links are connected to the PC and shows a selection dialog which allows the user to select the appropriate J-Link he wants to connect to.

So even in IDEs which do not have an selection option for the J-Link, it is possible to connect to different J-Links.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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Chapter 5

Working with J-Link and J-Trace

This chapter describes functionality and how to use J-Link and J-Trace.

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5.1 Connecting the target system

5.1.1 Power-on sequence

In general, J-Link / J-Trace should be powered on before connecting it with the target device. That means you should first connect J-Link / J-Trace with the host system via USB and then connect J-Link / J-Trace with the target device via JTAG. Power-on the device after you connected J-Link / J-Trace to it.

5.1.2 Verifying target device connection

If the USB driver is working properly and your J-Link / J-Trace is connected with the host system, you may connect J-Link / J-Trace to your target hardware. Then start JLink.exe which should now display the normal J-Link / J-Trace related information and in addition to that it should report that it found a JTAG target and the target’s core ID. The screenshot below shows the output of JLink.exe. As can be seen, it reports a J-Link with one JTAG device connected.

5.1.3 Problems

If you experience problems with any of the steps described above, read the chapter Support and FAQs on page 259 for troubleshooting tips. If you still do not find appropriate help there and your J-Link / J-Trace is an original SEGGER product, you can contact SEGGER support via e-mail. Provide the necessary information about your target processor, board etc. and we will try to solve your problem. A checklist of the required information together with the contact information can be found in chapter Support and FAQs on page 259 as well.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

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5.2 Indicators

J-Link uses indicators (LEDs) to give the user some information about the current status of the connected J-Link. All J-Links feature the main indicator. Some newer JLinks such as the J-Link Pro / Ultra come with additional input/output Indicators. In the following, the meaning of these indicators will be explained.

5.2.1 Main indicator

For J-Links up to V7, the main indicator is single color (Green). J-Link V8 comes with a bi-color indicator (Green & Red LED), which can show multiple colors: green, red and orange.

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5.2.1.1 Single color indicator (J-Link V7 and earlier)

Indicator status Meaning

GREEN, flashing at 10 Hz Emulator enumerates.

Emulator is in operation. Whenever the emulator is executing a command, the LED is switched off temporarily.

GREEN, flickering

GREEN, constant Emulator has enumerated and is in Idle mode.

Flickering speed depends on target interface speed. At low interface speeds, operations typically take longer and the "OFF" periods are typically longer than at fast speeds.

GREEN, switched off for 10ms once per second

GREEN, flashing at 1 Hz

Table 5.1: J-Link single color main indicator

J-Link heart beat. Will be activated after the emulator has been in idle mode for at least 7 seconds.

Emulator has a fatal error. This should not normally happen.

5.2.1.2 Bi-color indicator (J-Link V8)

Indicator status Meaning

GREEN, flashing at 10 Hz Emulator enumerates.

Emulator is in operation. Whenever the emulator is executing a command, the LED is switched off temporarily.

GREEN, flickering

GREEN, constant Emulator has enumerated and is in Idle mode.

Flickering speed depends on target interface speed. At low interface speeds, operations typically take longer and the "OFF" periods are typically longer than at fast speeds.

GREEN, switched off for 10ms once per second

ORANGE Reset is active on target.

RED, flashing at 1 Hz

Table 5.2: J-Link single color LED main color indicator

J-Link heart beat. Will be activated after the emulator has been in idle mode for at least 7 seconds.

Emulator has a fatal error. This should not normally happen.

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5.2.2 Input indicator

Some newer J-Links such as the J-Link Pro/Ultra come with additional input/output Indicators. The input indicator is used to give the user some information about the status of the target hardware.

5.2.2.1 Bi-color input indicator

Indicator status Meaning

GREEN Target voltage could be measured. Target is connected.

ORANGE

RED

Table 5.3: J-Link bi-color input indicator

Target voltage could be measured. RESET is pulled low (active) on target side.

RESET is pulled low (active) on target side. If no target is connected, reset will be also active on target side.

5.2.3 Output indicator

Some newer J-Links such as the J-Link Pro/Ultra come with additional input/output Indicators. The output indicator is used to give the user some information about the emulator-to-target connection.

5.2.3.1 Bi-color output indicator

Indicator status Meaning

OFF Target power supply via Pin 19 is not active.

GREEN Target power supply via Pin 19 is active.

ORANGE

Target power supply via Pin 19 is active. Emulator pulls RESET low (active).

RED Emulator pulls RESET low (active).

Table 5.4: J-Link bi-color output indicator

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5.3 JTAG interface

By default, only one ARM device is assumed to be in the JTAG scan chain. If you have multiple devices in the scan chain, you must properly configure it. To do so, you have to specify the exact position of the ARM device that should be addressed. Configuration of the scan is done by the target application. A target application can be a debugger such as the IAR C-SPY® debugger, ARM’s AXD using RDI, a flash programming application such as SEGGER’s J-Flash, or any other application using J-Link / J-Trace. It is the application’s responsibility to supply a way to configure the scan chain. Most applications offer a dialog box for this purpose.

5.3.1 Multiple devices in the scan chain

J-Link / J-Trace can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the following figure, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus.

Device 1 Device 0

TDI TDITDO TDO

TMS

TRST

TCK

TMS

TDI

TRST

TMS

TRST

TCK

TDO

JTAG

Currently, up to 8 devices in the scan chain are supported. One or more of these devices can be ARM cores; the other devices can be of any other type but need to comply with the JTAG standard.

5.3.1.1 Configuration

The configuration of the scan chain depends on the application used. Read JTAG interface on page 98 for further instructions and configuration examples.

5.3.2 Sample configuration dialog boxes

As explained before, it is responsibility of the application to allow the user to configure the scan chain. This is typically done in a dialog box; some sample dialog boxes are shown below.

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SEGGER J-Flash configuration dialog

This dialog box can be found at Options|Project settings.

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SEGGER J-Link RDI configuration dialog box

This dialog can be found under RDI|Configure for example in IAR Embedded Workbench®. For detailed information check the IAR Embedded Workbench user guide.

IAR J-Link configuration dialog box

This dialog box can be found under Project|Options.

2004-2012 SEGGER Microcontroller GmbH & Co. KG

Segger J-Link Series, J-Trace Series, J-Link ARM, J-Trace for Cortex-M, J-Trace ARM User Manual

About this document

Table of Contents

Introduction

1.1 Requirements

1.2 Supported OS

1.3 J-Link / J-Trace models

1.3.1 Model comparison

1.3.2 J-Link ARM

1.3.3 J-Link Ultra

1.3.4 J-Link ARM Pro

1.3.5 J-Link ARM Lite

1.3.6 J-Link Lite Cortex-M

1.3.7 J-Trace ARM

1.3.8 J-Trace for Cortex-M

1.3.9 Flasher ARM

1.3.10 J-Link ColdFire

1.4 Common features of the J-Link product family

1.5 Supported CPU cores

1.6 Built-in intelligence for supported CPU-cores

1.6.1 Intelligence in the J-Link firmware

1.6.2 Intelligence on the PC-side (DLL)

1.6.3 Firmware intelligence per model

1.7 Supported IDEs

Licensing

2.1 Introduction

2.2 Software components requiring a license

2.3 License types

2.3.1 Built-in license

2.3.2 Key-based license

2.3.3 Device-based license

2.4 Legal use of SEGGER J-Link software

2.4.1 Use of the software with 3rd party tools

2.5 Original SEGGER products

2.5.1 J-Link

2.5.2 J-Link Ultra

2.5.3 J-Link Pro

2.5.4 J-Trace

2.5.5 J-Trace for Cortex-M

2.5.6 Flasher ARM

2.6 J-Link OEM versions

2.6.1 Analog Devices: mIDASLink

2.6.2 Atmel: SAM-ICE

2.6.3 Digi: JTAG Link

2.6.4 IAR: J-Link / J-Link KS

2.6.5 IAR: J-Link Lite

2.6.6 IAR: J-Trace

2.6.7 NXP: J-Link Lite LPC Edition

2.6.8 SEGGER: J-Link Lite

2.7 J-Link OBs

2.8 Illegal Clones

3.1 J-Link related software

3.1.1 J-Link software and documentation package

3.1.2 List of additional software packages

3.2 J-Link software and documentation package in detail

3.2.1 J-Link Commander (Command line tool)

3.2.2 SWO Analyzer

3.2.3 J-Link STR91x Commander (Command line tool)

3.2.4 J-Link STM32 Commander (Command line tool)

3.2.5 J-Link TCP/IP Server (Remote J-Link / J-Trace use)

3.2.6 J-Mem Memory Viewer

3.2.7 J-Flash ARM (Program flash memory via JTAG)

3.2.8 J-Link RDI (Remote Debug Interface)

3.2.9 J-Link GDB Server

3.3 Dedicated flash programming utilities for J-Link

3.3.1 Introduction

3.3.2 Supported Eval boards

3.3.3 Supported flash memories

3.3.4 How to use the dedicated flash programming utilities

3.3.6 F.A.Q.

3.4 Additional software packages in detail

3.4.1 JTAGLoad (Command line tool)

3.4.2 J-Link Software Developer Kit (SDK)

3.4.3 J-Link Flash Software Developer Kit (SDK)

3.5 Using the J-LinkARM.dll

3.5.1 What is the JLinkARM.dll?

3.5.2 Updating the DLL in third-party programs

3.5.3 Determining the version of JLinkARM.dll

3.5.4 Determining which DLL is used by a program

Setup