Segger J-Link, J-Trace User Manual

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A product of SEGGER Microcontroller GmbH & Co. KG

J-Link / J-Trace

User Guide

JTAG Emulators for

ARM Cores

Release date: 07-12-04

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Disclaimer

Specifications written in this document are believed to be accurate, but are not guaranteed to be entirely free of error. The information in this manual is subject to change for functional or performance improvements without notice. Please make sure your manual is the latest edition. While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no responsibility for any errors or omissions. The manufacturer makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you. The manufacturer specifically disclaims any implied warranty of merchantability or fitness for a particular purpose.

You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of the manufacturer. The software described in this document is furnished under a license and may only be used or copied in accordance with the terms of such a license.

Trademarks

Names mentioned in this manual may be trademarks of their respective companies.

Brand and product names are trademarks or registered trademarks of their respective holders.

Contact address

SEGGER Microcontroller GmbH & Co. KG

Heinrich-Hertz-Str. 5 D-40721 Hilden

Germany

Tel.+49 2103-2878-0 Fax.+49 2103-2878-28 Email: support@segger.com Internet: http://www.segger.com

Revisions

This manual describes the J-Link and J-Trace device.

For further information on topics or routines not yet specified, please contact us.

Revision Date By Explanation

29 070912 SK

Chapter "Hardware", section "Target board design" updated.

28 070912 SK

Chapter "Related software": Section "J-LinkSTR91x Commander" added. Chapter "Device specifics": Section "ST Microelectronics" added. Section "Texas Instruments" added. Subsection "AT91SAM9" added.

28 070912 AG

Chapter "Working with J-Link/J-Trace": Section "Command strings" updated.

27 070827 TQ

Chapter "Working with J-Link/J-Trace": Section "Command strings" updated.

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26 070710 SK

Chapter "Introduction": Section "Features of J-Link" updated. Chapter "Background Information": Section "Embedded Trace Macrocell" added. Section "Embedded Trace Buffer" added.

25 070516 SK

Chapter "Working with J-Link/J-Trace": Section "Reset strategies in detail"

- "Software, for Analog Devices ADuC7xxx MCUs" updated

- "Software, for ATMEL AT91SAM7 MCUs" added. Chapter "Device specifics" Section "Analog Devices" added. Section "ATMEL" added.

24 070323 SK

Chapter "Setup": "Uninstalling the J-Link driver" updated. "Supported ARM cores" updated.

23 070320 SK

Chapter "Hardware": "Using the JTAG connector with SWD" updated.

22 070316 SK

Chapter "Hardware": "Using the JTAG connector with SWD" added.

21 070312 SK

Chapter "Hardware": "Differences between different versions" supplemented.

20 070307 SK

Chapter "J-Link / J-Trace related software": "J-Link GDB Server" licensing updated.

19 070226 SK

Chapter "J-Link / J-Trace related software" updated and reorganized. Chapter "Hardware" "List of OEM products" updated

18 070221 SK

Chapter "Device specifics" added Subchapter "Command strings" added

17 070131 SK

Chapter "Hardware": "Version 5.3": Current limits added "Version 5.4" added Chapter "Setup": "Installating the J-Link USB driver" removed. "Installing the J-Link software and documentation pack" added. Subchapter "List of OEM products" updated. "OS support" updated

16 061222 SK

Chapter "Preface": "Company description" added. J-Link picture changed.

15 060914 OO

Subchapter 1.5.1: Added target supply voltage and target supply current to specifications. Subchapter 5.2.1: Pictures of ways to connect JTrac e .

14 060818 TQ

Subchapter 4.7 "Using DCC for memory reads" added.

13 060711 OO

Subchapter 5.2.2: Corrected JTAG+Trace connector pinout table.

12 060628 OO

Subchapter 4.1: Added ARM966E-S to List of supported ARM cores.

11 060607 SK

Subchapter 5.5.2.2 changed. Subchapter 5.5.2.3 added.

Revision Date By Explanation

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10 060526 SK

ARM9 download speed updated. Subchapter 8.2.1: Screenshot "Start sequence" updated. Subchapter 8.2.2 "ID sequence" removed. Chapter "Support" and "FAQ" merged. Various improveme nts

9 060324 OO

Chapter "Literature and references" added. Chapter "Hardware": Added common information trace signals. Added timing diagram for trace. Chapter "Designing the target board for trace" added.

8 060117 OO

Chapter "Related Software": Added JLinkARM.dll. Screenshots updated.

7 051208 OO Chapter Working with J-Link: Sketch added.

6 051118 OO

Chapter Working with J-Link: "Connecting multiple J-Links to your PC" added. Chapter Working with J-Link: "Multi core debugging" added. Chapter Background information: "J-Link firmware" added.

5 051103 TQ Chapter Setup: "JTAG Speed" added.

4 051025 OO

Chapter Background information: "Flash programming" added. Chapter Setup: "Scan chain configuration" added.

Some smaller changes. 3 051021 TQ Performance values updated. 2 051011 TQ Chapter "Working with J-Link" added. 1 050818 TW Initial version.

Revision Date By Explanation

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About this document

This document describes J-Link and J-Trace. It provides an overview over the major features of J-Link and J-Trace, gives you some background information about JTAG, ARM and Tracing in general and describes J-Link and J-Trace related software packages available from Segger. Finally, the chapter Support and FAQs on page 107 helps to troubleshoot common problems.

For simplicity, we will refer to J-Link ARM as J-Link in this manual.

Typographic conventions

This manual uses the following typographic conventions:

Style Used for

Body Body text.

Keyword

Text that you enter at the command-prompt or that appears on the display (that is system functions, file- or pathnames).

Reference Reference to chapters, tables and figures or other documents.

GUIElement Buttons, dialog boxes, menu names, menu commands.

Table 1.1: Typographic conventions

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J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

EMBEDDED SOFTWARE (Middleware)

emWin

Graphics software and GUI

emWin is designed to provide an efficient, processor- and display controller-independent graphical user interface (GUI) for any application that operates with a graphical display. Starterkits, eval- and trial-versions are available.

embOS

Real Time Operating System

embOS is an RTOS designed to offer the benefits of a complete multitasking system for hard real time applications with minimal resources. The profiling PC tool embOSView is included.

emFile

File system

emFile is an embedded file system with FAT12, FAT16 and FAT32 support. emFile has been optimized for minimum memory consumption in RAM and ROM while maintaining high speed. Various Device drivers, e.g. for NAND and NOR flashes, SD/MMC and CompactFlash cards, are available.

emUSB

USB device stack

A USB stack designed to work on any embedded system with a USB client controller. Bulk communication and most standard device classes are supported.

SEGGER TOOLS

Flasher

Flash programmer

Flash Programming tool primarily for microcontrollers.

J-Link

JTAG emulator for ARM cores

USB driven JTAG interface for ARM cores.

J-Trace

JTAG emulator with trace

USB driven JTAG interface for ARM cores with Trace memory. supporting the ARM ETM (Embedded Trace Macrocell).

J-Link / J-Trace Related Software

Add-on software to be used with SEGGER’s industry standard JTAG emulator, this includes flash programming software and flash breakpoints.

SEGGER Microcontroller GmbH & Co. KG develops and distributes software development tools and ANSI C software components (middleware) for embedded systems in several industries such as telecom, medical technology, consumer electronics, automotive industry and industrial automation.

SEGGER’s intention is to cut software developmenttime for embedded applications by offering compact flexible and easy to use middleware, allowing developers to concentrate on their application.

Our most popular products are emWin, a universal graphic software package for embedded applications, and embOS, a small yet efficent real-time kernel. emWin, written entirely in ANSI C, can easily be used on any CPU and most any display. It is complemented by the available PC tools: Bitmap Converter, Font Converter, Simulator and Viewer. embOS supports most 8/16/32-bit CPUs. Its small memory footprint makes it suitable for single-chip applications.

Apart from its main focus on software tools, SEGGER developes and produces programming tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in development, debugging and production, which has rapidly become the industry standard for debug access to ARM cores.

Corporate Office:

http://www.segger.com

United States Office:

http://www.segger-us.com

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1 Introduction....................................................................................................................11

1.1 J-Link overview .......................................................................................12

1.1.1 Features of J-Link ....................................................................................12

1.2 J-Trace overview .....................................................................................13

1.2.1 Features of J-Trace ..................................................................................13

1.2.2 Test environment ....................................................................................14

1.3 Specifications..........................................................................................15

1.3.1 Specifications for J-Link............................................................................15

1.3.2 Specifications for J-Trace ..........................................................................15

1.3.3 Download speed ......................................................................................16

1.4 Requirements..........................................................................................17

2 Setup..............................................................................................................................19

2.1 Installing the J-Link ARM software and documen-tation pack .........................20

2.1.1 Setup procedure......................................................................................21

2.1.2 Verifying correct driver installation.............................................................24

2.2 Uninstalling the J-Link USB driver .............................................................. 26

2.3 Connecting the target system....................................................................27

2.3.1 Power-on sequence..................................................................................27

2.3.2 Verifying target device connection .............................................................27

2.3.3 Problems ................................................................................................27

2.4 Scan chain configuration...........................................................................28

2.4.1 Sample configuration dialog boxes .............................................................28

2.4.2 Determining values for scan chain configuration...........................................30

2.5 JTAG Speed ............................................................................................31

2.5.1 Fixed JTAG speed ....................................................................................31

2.5.2 Automatic JTAG speed..............................................................................31

2.5.3 Adaptive clocking.....................................................................................31

3 J-Link and J-Trace related software...............................................................................33

3.1 J-Link related software .............................................................................34

3.1.1 J-Link software and documentation package................................................34

3.1.2 List of additional software packages ........................................................... 34

3.2 J-Link software and documentation package in

detail .....................................................................................................35

3.2.1 J-Link Commander (Command line tool) .....................................................35

3.2.2 J-Link STR9 Commander (Command line tool) .............................................35

3.2.3 J-Link TCP/IP Server (Remote J-Link / J-Trace use)...................................... 36

3.2.4 J-Mem Memory Viewer .............................................................................36

3.2.5 J-Flash ARM (Program flash memory via JTAG)............................................37

3.2.6 J-Link RDI (Remote Debug Interface) .........................................................38

3.2.7 J-Link GDB Server ...................................................................................40

3.3 Additional software packages in detail ........................................................ 41

3.3.1 JTAGLoad (Command line tool).................................................................. 41

3.3.2 J-Link Software Developer Kit (SDK) ..........................................................41

3.3.3 J-Link Flash Software Developer Kit (SDK) ..................................................41

3.4 Using the J-LinkARM.dll ............................................................................42

3.4.1 What is the JLinkARM.dll? .........................................................................42

3.4.2 Updating the DLL in third-party programs ................................................... 42

3.4.3 Determining the version of JLinkARM.dll .....................................................42

Table of Contents

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3.4.4 Determining which DLL is used by a program .............................................. 43

4 Working with J-Link and J-Trace....................................................................................45

4.1 Supported ARM Cores .............................................................................. 46

4.2 Reset strategies ...................................................................................... 47

4.2.1 Reset strategies in detail .......................................................................... 47

4.3 Cache handling ....................................................................................... 49

4.3.1 Cache coherency..................................................................................... 49

4.3.2 Cache clean area..................................................................................... 49

4.3.3 Cache handling of ARM7 cores .................................................................. 49

4.3.4 Cache handling of ARM9 cores .................................................................. 49

4.4 Connecting multiple J-Links / J-Traces to your PC ........................................ 50

4.4.1 How does it work?................................................................................... 50

4.4.2 Configuring multiple J-Links / J-Traces ....................................................... 51

4.4.3 Connecting to a J-Link / J-Trace with non default USB-Address...................... 52

4.5 Multi-core debugging ............................................................................... 53

4.5.1 How multi-core debugging works............................................................... 53

4.5.2 Using multi-core debugging in detail .......................................................... 54

4.5.3 Things you should be aware of .................................................................. 56

4.6 Multiple devices in the scan chain.............................................................. 57

4.6.1 Configuration.......................................................................................... 57

4.7 Using DCC for memory access .................................................................. 58

4.7.1 What is required ? ................................................................................... 58

4.7.2 Target DCC handler ................................................................................. 58

4.7.3 Target DCC abort handler......................................................................... 58

4.7.4 Testing DCC memory access..................................................................... 59

4.8 Command strings .................................................................................... 60

4.8.1 List of available commands....................................................................... 60

4.8.2 Using command strings............................................................................ 64

4.9 Switching off CPU clock during debug......................................................... 66

5 Device specifics.............................................................................................................67

5.1 Analog Devices ....................................................................................... 68

5.1.1 ADuC7xxx .............................................................................................. 68

5.2 ATMEL ................................................................................................... 69

5.2.1 AT91SAM7 ............................................................................................. 69

5.2.2 AT91SAM9 ............................................................................................. 69

5.3 NXP....................................................................................................... 70

5.3.1 LPC ....................................................................................................... 70

5.4 ST Microelectronics.................................................................................. 71

5.4.1 STR 71x................................................................................................. 71

5.4.2 STR 73x................................................................................................. 71

5.4.3 STR 75x................................................................................................. 71

5.4.4 STR91x.................................................................................................. 71

5.4.5 STM32 ................................................................................................... 71

5.5 Texas Instruments .................................................................................. 71

5.5.1 TMS470 ................................................................................................. 71

6 Hardware .......................................................................................................................73

6.1 JTAG Connector ...................................................................................... 74

6.1.1 Pinout.................................................................................................... 74

6.1.2 Target board design for JTAG.................................................................... 75

6.2 Using the JTAG connector with SWD .......................................................... 76

6.2.1 Pin Out .................................................................................................. 76

6.3 JTAG+Trace connector ............................................................................. 77

6.3.1 Connecting the target board ..................................................................... 77

6.3.2 Pinout.................................................................................................... 78

6.3.3 Assignment of trace information pins between ETM architecture versions ........ 79

6.3.4 Trace signals .......................................................................................... 79

6.4 RESET, nTRST ........................................................................................ 81

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6.5 Adapters ................................................................................................82

6.5.1 JTAG 14 pin adapter ................................................................................82

6.5.2 5 Volt adapter .........................................................................................83

6.6 How to determine the hardware version......................................................84

6.6.1 Differences between different versions .......................................................85

6.7 J-Link OEM versions.................................................................................87

6.7.1 List of OEM products ................................................................................87

7 Background information.................................................................................................89

7.1 JTAG......................................................................................................90

7.1.1 Test access port (TAP)..............................................................................90

7.1.2 Data registers .........................................................................................90

7.1.3 Instruction register ..................................................................................90

7.1.4 The TAP controller ...................................................................................91

7.2 The ARM core..........................................................................................93

7.2.1 Processor modes .....................................................................................93

7.2.2 Registers of the CPU core .........................................................................93

7.2.3 ARM / Thumb instruction set .....................................................................94

7.3 EmbeddedICE ......................................................................................... 95

7.3.1 Breakpoints and watchpoints..................................................................... 95

7.3.2 The ICE registers.....................................................................................96

7.4 Embedded Trace Macrocell (ETM)...............................................................97

7.5 Embedded Trace Buffer (ETB) ...................................................................98

7.6 Flash programming ..................................................................................99

7.6.1 How does flash programming via J-Link / J-Trace work ?............................... 99

7.6.2 Data download to RAM .............................................................................99

7.6.3 Data download via DCC ............................................................................99

7.6.4 Available options for flash programming .....................................................99

7.7 J-Link / J-Trace firmware ........................................................................ 101

7.7.1 Firmware update ................................................................................... 101

7.7.2 Invalidating the firmware........................................................................ 101

8 Designing the target board for trace ............................................................................103

8.1 Overview of high-speed board design ....................................................... 104

8.1.1 Avoiding stubs ...................................................................................... 104

8.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)............................... 104

8.1.3 Minimizing Crosstalk .............................................................................. 104

8.1.4 Using impedance matching and termination .............................................. 104

8.2 Terminating the trace signal.................................................................... 105

8.2.1 Rules for series terminators .................................................................... 105

8.3 Signal requirements............................................................................... 106

9 Support and FAQs.......................................................................................................107

9.1 Troubleshooting .................................................................................... 108

9.1.1 General procedure ................................................................................. 108

9.1.2 Typical problem scenarios....................................................................... 108

9.2 Signal analysis ...................................................................................... 110

9.2.1 Start sequence ...................................................................................... 110

9.2.2 Troubleshooting .................................................................................... 110

9.3 Contacting support ................................................................................ 111

9.4 Frequently Asked Questions .................................................................... 112

10 Glossary.....................................................................................................................113

11 Literature and references...........................................................................................119

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Chapter 1

Introduction

This chapter gives a short overview about J-Link and J-Trace.

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12 CHAPTER 1 Introduction

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

1.1 J-Link overview

J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003 or Windows Vista. J-Link has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM.

1.1.1 Features of J-Link

• USB 2.0 interface

• Any ARM7/ARM9 core supported, including thumb mode

• Automatic core recognition

• Maximum JTAG speed 12 MHz

• Download speed up to 720 Kbytes/second *

• DCC speed up to 800 Kbytes/second *

• Seamless integration into the IAR Embedded Workbench® IDE

• No power supply required, powered through USB

• Auto speed recognition

• Support for adaptive clocking

• All JTAG signals can be monitored, target voltage can be measured

• Support for multiple devices

• Fully plug and play compatible

• A Standard 20-pin JTAG connector

• Optional 14-pin JTAG adapter available

• Wide target voltage range: 1.2V - 3.3V

• Optional adapter for 5V targets available

• An USB and 20-pin ribbon cable included

• Memory viewer (J-Mem) included

• A TCP/IP server included, which allows using J-Link via TCP/IP networks

• A RDI DLL available, which allows using J-Link with RDI compliant software

• Flash programming software (J-Flash) available

• A Flash DLL available, which allows using flash functionality in custom applications

• A Software Developer Kit (SDK) available

• Embedded Trace Buffer (ETB) support

* = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed.

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1.2 J-Trace overview

J-Trace is a JTAG emulator designed for ARM cores which includes trace (ETM) support. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003 or Windows Vista. J-Trace has a built-in 20-pin JTAG connector and a built in 38-pin JTAG+Trace connector, which is compatible with the standard 20-pin connector and 38-pin connector defined by ARM.

1.2.1 Features of J-Trace

• USB 2.0 interface

• Any ARM7/ARM9 core supported, including thumb mode

• Automatic core recognition

• Maximum JTAG speed 12 MHz

• Download speed up to 420 Kbytes/second *

• DCC speed up to 600 Kbytes/second *

• Seamless integration into the IAR Embedded Workbench® IDE

• No power supply required, powered through USB

• Auto speed recognition

• Support for adaptive clocking

• All JTAG signals can be monitored, target voltage can be measured

• Support for multiple devices

• Fully plug and play compatible

• Standard 20-pin JTAG connector, standard 38-pin JTAG+Trace connector

• An Optional 14-pin JTAG adapter available

• Wide target voltage range: 3.0V - 3.6V

• An Optional adapter for 5V targets available

• An USB and 20-pin ribbon cable included

• Memory viewer (J-Mem) included

• A TCP/IP server included, which allows using J-Trace via TCP/IP networks

• Flash programming software (J-Flash) available

• A Flash DLL available, which allows using flash functionality in custom applications

• A Software Developer Kit (SDK) available

• Full integration with the IAR C-SPY® debugger; advanced debugging features available from IAR C-SPY debugger.

* = Measured with J-Trace, ARM7 @ 50 MHz, 12MHz JTAG speed.

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14 CHAPTER 1 Introduction

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

1.2.2 Test environment

JLink.exe has been used for measurement performance. The hardware consisted of:

• PC with 2.6 GHz Pentium 4, running Win2K

• USB 2.0 port

• USB 2.0 hub

•J-Link

• Target with ARM7 running at 50MHz.

Below is a screenshot of JLink.exe after the measurement has been performed.

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1.3 Specifications

1.3.1 Specifications for J-Link

1.3.2 Specifications for J-Trace

Power Supply USB powered <50mA USB Interface USB 2.0, full speed Target Interface JTAG 20-pin (14-pin adapter available) Serial Transfer Rate between J-Link and Tar-

get

up to 12 MHz

Supported Target Voltage 1.2 - 3.3 V (5V adapter available) Target supply voltage 4.5V .. 5V (if powered with 5V on USB) Target supply current Max. 300mA Operating Temperature +5°C ... +60°C Storage Temperature -20°C ... +65 °C Relative Humidity (non-condensing) <90% rH Size (without cables) 100mm x 53mm x 27mm Weight (without cables) 70g Electromagnetic Compatibility (EMC) EN 55022, EN 55024

Supported OS

Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64

Table 1.1: J-Link specifications

Power Supply USB powered < 300mA USB Interface USB 2.0, full speed

Target Interface

JTAG 20-pin (14-pin adapter available) JTAG+Trace: Mictor, 38-pin

Serial Transfer Rate between J-Trace and Tar g e t

up to 12 MHz

Supported Target Voltage 3.0 - 3.6 V (5V adapter available) Operating Temperature +5°C ... +40°C Storage Temperature -20°C ... +65 °C Relative Humidity (non-condensing) <90% rH Size (without cables) 123mm x 68mm x 30mm Weight (without cables) 120g Electromagnetic Compatibility (EMC) EN 55022, EN 55024

Supported OS

Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64

Table 1.2: J-Trace specifications

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16 CHAPTER 1 Introduction

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

1.3.3 Download speed

The following table lists performance values (Kbytes/s) for writing to memory (RAM):

Note: The actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

Hardware

Memory download

via DCC

ARM7

Memory download

ARM9

Memory download

J-Link Rev. 1 — 4

185.0 Kbytes/s (4MHz JTAG)

150.0 Kbytes/s (4MHz JTAG)

75.0 Kbytes/s (4MHz JTAG)

J-Link Rev. 5

800.0 Kbytes/s (12MHz JTAG)

720.0 Kbytes/s (12MHz JTAG)

550.0 Kbytes/s (12MHz JTAG)

J-Trace Rev.1

600.0 Kbytes/s (12MHz JTAG)

420.0 Kbytes/s (12MHz JTAG)

280.0 Kbytes/s (12MHz JTAG)

Table 1.3: Download speed differences between hardware revisions

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1.4 Requirements

Host System

To use J-Link or J-Trace you need a host system running Windows 2000, Windows XP, Windows 2003, or Windows Vista.

Target System

An ARM7 or ARM9 target system is required. The system should have a standardized 20-pin connector as defined by ARM Ltd. for a simple JTAG connection. The individual pins are described in section JTAG Connector on page 74. Note that Segger offers an optional adapter to use J-Link and J-Trace with targets using 14 pin 0.1" mating JTAG connectors.

To use tracing with J-Trace, you need a 38-pin connector on your target board as defined by ARM Ltd. and described under JTAG+Trace connector on page 77. The individual pins are described in section Pinout on page 78.

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18 CHAPTER 1 Introduction

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

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Chapter 2

Setup

This chapter describes the setup procedure required in order to work with J-Link / JTrace. Primarily this includes the installation of the J-Link software and documentation package, which also includes a kernel mode J-Link USB driver in your host system.

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20 CHAPTER 2 Setup

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

2.1 Installing the J-Link ARM software and documentation pack

J-Link is shipped with a bundle of applications, corresponding manuals and some sample projects and the kernel mode J-Link USB driver. Some of the applications require an additional license, free trial licenses are avaliable upon request from www.segger.com.

Refer to chapter J-Link and J-Trace related software on page 33 for an overview about the J-Link software and documentation pack.

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2.1.1 Setup procedure

To install the J-Link ARM software and documentation pack, follow this procedure:

Note: We recommend to check if a newer version of the J-Link software and documentation pack is available for download before starting the installation. Check therefore the J-Link related download section of our website:

http://www.segger.com/download_jlink.html

1. Before you plug your J-Link / J-Trace into your computer's USB port, extract the setup tool Setup_JLinkARM_V<VersionNumber>.zip. The setup wizard will install the software and documentation pack that also includes the certified JLink USB driver. Start the setup by double clicking Setup_JLinkARM_V<Version- Number>.exe. The license Agreement dialog box will be opened. Accept the terms with the Yes button.

2. The Welcome dialog box is opened. Click Next > to open the Choose Destina- tion Location dialog box.

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22 CHAPTER 2 Setup

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

3. Accept the default installation path C:\Program Files\SEGGER\JLinkARM_V<VersionNumber> or choose an alternative location. Confirm

your choice with the Next > button.

4. The Choose options dialog is opened. The Create entry in start menu and the Add shortcuts to desktop option are preselected. Accept or deselect the options and confirm the selection with the Next > button.

5. The installation process will be started.

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6. The Installation Complete dialog box appears after the copy process. Close the installation wizard with the Finish > button.

The J-Link software and documentation pack is successfully installed on your PC.

7. Connect your J-Link via USB with your PC. The J-Link will be identified and after a short period the J-Link LED stopps rapidly flashing and stays on permanently.

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24 CHAPTER 2 Setup

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

2.1.2 Verifying correct driver installation

To verify the correct installation of the driver, disconnect and reconnect J-Link / JTrace to the USB port. During the enumeration process which takes about 2 seconds, the LED on J-Link / J-Trace is flashing. After successful enumeration, the LED stays on permanently.

Start the provided sample application JLink.exe, which should display the compilation time of the J-Link firmware, the serial number, a target voltage of 0.000V, a complementary error message, which says that the supply voltage is too low if no target is connected to J-Link / J-Trace, and the speed selection. The screenshot below shows an example.

In addition you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your computer, the device manager should list the J-Link USB driver as a node below "Universal Serial Bus controllers" as shown in the following screenshot:

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Right-click on the driver to open a context menu which contains the command Properties. If you select this command, a J-Link driver Properties dialog box is opened

and should report: This device is working properly.

If you experience problems, refer to the chapter Support and FAQs on page 107 for help. You can select the Driver tab for detailed information about driver provider, version, date and digital signer.

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26 CHAPTER 2 Setup

J-Link / J-Trace User Guide ©

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

2.2 Uninstalling the J-Link USB driver

If J-Link / J-Trace is not properly recognized by Windows and therefore does not enumerate, it make sense to uninstall the J-Link USB driver.

This might be the case when:

• The LED on the J-Link / J-Trace is rapidly flashing.

• The J-Link / J-Trace is recognized as Unknown Device by Windows.

To have a clean system and help Windows to reinstall the J-Link driver, follow this procedure:

1. Disconnect J-Link / J-Trace from your PC.

2. Open the Add/Remove Programs dialog (Start > Settings > Control Panel

> Add/Remove Programs) and select Windows Driver Package - Segger (jlink) USB and click the Change/Remove button.

3. Confirm the uninstallation process.

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2.3 Connecting the target system

2.3.1 Power-on sequence

In general, J-Link / J-Trace should be powered on before connecting it with the target device. That means you should first connect J-Link / J-Trace with the host system via USB and then connect J-Link / J-Trace with the target device via JTAG. Power-on the device after you connected J-Link / J-Trace to it.

2.3.2 Verifying target device connection

If the USB driver is working properly and your J-Link / J-Trace is connected with the host system, you may connect J-Link / J-Trace to your target hardware. Then start JLink.exe which should now display the normal J-Link / J-Trace related information and in addition to that it should report that it found a JTAG target and the target’s core ID. The screenshot below shows the output of JLink.exe. As can be seen, it reports a J-Link with one JTAG device connected.

2.3.3 Problems

If you experience problems with any of the steps described above, read the chapter Support and FAQs on page 107 for troubleshooting tips. If you still do not find appropriate help there and your J-Link / J-Trace is an original Segger product, you may contact Segger support via e-mail. Provide the necessary information about your target processor, board etc. and we will try to solve your problem. A checklist of the required information together with the contact information can be found in chapter Support and FAQs on page 107 as well.

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2.4 Scan chain configuration

By default, only one ARM device is assumed to be in the JTAG scan chain. If you have multiple devices in the scan chain, you must properly configure it. To do so, you have to specify the exact position of the ARM device that should be addressed. Configuration of the scan is done by the target application. A target application can be a debugger such as the IAR C-SPY® debugger, ARM’s AXD using RDI, a flash programming application such as SEGGER’s J-Flash, or any other application using J-Link / J-Trace. It is the application’s responsibility to supply a way to configure the scan chain. Most applications offer a dialog box for this purpose.

2.4.1 Sample configuration dialog boxes

As explained before, it is responsibility of the application to allow the user to configure the scan chain. This is typically done in a dialog box; some sample dialog boxes are shown below.

SEGGER J-Flash configuration dialog

This dialog box can be found under Options|Project settings.

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SEGGER J-Link RDI configuration dialog box

This dialog can be found under RDI|Configure for example in IAR Embedded Workbench®. For detailed information check the IAR Embedded Workbench user guide.

IAR J-Link configuration dialog box

This dialog can be found under Project|Options.

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2.4.2 Determining values for scan chain configuration

When do I need to configure the scan chain?

If only one device is connected to the scan chain, the default configuration can be used. In other cases, J-Link / J-Trace may succeed in automatically recognizing the devices on the scan chain, but whether this is possible depends on the devices present on the scan chain.

How do I configure the scan chain ?

2 values need to be known:

• The position of the target device in the scan chain

• The total number of bits in the instruction registers of the devices before the target device (IR len).

The position can usually be seen in the schematic; the IR len can be found in the manual supplied by the manufacturers of the others devices.

ARM7/ARM9 have an IR len of four.

Sample configurations

The diagram below shows a scan chain configuration sample with 2 devices connected to the JTAG port.

Examples

The following table shows a few sample configurations with 1,2 and 3 devices in different configurations.

The target device is marked in blue.

Device 0

Chip(IR len)

Device 1

Chip(IR len)

Device 2

Chip(IR len)

Position IR len

ARM(4) --00 ARM(4) Xilinx(8) - 0 0

Xilinx(8) ARM(4) -18 Xilinx(8) Xilinx(8) ARM(4) 216

ARM(4) Xilinx(8) ARM(4) 0 0

ARM(4) Xilinx(8) ARM(4) 212

Xilinx(8) ARM(4) Xilinx(8) 1 8

Table 2.1: Example scan chain configurations

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2.5 JTAG Speed

There are basically three types of speed settings:

• Fixed JTAG speed

•Automatic JTAG speed

• Adaptive clocking.

These are explained below.

2.5.1 Fixed JTAG speed

The target is clocked at a fixed clock speed. The maximum JTAG speed the target can handle depends on the target itself. In general ARM cores without JTAG synchronization logic (such as ARM7-TDMI) can handle JTAG speeds up to the CPU speed, ARM cores with JTAG synchronization logic (such as ARM7-TDMI-S, ARM946E-S, ARM966EJ-S) can handle JTAG speeds up to 1/6 of the CPU speed.

JTAG speeds of more than 10 MHz are not recommended.

2.5.2 Automatic JTAG speed

Selects the maximum JTAG speed handled by the TAP controller.

Note: On ARM cores without synchronization logic, this may not work reliably, because the CPU core may be clocked slower than the maximum JTAG speed.

2.5.3 Adaptive clocking

If the target provides the RTCK signal, select the adaptive clocking function to synchronize the clock to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface.

Note: If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking.

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Chapter 3

J-Link and J-Trace related software

This chapter describes Segger’s J-Link / J-Trace related software portfoliowhich covers nearly all phases of the development of embedded applications. The support of the remote debug interface (RDI) and the J-Link GDBServer allows an easy J-Link integration in all relevant toolchains.

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3.1 J-Link related software

3.1.1 J-Link software and documentation package

J-Link is shipped with a bundle of applications. Some of the applications require an additional license, free trial licenses are available upon request from www.seg- ger.com.

3.1.2 List of additional software packages

The software packages listed below are available upon request from www.segger.com.

Software Description

JLinkARM.dll DLL for using J-Link / J-Trace with third-party programs.

JLink.exe

Free command-line tool with basic functionality for target analysis.

JLinkSTR91x Free command-line tool to configure the ST STR91x cores.

J-Link TCP/IP Server

Free utility which provides the possibility to use J-Link / J-Trace remotely via TCP/IP.

J-Mem memory viewer

Free target memory viewer. Shows the memory content of a running target and allows editing as well.

J-Flash

Stand-alone flash programming application. Requires an additional license.

RDI support with Flash download and Flash breakpoints.

Provides Remote Debug Interface (RDI) support. Flash breakpoints provide the ability to set an unlimited number of software breakpoints in flash memory areas. Flash download allows an arbitrary debugger to write into flash memory. Each additional feature requires an own additional license.

J-Link GDB Server

The J-Link GDB Server is a remote server for the GNU Debugger (GDB). Requires an additional license.

Table 3.1: J-Link / J-Trace related software

Software Description

JTAGLoad

Command line tool that opens an svf file and sends the data in it via J-Link / J-Trace to the target.

J-Link Software Developer Kit (SDK)

The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace.

J-Link Flash Software Developer Kit (SDK)

An enhanced version of the JLinkARM.DLL, which contains additional API functions for flash programming.

Table 3.2: J-Link / J-Trace additional software packages

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3.2 J-Link software and documentation package in detail

The J-Link / J-Trace software documentation packge is shipped together with J-Link / J-Trace and may also be downloaded from www.segger.com.

3.2.1 J-Link Commander (Command line tool)

J-Link Commander (JLink.exe) is a tool that can be used for verifying proper installation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system. It permits some simple commands, such as memory dump, halt, step, go and ID-check, as well as some more in-depths analysis of the state of the ARM core and the ICE breaker module.

3.2.2 J-Link STR9 Commander (Command line tool)

J-Link Commander (JLinkSTR9x.exe) is a tool that can be used to configure STR91x cores. It permits some STR9 specific commands like setting the flash configuration register and erasing the flash. This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall.

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3.2.3 J-Link TCP/IP Server (Remote J-Link / J-Trace use)

The J-Link TCP/IP Server allows using J-Link / J-Trace remotely via TCP/IP. This enables you to connect to and fully use a J-Link / J-Trace from another computer. Performance is just slightly (about 10%) lower than with direct USB connection.

3.2.4 J-Mem Memory Viewer

J-Mem displays memory contents of ARM-systems and allows modifications of RAM and SFRs (Special Function Registers) while the target is running. This makes it possible to look into the memory of an ARM chip at run-time; RAM can be modified and SFRs can be written. You can choose bewteen 8/16/32-bit size for read and write accesses. J-Mem works nicely when modifying SFRs, especially because it writes the SFR only after the complete value has been entered.

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3.2.5 J-Flash ARM (Program flash memory via JTAG)

J-Flash ARM is a software running on Windows 2000, Windows XP, Windows 2003 or Windows Vista systems and enables you to program your flash EEPROM devices via the JTAG connector on your target system.

J-Flash ARM works with any ARM7/9 system and supports all common external flashes, as well as the programming of internal flash of ARM microcontrollers. It allows you to erase, fill, program, blank check, upload flash content, and view memory functions of the software with your flash devices.

J-Flash requires a additional license from Segger. Even without a license key you can still use J-Flash ARM to open project files, read from connected devices, blank check target memory, verify data files and so on. However, to actually program devices via J-Flash ARM and J-Link / J-Trace you are required to obtain a license key from us. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.

Features

•Works with any ARM7/ARM9 chip

• ARM microcontrollers (internal flash) supported

• Most external flash chips can be programmed

• High-speed programming: up to 200 Kbytes/second (depends on flash device)

• Very high-speed blank check: Approximatelly 16 Mbytes/sec (depends on target)

• Smart read-back: Only non-blank portions of flash transferred and saved

• Easy to use, comes with projects for standard eval boards.

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3.2.6 J-Link RDI (Remote Debug Interface)

The J-Link RDI software is an remote debug interface for J-Link. It makes it possible to use J-Link with any RDI compliant debugger. The main part of the software is an RDI-compliant DLL, which needs to be selected in the debugger. There are two additional features available which build on the RDI software foundation. Each additional features requires an RDI license in addition to its own license. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.

Note: The RDI software (as well as flash breakpoints and flash downloads) do not require a license if the target device is an LPC2xxx. In this case the software verifies that the target device is actually an LPC 2xxx.

3.2.6.1 Flash download

The J-Link RDI software contains a flash loader. On top of that, the flash download software lets flash memory appear as RAM to a debugger. This enables you to use any arbitrary debugger which normally only allows downloads into RAM to work with flash memory as well. If a debugger splits the download image into several pieces, the flash download software will collect the individual parts and perform the actual flash programming right before program execution. This avoids repeated flash programming.

The advantage you gain is the possibility to transparently use your toolchain of choice—that may not contain a flash loader—with flash memory that can be programmed as if it were RAM.

3.2.6.2 Flash breakpoints

The J-Link RDI software contains an additional feature, called flash breakpoints (short FlashBPs). This feature requires an additional license. It adds the ability to set an unlimited number of software breakpoints in flash memory areas, rather than just the 2 hardware breakpoints permitted by the ICE. Setting the breakpoints in flash is executed very fast using a RAM code specifically designed for this purpose; on chips with fast flash, the difference between breakpoints in RAM and flash is unnoticeable.

How do breakpoints work?

ARM7 and ARM9 cores have 2 breakpoint units (called "watchpoint units" in ARM's documentation), allowing 2 hardware breakpoints to be set. Hardware breakpoints do not require modification of the program code. Software breakpoints are different: The debugger modifies the program by replacing the instruction where the breakpoint is set with a special value. Additional software breakpoints do not require additional hardware units in the processor, since simply more instructions are replaced. This is a standard procedure that most debuggers are capable of, however, it requires the program to be located in RAM.

What is special about software breakpoints in flash?

FlashBPs allow you to set an unlimited number of breakpoints even if your application program is not located in RAM, but in flash memory. This is a scenario which was very rare before ARM-microcontrollers hit the market. This new technology makes very powerful, yet inexpensive ARM microcontrollers available for systems, which required external RAM before. The downside of this new technology is that it is not possible to debug larger programs on these micros in RAM, because the RAM is not big enough to hold program and data (typically, these chips contain about 4 times as much flash as RAM), and therefore with standard debuggers, only 2 breakpoints can be set. The breakpoint limit makes debugging very tough; a lot of times the debugger requires 2 breakpoints to simply step over a line of code. With software breakpoints in flash, this limitation is gone.

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How does this work?

Basically, it is very simple the J-Link RDI software reprograms a sector of the flash to set or clear a breakpoint.

What performance can I expect?

A RAM code, specially designed for this purpose, sets and clears flash breakpoints extremely fast; on micros with fast flash the difference between breakpoints in RAM and flash is hardly noticeable.

How is this performance achieved?

We have put a lot of effort in making FlashBPs really usable and convenient. Flash sectors are programmed only when necessary; this is usually the moment execution of the target program is started. A lot of times, more than one breakpoint is located in the same flash sector, which allows programming multiple breakpoints by programming just a single sector. The contents of program memory are cached, avoiding time consuming reading of the flash sectors. A smart combination of software and hardware breakpoints allows us to use hardware breakpoints a lot of times, especially when the debugger is source-level stepping, avoiding reprogramming of the flash in these situations. A built-in instruction set simulator further reduces the number of flash operations which need to be performed. This minimizes delays for the user, maximizing the life time of the flash. All resources of the ARM micro are available to the application program, no memory is lost for debugging. All of the optimizations described above can be disabled.

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3.2.7 J-Link GDB Server

GDB Server is a remote server for the GNU Debugger GDB. GDB and GDB Server communicate via a TCP/IP connection, using the standard GDB remote serial protocol. The GDB Server translates the GDB monitor commands into J-Link commands.

The GNU Project Debugger (GDB) is a freely available debugger, distributed under the terms of the GPL. It connects to an emulator via a TCP/IP connection. It can connect to every emulator for which a GDB Server software is available. The latest Unix version of the GDB is freely available from the GNU commitee under:

http://www.gnu.org/software/gdb/download/

J-Link GDB Server is distributed as "free for evaluation and non commercial use". The software can be used free of charge for educational and nonprofit purposes without additional license. Without additional license, only 32 KBytes may be downloaded. To download bigger programs or to use the software for other, especially commercial purposes, a license is required. With such a license, the download size is not limited. Free 30 days limited license are available upon request. For further information go to our website or contact us directly.

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3.3 Additional software packages in detail

The packages described in this section are not available for download. If you wish to use one of them, contact SEGGER Microcontroller Systeme directly.

3.3.1 JTAGLoad (Command line tool)

JTAGLoad is a tool that can be used to open an svf (Serial vector format) file. The data in the file will be sent to the target via J-Link / J-Trace.

3.3.2 J-Link Software Developer Kit (SDK)

The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace. The J-Link DLL is a standard Windows DLL typically used from C programs (Visual Basic or Delphi projects are also possible). It makes the entire functionality of J-Link / J-Trace available through its exported functions, such as halting/stepping the ARM core, reading/writing CPU and ICE registers and reading/writing memory. Therefore it can be used in any kind of application accessing an ARM core. The standard DLL does not have API functions for flash programming. However, the functionality offered can be used to program flash. In this case, a flash loader is required. The table below lists some of the included files and their respective purpose.

3.3.3 J-Link Flash Software Developer Kit (SDK)

This is an enhanced version of the JLinkARM.DLL which contains additional API functions for flash programming. The additional API functions (prefixed JLINKARM_FLASH_) allow erasing and programming of flash memory. This DLL comes with a sample executable, as well as with source code of this executable and a Microsoft Visual C/C++ project file. It can be an interesting option if you want to write your own programs for production purposes.

Files Contents

GLOBAL.h JLinkARMDLL.h

Header files that must be included to use the DLL functions. These files contain the defines, typedef names, and function declarations.

JLinkARM.lib A Library that contains the exports of the JLink DLL. JLinkARM.dll The DLL itself. Main.c Sample application, which calls some JLinkARM DLL functions. JLink.dsp

JLink.dsw

Project files of the sample application. Double click JLink.dsw to open the project.

JLinkARMDLL.pdf Extensive documentation (API, sample projects etc.).

Table 3.3: J-Link SDK

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3.4 Using the J-LinkARM.dll

3.4.1 What is the JLinkARM.dll?

The J-LinkARM.dll is a standard Windows DLL typically used from C or C++, but also Visual Basic or Delphi projects. It makes the entire functionality of the J-Link / JTrace available through the exported functions.

The functionality includes things such as halting/stepping the ARM core, reading/ writing CPU and ICE registersm, and reading/writing memory. Therefore, it can be used in any kind of application accessing an ARM core.

3.4.2 Updating the DLL in third-party programs

The JLinkARM.dll can be used by any debugger that is designed to work with it. Some debuggers, like the IAR C-SPY® debugger, are usually shipped with the JLinkARM.dll already installed. Anyhow it may make sense to replace the included DLL with the latest one available, to take advantage of improvements in the newer version.

3.4.2.1 Updating the JLinkARM.dll in the IAR Embedded Workbench (EWARM)

The IAR Embedded Workbench IDE is a high-performance integrated development environment with an editor, compiler, linker, debugger. The compiler generates very efficient code and is widely used. It comes with the J-LinkARM.dll in the arm\bin subdirectory of the installation directory. To update this DLL, you should backup your original DLL and then replace it with the new one.

Typically, the DLL is located in C:\Program Files\IAR Systems\Embedded Work- bench 4.0\arm\bin\.

After updating the DLL, it is recommended to verify that the new DLL is loaded as described in Determining which DLL is used by a program on page 35.

3.4.3 Determining the version of JLinkARM.dll

To determine which version of the JLinkARM.dll you are facing, the DLL version can be viewed by right clicking the DLL in explorer, and choosing Properties from the context menu. Click the Version tab to display information about the product version.

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3.4.4 Determining which DLL is used by a program

To verify that the program you are working with is using the DLL you expect it to use, you can investigate which DLLs are loaded by your program with tools like Sysinternals’ Process Explorer. It shows you details about the DLLs, used by your program, such as manufacturer and version.

Process Explorer is - at the time of writing - a free utility which can be downloaded from www.sysinternals.com.

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Chapter 4

Working with J-Link and J-Trace

This chapter describes functionality and how to use J-Link and J-Trace.

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4.1 Supported ARM Cores

J-Link / J-Trace has been tested with the following cores, but should work with any ARM7/ARM9 and Cortex-M3 core. If you experience problems with a particular core, do not hesitate to contact Segger.

• ARM7TDMI (Rev 1)

• ARM7TDMI (Rev 3)

• ARM7TDMI-S (Rev 4)

• ARM720T

• ARM920T

• ARM922T

• ARM926EJ-S

• ARM946E-S

• ARM966E-S

•Cortex-M3

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4.2 Reset strategies

J-Link / J-Trace supports different reset strategies. This is necessary because there is no single way of resetting and halting an ARM core before it starts to execute instructions.

What is the problem if the core executes some instructions after RESET?

The instructions executed can cause various problems. Some cores can be completely "confused", which means they can not be switched into debug mode (CPU can not be halted). In other cases, the CPU may already have initialized some hardware components, causing unexpected interrupts or worse, the hardware may have been initialized with illegal values. In some of these cases, such as illegal PLL settings, the CPU may be operated beyond specification, possibly locking the CPU.

4.2.1 Reset strategies in detail

4.2.1.1 Type 0: Hardware, halt after reset (normal)

The hardware reset pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted. The number of instructions executed depends primarily on the JTAG speed: the higher the JTAG speed, the faster the CPU can be halted.

Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release. If a pause has been specified, J-Link waits for the specified time before trying to halt the CPU. This can be useful if a bootloader which resides in flash or ROM needs to be started after reset.

This reset strategy is typically used if nRESET and nTRST are coupled. If nRESET and nTRST are coupled, either on the board or the CPU itself, reset clears the breakpoint, which means that the CPU can not be stopped after reset with the BP@0 reset strategy.

4.2.1.2 Type 1: Hardware, halt with BP@0

The hardware reset pin is used to reset the CPU. Before doing so, the ICE breaker is programmed to halt program execution at address 0; effectively, a breakpoint is set at address 0. If this strategy works, the CPU is actually halted before executing a single instruction.

This reset strategy does not work on all systems for two reasons:

• If nRESET and nTRST are coupled, either on the board or the CPU itself, reset clears the breakpoint, which means the CPU is not stopped after reset.

• Some MCUs contain a bootloader program (sometimes called kernel), which needs to be executed to enable JTAG access.

4.2.1.3 Type 2: Software, for Analog Devices ADuC7xxx MCUs

This reset strategy is a software strategy. The CPU is halted and performs a sequence which causes a peripheral reset. The following sequence is executed:

•The CPU is halted

• A software reset sequence is downloaded to RAM

• A breakpoint at address 0 is set

• The software reset sequence is executed.

This sequence performs a reset of CPU and peripherals and halts the CPU before executing instructions of the user program. It is the recommended reset sequence for Analog Devices ADuC7xxx MCUs and works with these chips only.

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4.2.1.4 Type 3: No reset

No reset is performed. Nothing happens.

4.2.1.5 Type 4: Hardware, halt with WP

The hardware RESET pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU using a watchpoint. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted.

The number of instructions executed depends primarily on the JTAG speed: the higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release

4.2.1.6 Type 5: Hardware, halt with DBGRQ

The hardware RESET pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU using the DBGRQ. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted.

4.2.1.7 Type 6: Software

This reset strategy is only a software reset. "Software reset" means basically no reset, just changing the CPU registers such as PC and CPSR. This reset strategy sets the CPU registers to their after-Reset values:

•PC = 0

• CPSR = 0xD3 (Supervisor mode, ARM, IRQ / FIQ disabled)

• All SPSR registers = 0x10

• All other registers (which are unpredictable after reset) are set to 0.

• The hardware RESET pin is not affected.

4.2.1.8 Type 7: Reserved

Reserved reset type.

4.2.1.9 Type 8: Software, for ATMEL AT91SAM7 MCUs

The reset pin of the device is per default disabled. This means that the reset strategies which rely on the reset pin (low pulse on reset) do not work per default. For this reason a special reset strategy has been made available.

It is recommended to use this reset strategy. This special reset strategy resets the peripherals by writing to the RSTC_CR register. Resetting the peripherals puts all peripherals in the defined reset state. This includes memory mapping register, which means that after reset flash is mapped to address 0. It is also possible to achieve the same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.

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4.3 Cache handling

Most ARM systems with external memory have at least one cache. Typically, ARM7 systems with external memory come with a unified cache, which is used for both code and data. Most ARM9 systems with external memory come with separate caches for the instruction bus (I-Cache) and data bus (D-Cache) due to the hardware architecture.

4.3.1 Cache coherency

When debugging or otherwise working with a system with processor with cache, it is important to maintain the cache(s) and main memory coherent. This is easy in systems with a unified cache and becomes increasingly difficult in systems with hardware architecture. A write buffer and a D-Cache configured in write back-mode can further complicate the problem.

ARM 9 chips have no hardware to keep the caches coherent, so that this is the responsibility of the software.

4.3.2 Cache clean area

J-Link / J-Trace handles cache cleaning directly through JTAG commands. Unlike other emulators, it does not have to download code to the target system. This makes setting up J-Link / J-Trace easier. Therefore, a cache clean area is not required.

4.3.3 Cache handling of ARM7 cores

Because ARM7 cores have a unified cache, there is no need to handle the caches during debug.

4.3.4 Cache handling of ARM9 cores

ARM9 cores with cache require J-Link / J-Trace to handle the caches during debug. If the processor enters debug state with caches enabled, J-Link / J-Trace does the following:

When entering debug state

J-Link / J-Trace performs the following:

• it stores the current write behavior for the D-Cache

• it selects write-through behavior for the D-Cache.

When leaving debug state

J-Link / J-Trace performs the following:

• it restores the stored write behavior for the D-Cache

• it invalidates the D-Cache.

Note: The implementation of the cache handling is different for different cores. However, the cache is handled correctly for all supported ARM9 cores.

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4.4 Connecting multiple J-Links / J-Traces to your PC

You can connect up to 4 J-Links / J-Traces to your PC. In this case, all J-Links / JTraces must have different USB-addresses. The default USB-address is 0.

In order to do this, 3 J-Links / J-Traces must be configured as described below. Every J-Link / J-Trace need its own J-Link USB driver which can be downloaded from www.segger.com.

This feature is supported by J-Link Rev. 5.0 and up and by J-Trace.

4.4.1 How does it work?

USB devices are identified by the OS by their product id, vendor id and serial number. The serial number reported by J-Links / J-Traces is always the same. The product id depends on the configured USB-address.

• The vendor id (VID) representing SEGGER is always 1366

• The product id (PID) for J-Link / J-Trace #1 is 101

• The product id (PID) for J-Link / J-Trace #2 is 102 and so on.

A different PID means that J-Link / J-Trace is identified as a different device, requiring a new driver.

The sketch below shows a host, running two application programs. Each application communicates with one ARM core via a separate J-Link.

Host (PC)

Target hardware 1

ARM2

Application

Instance 2

Application

Instance 1

ARM1

USB

JTAG

J-Link

USB

JTAG

J-Link

Target hardware 2

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4.4.2 Configuring multiple J-Links / J-Traces

1. Start JLink.exe to view your hardware version. Your J-Link needs to be V5.0 or up to continue. For J-Trace the Version does not matter.

2. Type usbaddr = 1 to set the J-Link / J-Trace #1.

3. Unplug J-Link / J-Trace and then plug it back in.

4. The system will recognize a new J-Link / J-Trace and will prompt for a driver.

5. Click OK and browse to the J-Link USB driver for your new J-Link / J-Trace. For your second J-Link / J-Trace this would be JLink1.sys, for your third J-Link / JTrace this would be JLink2.sys.

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4.4.3 Connecting to a J-Link / J-Trace with non default USBAddress

Restart JLink.exe and type usb 1 to connect to J-Link / J-Trace #1.

You may connect other J-Links / J-Traces to your PC and connect to them as well. To connect to an unconfigured J-Link / J-Trace (with default address "0"), restart JLink.exe or type usb 0.

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4.5 Multi-core debugging

J-Link / J-Trace is able to debug multiple cores on one target system connected to the same scan chain. Configuring and using this feature is described in this section.

4.5.1 How multi-core debugging works

Multi-core debugging requires multiple debuggers or multiple instances of the same debugger. Two or more debuggers can use the same J-Link / J-Trace simultaneously. Configuring a debugger to work with a core in a multi-core environment does not require special settings. All that is required is proper setup of the scan chain for each debugger. This enables J-Link / J-Trace to debug more than one core on a target at the same time.

The following figure shows a host, debugging two ARM cores with two instances of the same debugger.

Both debuggers share the same physical connection. The core to debug is selected through the JTAG-settings as described below.

Host (PC)

Target hardware

ARM2

Debugger

Instance 2

Debugger

Instance 1

USB

JTAG

ARM1

J-Link

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4.5.2 Using multi-core debugging in detail

1. Connect your target to J-Link / J-Trace.

2. Start your debugger, for example IAR Embedded Workbench for ARM.

3. Choose Project|Options and configure your scan chain. The picture below shows the configuration for the first ARM core on your target.

4. Start debugging the first core.

5. Start another debugger, for example another instance of IAR Embedded Workbench for ARM.

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6. Choose Project|Options and configure your second scan chain. The following dialog box shows the configuration for the second ARM core on your target.

7. Start debugging your second core.

Example:

Cores to debug are marked in blue.

Core #1 Core #2 Core #3

TAP num b e r

debugger #1

TAP num b e r

debugger #2

ARM7TDMI ARM7TDMI-S ARM7TDMI 0 1 ARM7TDMI ARM7TDMI ARM7TDMI 02

ARM7TDM I-S

ARM7TDMI-S ARM7TDMI-S 12

Table 4.1: Multicore debugging

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4.5.3 Things you should be aware of

Multi-core debugging is more difficult than single-core debugging. You should be aware of the pitfalls related to JTAG speed and resetting the target.

4.5.3.1 JTAG speed

Each core has its own maximum JTAG speed. The maximum JTAG speed of all cores in the same chain is the minimum of the maximum JTAG speeds.

For example:

Core #1: 2MHz maximum JTAG speed

Core #2: 4MHz maximum JTAG speed

Scan chain: 2MHz maximum JTAG speed

4.5.3.2 Resetting the target

All cores share the same RESET line. You should be aware that resetting one core through the RESET line means resetting all cores which have their RESET pins connected to the RESET line on the target.

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4.6 Multiple devices in the scan chain

J-Link / J-Trace can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the following figure, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus.

Currently, up to 8 devices in the scan chain are supported. One or more of these devices can be ARM cores; the other devices can be of any other type but need to comply with the JTAG standard.

4.6.1 Configuration

The configuration of the scan chain depends on the application used. Read Scan chain configuration on page 28 for further instructions and configuration examples.

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4.7 Using DCC for memory access

The ARM7/9 architecture requires cooperation of the CPU to access memory. This means that memory can not normaly be accessed while the CPU is executing the application program. The normal way to read or write memory is to halt the CPU (put it in debug mode) before accessing memory. Even if the CPU is restarted after the memory access, the real time behaviour is significantly affected; halting and restarting the CPU costs typically multiple milliseconds. For this reason, most debuggers do not even allow memory access if the CPU is running. Fortunately, there is one other option: DCC (Direct communication channel) can be used to communicate with the CPU while it is executing the application program. All that is required is that the application program calls a DCC handler from time to time. This DCC handler typically requires less than 1 µs per call.

The DCC handler, as well as the optional DCC abort handler, is part of the J-Link software package and can be found in the "Samples\DCC\IAR" directory of the package.

4.7.1 What is required ?

• An application program on the host (typ. debugger) that uses DCC

• A target application program that regularily calls the DCC handler

• The supplied abort handler should be installed (optional)

An application program that uses DCC is JLink.exe.

4.7.2 Target DCC handler

The target DCC handler is a simple C-file taking care of the communication. The function DCC_Process() needs to be called regularily from the application program or from an interrupt handler. If a RTOS is used, a good place to call the DCC handler is from the timer tick interrupt. In general, the more often the DCC handler is called, the faster memory can be accessed. On most devices, it is also possible to let the DCC generate an interrupt which can be used to call the DCC handler.

4.7.3 Target DCC abort handler

An optional DCC abort handler (a simple assembly file) can be included in the application. The DCC abort handler allows data aborts caused by memory reads/writes via DCC to be handled gracefully. If the data abort has been caused by the DCC communication, it returns to the instruction right after the one causing the abort, allowing the application program to continue to run. In addition to that, it allows the host to detect if a data abort occurred.

In order to use the DCC abort handler, 3 things need to be done:

• Place a branch to DCC_Abort at address 0x10 ("vector" used for data aborts)

• Initialize the Abort-mode stack pointer to an area of at least 8 bytes of stack memory required by the handler

• Add the DCC abort handler assembly file to the application

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4.7.4 Testing DCC memory access

To test if your target system properly calls the DCC handler you can use JLink.exe. The output should be similar to the below:

SEGGER J-Link Commander V3.38c ('?' for help) Compiled Aug 18 2006 18:48:43 DLL version V3.38c, compiled Aug 18 2006 18:48:40 -- Debug -Firmware: J-Link compiled Aug 14 2006 14:58:04 ARM Rev.5 Hardware: V5.40 S/N : 1 VTarget = 3.306V Speed set to 30 kHz Found 1 JTAG device, Total IRLen = 4: Id of device #0: 0x3F0F0F0F Found ARM with core Id 0x3F0F0F0F (ARM7) J-Link>mem 0,40 Reading memory using DCC... 00000000 = 0F 00 00 EA FE FF FF EA FE FF FF EA FE FF FF EA 00000010 = FE FF FF EA FE FF FF EA 1C 00 00 EA 00 90 A0 E1 00000020 = 04 01 98 E5 D3 F0 21 E3 0E 50 2D E9 0F E0 A0 E1 00000030 = 10 FF 2F E1 0E 50 BD E8 D1 F0 21 E3 09 00 A0 E1 J-Link>h PC: (R15) = 000002EA, CPSR = 80000033 (SVC mode, THUMB) R0 = 00005BB4, R1 = 0000BBB2, R2 = FFFFD000, R3 = 000003B8 R4 = FFFFF430, R5 = 00000001, R6 = 00000002, R7 = 00000000 USR: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000 R13=00000000, R14=00000000 FIQ: R8 =FFFFF000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000 R13=00000000, R14=00000000, SPSR=00000010 SVC: R13=00003F8C, R14=000002DF, SPSR=00000010 ABT: R13=00000000, R14=00000000, SPSR=00000010 IRQ: R13=00004000, R14=00000000, SPSR=00000010 UND: R13=00000000, R14=00000000, SPSR=00000010 J-Link>mem 0,40 00000000 = 0F 00 00 EA FE FF FF EA FE FF FF EA FE FF FF EA 00000010 = FE FF FF EA FE FF FF EA 1C 00 00 EA 00 90 A0 E1 00000020 = 04 01 98 E5 D3 F0 21 E3 0E 50 2D E9 0F E0 A0 E1 00000030 = 10 FF 2F E1 0E 50 BD E8 D1 F0 21 E3 09 00 A0 E1

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4.8 Command strings

The behaviour of the J-Link can be customized via command strings passed to the JLinkARM.dll which controls J-Link. Applications such as the J-Link Commander, but also the C-SPY debugger which is part of the IAR Embedded Workbench, allow passing one or more command strings. Command line strings can be used for passing commands to J-Link (such as switching on target power supply), as well as customize the behaviour (by defining memory regions and other things) of J-Link. The use of command strings enables options which can not be set with the configuration dialog box provided by C-SPY.

4.8.1 List of available commands

The table below lists and describes the available command strings.

Command Description

map exclude Ignore all memory accesses to specified area. map indirectread Specifies an area which should be read indirect. map ram Specifies location of target RAM.

map reset

Restores the default mapping, which means all memory accesses are permitted.

SetAllowSimulation Enable/Disable instruction set simulation. SetCheckModeAfterRead Enable/Disable CPSR check after read operations. SetResetPulseLen Defines the length of the RESET pulse in milliseconds. SetResetType Selects the reset strategy

SupplyPower

Activates/Deactivates power supply over pin 19 of the JTAG connector.

SupplyPowerDefault

Activates/Deactivates power supply over pin 19 of the JTAG connector permanently.

Table 4.2: Available command line options

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4.8.1.1 map exclude

This command excludes a specified memory region from all memory accesses. All subsequent memory accesses to this memory region are ignored.

Typical applications

Some devices do not allow access of the entire 4GB memory area. Ideally, the entire memory can be accessed; if a memory access fails, the CPU reports this by switching to abort mode. The CPU memory interface allows halting the CPU via a WAIT signal. On some devices, the WAIT signal stays active when accessing certain unused memory areas. This halts the CPU indefinetly (until RESET) and will therefore end the debug session. This is exactly what happens when accessing critical memory areas. Critical memory areas should not be present in a device; they are typically a hardware design problem. Nevertheless, critical memory areas exist on some devices.

To avoid stalling the debug session, a critical memory area can be excluded from access: J-Link will not try to read or write to critical memory areas and instead ignore the access silently. Some debuggers (such as IAR C-SPY) can try to access memory in such areas by dereferencing non-initialized pointers even if the debugged program (the debuggee) is working perfectly. In situations like this, defining critical memory areas is a good solution.

Syntax

map exclude <SAddr>-<EAddr>

Example

map exclude

4.8.1.2 map indirectread

This command can be used to read a memory area indirectly. Indirectly reading means that a small code snippet is downloaded into RAM of the target device, which reads and transfers the data of the specified memory area to the host. Before map indirectread can be called a RAM area for the indirectly read code snippet has to be defined. Use therefor the map ram command and define a RAM area with a size of >= 256 byte.

Typical applications

Refer to chapter Fast GPIO bug on page 70 for an example.

Syntax

map indirectread <StartAddressOfArea>-<EndAddress>

Example

map indirectread 0x3fffc000-0x3fffcfff

4.8.1.3 map ram

This command should be used to define an area in RAM of the target device. The area must be 256-byte aligned. The data which was located in the defined area will not be corrupted. Data which resides in the defined RAM area is saved and will be restored if necessary. This command has to be executed before map indirectread will be called.

Typical applications

Refer to chapter Fast GPIO bug on page 70 for an example.

Syntax

map ram <StartAddressOfArea>-<EndAddressOfArea>

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Example

map ram 0x40000000-0x40003fff;

4.8.1.4 map reset

This command restores the default memory mapping, which means all memory accesses are permitted.

Typical applications

Used with other "map" commands to return to the default values. The map reset command should be called before any other "map" command is called.

Syntax

map reset

Example

map reset

4.8.1.5 SetAllowSimulation

This command can be used to enable or disable the instruction set simulation. By default the instruction set simulation is enabled.

Syntax

Enable simulation: SetAllowSimulation 1 Disable simulation: SetAllowSimulation 0

Example

SetAllowSimulation 1

4.8.1.6 SetCheckModeAfterRead

This command is used to enable or disable the verification of the CPSR (current processor status register) after each read operation. By default this check is enabled. However this can cause problems with some CPUs (e.g. if invalid CPSR values are returned). Please note that if this check is turned off (SetCheckModeAfterRead = 0), the success of read operations cannot be verified anymore and possible data aborts are not recognized.

Typical applications

This verification of the CPSR can cause problems with some CPUs (e.g. if invalid CPSR values are returned). Note that if this check is turned off (SetCheckModeAfterRead =

0), the success of read operations cannot be verified anymore and possible data

aborts are not recognized.

Syntax

Disable CPSR verification: SetCheckModeAfterRead = 0 Enable CPSR verification: SetCheckModeAfterRead = 1

Example

SetCheckModeAfterRead = 0

4.8.1.7 SetResetPulseLen

This command defines the length of the RESET pulse in milliseconds. The default for the RESET pulse length is 20 milliseconds.

Syntax

SetResetPulseLen = <value>

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Example

SetResetPulseLen = 50

4.8.1.8 SetResetType

This command changes the reset strategy.

Typical applications

Refer to chapter Reset strategies on page 47 for additional informations about the different reset strategies.

Syntax

SetResetType = <value>

Example

SetResetType = 0

Value Description

0 Hardware, halt after reset (normal). 1 Hardware, halt with BP@0. 2 Software, for Analog Devices ADuC7xxx MCUs.

Table 4.3: List of possible value for command SetResetType

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4.8.1.9 SupplyPower

This command activates power supply over pin 19 of the JTAG connector. The KS (Kickstart) versions of J-Link have the V5 supply over pin 19 activated by default.

Typical applications

This feature is useful for some eval boards that can be powered over the JTAG connector.

Syntax

Enable power supply: SupplyPower = 1 Disable power supply: SupplyPower = 0

Example

SupplyPower = 1

4.8.1.10 SupplyPowerDefault

This command activates power supply over pin 19 of the JTAG connector permanently. The KS (Kickstart) versions of J-Link have the V5 supply over pin 19 activated by default.

Typical applications

This feature is usefull for some eval boards that can be powered over the JTAG connector.

Syntax

Enable power supply permanently: SupplyPowerDefault = 1 Disable power supply permanently: SupplyPowerDefault = 0

Example

SupplyPowerDefault = 1

4.8.2 Using command strings

4.8.2.1 J-Link Commander

The J-Link command strings can be testet with the J-Link Commander. Use the comamand exec supplemented by one of the command strings.

Example

exec SupplyPower = 1

exec map reset

exec map exclude 0x10000000-0x3FFFFFFF

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4.8.2.2 IAR Embedded Workbench

The J-Link command strings can be supplied using the C-SPY debugger of the IAR Embedded Workbench. Open the Project options dialog box and select Debugger.

On the Extra Options page, select Use command line options. Enter -jlink_exec_command "<CommandLineOption>" in the textfield, as shown in the screenshot below. If more than one command should be used separate the commands with semicolon.

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4.9 Switching off CPU clock during debug

We recommend not to switch off CPU clock during debug. However, if you do, you should consider the following:

Non-synthesizable cores (ARM7TDMI, ARM9TDMI, ARM920, etc.)

With these cores, the TAP controller uses the clock signal provided by the emulator, which means the TAP controller and ICE-Breaker continue to be accessible even if the CPU has no clock. Therefore, switching off CPU clock during debug is normally possible if the CPU clock is periodically (typically using a regular timer interrupt) switched on every few ms for at least a few us. In this case, the CPU will stop at the first instruction in the ISR (typically at address 0x18).

Synthesizable cores (ARM7TDMI-S, ARM9E-S, etc.)

With these cores, the clock input of the TAP controller is connected to the output of a three-stage synchronizer, which is fed by clock signal provided by the emulator, which means that the TAP controller and ICE-Breaker are not accessible if the CPU has no clock. If the RTCK signal is provided, adaptive clocking function can be used to synchronize the JTAG clock (provided by the emulator) to the processor clock. This way, the JTAG clock is stopped if the CPU clock is switched off.

If adaptive clocking is used, switching off CPU clock during debug is normally possible if the CPU clock is periodically (typically using a regular timer interrupt) switched on every few ms for at least a few us. In this case, the CPU will stop at the first instruction in the ISR (typically at address 0x18).

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Chapter 5

Device specifics

This chapter gives some additional information about specific devices.

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5.1 Analog Devices

5.1.1 ADuC7xxx

5.1.1.1 Software reset

A special reset strategy has been made available for Analog Devices ADuC7xxx MCUs. This special reset strategy is a software reset. "Software reset" means basically no reset, just changing the CPU registers such as PC and CPSR.

The software reset for Analog Devices ADuC7xxxx executes the following sequence:

• The CPU is halted

• A software reset sequence is downloaded to RAM

• A breakpoint at address 0 is set

• The software reset sequence is executed.

It is recommended to use this reset strategy. This sequence performs a reset of CPU and peripherals and halts the CPU before executing instructions of the user program. It is the recommended reset sequence for Analog Devices ADuC7xxx MCUs and works with these devices only.

This information is applicable to the following devices:

• Analog ADuC7020x62

• Analog ADuC7021x32

• Analog ADuC7021x62

• Analog ADuC7022x32

• Analog ADuC7022x62

• Analog ADuC7024x62

• Analog ADuC7025x32

• Analog ADuC7025x62

• Analog ADuC7026x62

• Analog ADuC7027x62

• Analog ADuC7030

• Analog ADuC7031

• Analog ADuC7032

• Analog ADuC7033

• Analog ADuC7128

• Analog ADuC7129

• Analog ADuC7229x126

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5.2 ATMEL

5.2.1 AT91SAM7

5.2.1.1 Reset strategy

It is recommended to use this reset strategy. This special reset strategy resets the peripherals by writing to the RSTC_CR register. Reseting the peripherals puts all peripherals in the defined reset state. This includes memory mapping register, which means that after reset flash is mapped to address 0. It is also possible to achieve the same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.

This information is applicable to the following devices:

• AT91SAM7S (all devices)

• AT91SAM7SE (all devices)

• AT91SAM7X (all devices)

• AT91SAM7XC (all devices)

• AT91SAM7A (all devices)

5.2.1.2 Memory mapping

Either flash or RAM can be mapped to address 0. After reset flash is mapped to address 0. In order to map RAM to address 0, a 1 can be written to the RSTC_CR register. Unfortunately, this remap register is a toggle register, which switches between RAM and flash with every time bit zero is written.

In order to achieve a defined mapping, there are two options:

1. Use the software reset described above.

2. Test if RAM is located at 0 using multiple read/write operations and testing the results.

Clearly 1. is the easiest solution and is recommended.

This information is applicable to the following devices:

• AT91SAM7S (all devices)

• AT91SAM7SE (all devices)

• AT91SAM7X (all devices)

• AT91SAM7XC (all devices)

• AT91SAM7A (all devices)

5.2.2 AT91SAM9

These devices are based on ARM926EJ-S core. All devices of this family are supported by J-Link.

5.2.2.1 JTAG settings

We recommend using adaptive clocking.

This information is applicable to the following devices:

• AT91RM9200

• AT91SAM9260

• AT91SAM9261

• AT91SAM9262

• AT91SAM9263

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5.3 NXP

5.3.1 LPC

5.3.1.1 Fast GPIO bug

The values of the fast GPIO registers can not be read direct via JTAG from a debugger. The direct access to the registers corrupts the returned values. This means that the values in the fast GPIO registers normally can not be checked or changed from a debugger.

Solution / Workaround

J-Link supports command strings which can be used to read a memory area indirect. Indirectly reading means that a small code snippet will be written into RAM of the target device, which reads and transfers the data of the specified memory area to the debugger. Indirectly reading solves the fast GPIO problem, because only direct register access corrupts the register contents.

Define a 256 byte aligned area in RAM of the LPC target device with the J-Link command map ram and define afterwards the memory area which should be read indirect with the command map indirectread to use the indirectly reading feature of J-Link. Note that the data in the defined RAM area is saved and will be restored after using the RAM area.

This information is applicable to the following devices:

• LPC2101

• LPC2102

• LPC2103

• LPC213x/01

• LPC214x (all devices)

• LPC236x (all devices)

Example

J-Link commands line options can be used for example with the C-Spy debugger of the IAR Embedded Workbench. Open the Project options dialog and select Debug- ger. Select Use command line options in the Extra Options tap and enter in the textfield --jlink_exec_command "map ram 0x40000000-0x40003fff; map indirec- tread 0x3fffc000-0x3fffcfff" as shown in the screenshot below.

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With these additional commands are the values of the fast GPIO registers in the CSpy debugger correct and can be used for debugging. For more information about JLink command line options refer to subchapter Command strings on page 60.

5.4 ST Microelectronics

5.4.1 STR 71x

These devices are ARM7TDMI based. All devices of this family are supported by J-Link.

5.4.2 STR 73x

These devices are ARM7TDMI based. All devices of this family are supported by J-Link.

5.4.3 STR 75x

These devices are ARM7TDMI-S based. All devices of this family are supported by J-Link.

5.4.4 STR91x

These device are ARM966E-S based. All devices of this family are supported by J-Link.

5.4.4.1 Flash erasing

The devices have 3 TAP controllers built-in. When starting J-Link exe, it reports 3 JTAG devices. A special tool, J-Link STR9 Commander is available to directly access the flash controller of the device. This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall.

5.4.5 STM32

These device are Cortex-M3 based. All devices of this family are supported by J-Link.

5.5 Texas Instruments

5.5.1 TMS470

All devices of this family are supported by J-Link.

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Chapter 6

Hardware

This chapter gives an overview about J-Link / J-Trace specific hardware details, such as the pinouts and available adapters.

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6.1 JTAG Connector

J-Link and J-Trace have a JTAG connector compatible to ARM’s Multi-ICE. The JTAG connector is a 20 way Insulation Displacement Connector (IDC) keyed box header (2.54mm male) that mates with IDC sockets mounted on a ribbon cable.

6.1.1 Pinout

The following table lists the J-Link / J-Trace JTAG pinout.

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

PIN SIGNAL TYPE Description

1VTref Input

This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.

2 Vsupply NC

This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

3nTRST

Output

JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

5TDI

Output

JTAG data input of target CPU.- It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.

7TMS

Output

JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of target CPU.

9TCK

Output

JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.

11 RTCK Input

Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.

13 TDO Input

JTAG data output from target CPU. Typically connected to TDO of target CPU.

15 RESET I/O

Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".

17 DBGRQ NC

This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.

5V-Supply

Output

This pin is used to supply power to some eval boards. Not all JLinks supply power on this pin, only the KS (Kickstart) versions. Typically left open on target hardware.

Table 6.1: J-Link / J-Trace pinout

34 56

78 910

11 12

13 14 15 16

17 18 19 20

VTref

nTRST TDI

TMS TCK

RTCK

TDO RESET

DBGRQ V5-Supply

Vsupply

GND

GND GND

GND

GND GND

GND

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6.1.2 Target board design for JTAG

We strongly advise following the recommendations given by the chip manufacturer. These recommendations are normally in line with the recommendations given in the table Pinout on page 74. In case of doubt you should follow the recommendations given by the semiconductor manufacturer.

6.1.2.1 Pull-up/pull-down resistors

Unless otherwise specified by developer’s manual, pull-ups/pull-downs are recommended to be between 2.2 kOhms and 47 kOhms.

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6.2 Using the JTAG connector with SWD

The J-Link and J-Trace JTAG is also compatible to ARM’s Serial Wire Debug (SWD).

6.2.1 Pin Out

The following table lists the J-Link / J-Trace SWD pinout.

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

PIN SIGNAL TYPE Description

1VTref Input

2 Vsupply NC

This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

Not Used

This pin is not used by J-Link. If the device may also be accessed via JTAG, this pin may be connected to nTRST, otherwise leave open.

Not used

This pin is not used by J-Link. If the device may also be accessed via JTAG, this pin may be connected to TDI, otherwise leave open.

7 SWDIO I/O Single bi-directional data pin.

9SWCLK

Output

Clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.

Not used

This pin is not used by J-Link. This pin is not used by J-Link when operating in SWD mode. If the device may also be accessed via JTAG, this pin may be connected to RTCK, otherwise leave open.

13 SWO

Output

Serial Wire Output trace port. (Optional, not required for SWD communication.)

15 RESET I/O

Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".

Not used

NC This pin is not connected in J-Link.

5V-Supply

Output

This pin is used to supply power to some eval boards. Not all JLinks supply power on this pin, only the KS (Kickstart) versions. Typically left open on target hardware.

Table 6.2: J-Link / J-Trace SWD pinout

34 56

78 910

11 12

13 14 15 16

17 18 19 20

VTref

Not used Not used

SWDIO SWCLK

Not used

SWO RESET

Not used V5-Supply

Vsupply

GND

GND GND

GND

GND GND

GND

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6.3 JTAG+Trace connector

J-Trace provides a JTAG+Trace connector. This connector is a 38-pin mictor plug. It connects to the target via a 1-1 cable.

The connector on the target board should be "TYCO type 5767054-1" or a compatible receptacle. J-Trace supports 4, 8, and 16-bit data port widths with the high density target connector described below.

Target board trace connector

J-Trace can capture the state of signals PIPESTAT[2:0], TRACESYNC and TRACEPKT[n:0] at each rising edge of each TRACECLK or on each alternate rising or falling edge.

6.3.1 Connecting the target board

J-Trace connects to the target board via a 38-pin trace cable. This cable has a receptacle on the one side, and a plug on the other side. Alternatively J-Trace can be connected with a 14-pin JTAG cable.

Warning: Never connect trace cable and JTAG cable at the same time because

this may harm your J-Trace and/or your target.

38 37

Target system

Pin 1 chamfer

J-Trace

JTAG

Trace

JTAG

Target board

Trace

connector

Target board

ARM

Trace cable

Target board

JTAG

connector

J-Trace

JTAG

Trace

JTAG

Target board

Trace

connector

Target board

ARM

JTAG cable

Target board

JTAG

connector

J-Trace

JTAG

Trace

JTAG

Target board

Trace

connector

Target board

ARM

JTAG cable

Target board

JTAG

connector

Trace cable

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6.3.2 Pinout

The following table lists the JTAG+Trace connector pinout. It is compatible with the "Trace Port Physical Interface" described in [ETM], 8.2.2 "Single target connector pinout".

PIN SIGNAL Description

1NC No connect. 2NC No connect. 3NC No connect. 4NC No connect. 5 GND Signal ground. 6 TRACECLK Clocks trace data on rising edge or both edges. 7 DBGRQ Debug request.

8DBGACK

Debug acknowledge from the test chip, high when in debug state.

9 RESET

Open-collector output from the run control to the target system reset.

10 EXTTRIG

Optional external trigger signal to the Embedded trace

Macrocell (ETM). 11 TDO Test data output from target JTAG port. 12 VTRef Signal level reference. 13 RTCK Return test clock from the target JTAG port. 14 VSupply Supply voltage. 15 TCK Test clock to the run control unit from the JTAG port. 16 Trace signal 12 Trace signal. 17 TMS Test mode select from run control to the JTAG port. 18 Trace signal 11 Trace signal. 19 TDI Test data input from run control to the JTAG port. 20 Trace signal 10 Trace signal. 21 nTRST Active-low JTAG reset 22 Trace signal 9 Trace signal. 23 Trace signal 20 Trace signal. 24 Trace signal 8 Trace signal. 25 Trace signal 19 Trace signal. 26 Trace signal 7 Trace signal. 27 Trace signal 18 Trace signal. 28 Trace signal 6 Trace signal. 29 Trace signal 17 Trace signal. 30 Trace signal 5 Trace signal. 31 Trace signal 16 Trace signal. 32 Trace signal 4 Trace signal. 33 Trace signal 15 Trace signal. 34 Trace signal 3 Trace signal. 35 Trace signal 14 Trace signal. 36 Trace signal 2 Trace signal. 37 Trace signal 13 Trace signal. 38 Trace signal 1 Trace signal.

Table 6.3: JTAG+Trace connector pinout

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6.3.3 Assignment of trace information pins between ETM architecture versions

The following table show different names for the trace signals depending on the ETM architecture version.

6.3.4 Trace signals

Data transfer is synchronized by TRACECLK.

6.3.4.1 Signal levels

The maximum capacitance presented by J-Trace at the trace port connector,

including the connector and interfacing logic, is less than 6pF. The trace port lines have a matched impedance of 50.

The J-Trace unit will operate with a target board that has a supply voltage range of

3.0V-3.6V.

6.3.4.2 Clock frequency

For capturing trace port signals synchronous to TRACECLK, J-Trace supports

a TRACECLK frequency of up to 200MHz. The following table shows the TRACECLK frequencies and the setup and hold timing of the trace signals with respect to TRACE-

CLK.

Trace signal ETMv1 ETMv2 ETMv3

Trace signal 1 PIPESTAT[0] PIPESTAT[0] TRACEDATA[0] Trace signal 2 PIPESTAT[1] PIPESTAT[1] TRACECTL Trace signal 3 PIPESTAT[2] PIPESTAT[2] Logic 1 Trace signal 4 TRACESYNC PIPESTAT[3] Logic 0 Trace signal 5 TRACEPKT[0] TRACEPKT[0] Logic 0 Trace signal 6 TRACEPKT[1] TRACEPKT[1] TRACEDATA[1] Trace signal 7 TRACEPKT[2] TRACEPKT[2] TRACEDATA[2] Trace signal 8 TRACEPKT[3] TRACEPKT[3] TRACEDATA[3] Trace signal 9 TRACEPKT[4] TRACEPKT[4] TRACEDATA[4] Trace signal 10 TRACEPKT[5] TRACEPKT[5] TRACEDATA[5] Trace signal 11 TRACEPKT[6] TRACEPKT[6] TRACEDATA[6] Trace signal 12 TRACEPKT[7] TRACEPKT[7] TRACEDATA[7] Trace signal 13 TRACEPKT[8] TRACEPKT[8] TRACEDATA[8] Trace signal 14 TRACEPKT[9] TRACEPKT[9] TRACEDATA[9] Trace signal 15 TRACEPKT[10] TRACEPKT[10] TRACEDATA[10] Trace signal 16 TRACEPKT[11] TRACEPKT[11] TRACEDATA[11] Trace signal 17 TRACEPKT[12] TRACEPKT[12] TRACEDATA[12] Trace signal 18 TRACEPKT[13] TRACEPKT[13] TRACEDATA[13] Trace signal 19 TRACEPKT[14] TRACEPKT[14] TRACEDATA[14] Trace signal 20 TRACEPKT[15] TRACEPKT[15] TRACEDATA[15]

Table 6.4: Assignment of trace information pins between ETM architecture versions

Parameter Min. Max. Explenation

Tperiod 5ns 1000ns Clock period Fmax 1MHz 200MHz Maximum trace frequency Tch 2.5ns - High pulse width Tcl 2. 5 ns - Lo w p u ls e wi dt h

Table 6.5: Clock frequency

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The diagram below shows the TRACECLK frequencies and the setup and hold timing of the trace signals with respect to TRACECLK.

Note: J-Trace supports half-rate clocking mode. Data is output on each edge of the TRACECLK signal and TRACECLK (max) <= 100MHz. For half-rate clocking, the setup and hold times at the JTAG+Trace connector must be observed.

Tsh 2.5ns - Data setup high Thh 1.5ns - Data hold high Tsl 2.5ns - Data setup low Thl 1.5ns - Data hold low

Parameter Min. Max. Explenation

Table 6.5: Clock frequency

Tperiod

Tch Tcl

Tsh Thh Tsl Thl

Full TRACECLK

Half-rate TRACECLK

DATA

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6.4 RESET, nTRST

The TAP controller and ICE logic is reset independently from the ARM core with nTRST (DBGnTRST on synthesizable cores). For the ARM core to operate correctly, it is essential that both signals are asserted after power-up.

The advantage of having separate connection to the two reset signals is that it allows the developer performing software debug to set up breakpoints which are retained by the ICE logic even when the core is reset. (For example, at address 0, to allow the code to be single-stepped as soon as it comes out of reset). This can be particularly useful when first trying to bring up a board with a new ASIC.

You may tie (DBG)nTRST to the core reset, but this removes some of the flexibility and usefulness of the debug tools. What some designers facing similar pin constraints have done is to implement some kind of reset circuit within their device. This typically will assert both nTRST and the core reset for the initial power-on reset, but subsequent 'warm' resets, where the power to the device is maintained, will cause only the core reset to go LOW.

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6.5 Adapters

6.5.1 JTAG 14 pin adapter

An adapter is available to use J-Link / J-Trace with targets using this 14 pin 0.1" mating JTAG connector.

The following table shows the mapping between the 14 pin adapter and the standard 20 pin JTAG interface.

PIN Signal Pin no. on 20 pin JTAG

1VTref 1 2GND GND 3nTRST 3 4GND GND 5TDI 5 6GND GND 7TMS 7 8GND GND 9TCK 9 10 GND GND 11 TDO 13 12 RESET 15 13 VTref 1 14 GND GND

Table 6.6: Mapping between the JTAG 14 pin adapter and 20 pin JTAG interface

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6.5.2 5 Volt adapter

The 5V adapter extends the voltage range of J-Link / J-Trace (and other, pin-compatible JTAG probes) to 5V. Most targets have JTAG signals at voltage levels between

1.2V and 3.3V for J-Link and 3.0V up to 3.6V for J-Trace. These targets can be used with J-Link / J-Trace without a 5V adapter. Higher voltages are common primarily in the automotive sector.

6.5.2.1 Technical data

• 20 pin connector, female (plugs into J-Link / J-Trace)

• 20 pin connector male, for target ribbon cable

• LED shows power status

• Adapter is powered by target

• Power consumption < 20 mA Target supply voltage: 3.3V - 5V

• Maximum JTAG-frequency: 10 MHz

6.5.2.2 Compatibility note

The J-Link 5V adapter is compatible to J-Link revisions 4 or newer and J-Trace. Using an older revision of J-Link together with a 5V adapter will not output a reset signal to your target, because older J-Link versions were not able to drive high level on Reset and TRST to target. To actually determine if your J-Link is compatible to the 5V adapter, you may check whether J-Link outputs a reset signal (active high) to your target CPU.

6.5.2.3 Usage

The 5 volt adapter should be plugged directly into J-Link / J-Trace with the 20-pin female connector. The target ribbon cable is then attached to the 20-pin male connector of the adapter. The picture below shows a J-Link with a connected 5-volt adapter.

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6.6 How to determine the hardware version

To determine the hardware version of your J-Link, the first step should be to look at the label at the bottom side of the unit. J-Links have the hardware version printed on the back label.

If this is not the case with your J-Link, start JLink.exe. As part of the initial message, the hardware version is displayed.

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6.6.1 Differences between different versions

6.6.1.1 Versions 1-3

These J-Links use a 16-bit CISC CPU. Maximum download speed is approximately 150 Kbytes/second.

JTAG speed

Maximum JTAG frequency is 4 MHz; possible JTAG speeds are:

16 MHz / n, where n is 4,5, ..., resutling in speeds of:

4.000 MHz (n = 4)

3.200 MHz (n = 5)

2.666 MHz (n = 6)

2.285 MHz (n = 7)

2.000 MHz (n = 8)

1.777 MHz (n = 9)

1.600 MHz (n = 10)

Adaptive clocking is not supported.

Target Interface

nTRST is open drain + 4K7 pull up RESET is open drain

6.6.1.2 Versions 4

Identical to version 3.0 with the following exception:

Target Interface

nTRST is push-pull type RESET is push-pull type

6.6.1.3 Version 5.0

Uses a 32-bit RISC CPU. Maximum download speed (using DCC) is over 700 Kbytes/second.

JTAG speed

Maximum JTAG frequency is 12 MHz; possible JTAG speeds are:

48 MHz / n, where n is 4,5, ..., resutling in speeds of:

12.000 MHz (n = 4)

9.600 MHz (n = 5)

8.000 MHz (n = 6)

6.857 MHz (n = 7)

6.000 MHz (n = 8)

5.333 MHz (n = 9)

4.800 MHz (n = 10)

Adaptive clocking is supported.

Target Interface

nTRST is push-pull type RESET is push-pull type

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6.6.1.4 Version 5.2

Identical to version 5.0 with the following exception:

Target Interface

nTRST is push-pull type RESET is open drain

6.6.1.5 Version 5.3

Identical to version 5.2 with the following exception:

• 5V target supply current limited 5V target supply (pin 19) of Kick-Start versions of J-Link is current monitored and limited. J-Link automatically switches off 5V supply in case of over-current to protect both J-Link and host computer. Peak current (<= 10 ms) limit is 1A, operating current limit is 300mA.

6.6.1.6 Version 5.4

Identical to version 5.3 with the following exception:

• JTAG interface is 5V tolerant.

6.6.1.7 Version 6.0

Identical to version 5.4 with the following exception:

• Outputs can be tristated (Effectively disabling the JTAG interface)

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6.7 J-Link OEM versions

There are several different OEM versions of J-Link on the market. The OEM versions look different, but use basically identical hardware. Some of these OEM versions are limited in speed, some of these can only be used with certain chips and some of these have certain add-on features enabled, which normally requires license. In any case, it should be possible to use the J-Link software with these OEM versions. However, proper function cannot be guaranteed for OEM versions. SEGGER Microcontroller does not support OEM versions; support is provided by the respective OEM.

6.7.1 List of OEM products

The following table list OEM versions of J-Link as well as the major differences between them and J-Link.

Product Limitation Features

Analog Devices mIDASLink

Works with Analog Devices chips only.

RDI, FlashDL, FlashBP

Atmel SAM-ICE Works with ATMEL chips only. RDI, GDBServer Digi International

Digi JTAG Link

Works with Digi chips only. GDBServer

IAR J-Link -- -IAR J-Link KS -- --

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Page 89

Chapter 7

Background information

This chapter provides background information about JTAG and ARM. The ARM7 and ARM9 architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and the related decode mechanism are greatly simplified compared with microprogrammed Complex Instruction Set Computer (CISC).

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7.1 JTAG

JTAG is the acronym for Joint Test Action Group. In the scope of this document, "the JTAG standard" means compliance with IEEE Standard 1149.1-2001.

7.1.1 Test access port (TAP)

JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can provide access to many test support functions built into a component. It is composed as a minimum of the three input connections (TDI, TCK, TMS) and one output connection (TDO). An optional fourth input connection (nTRST) provides for asynchro-

nous initialization of the test logic.

7.1.2 Data registers

JTAG requires at least two data registers to be present: the bypass and the boundary-scan register. Other registers are allowed but are not obligatory.

Bypass data register

A single-bit register that passes information from TDI to TDO.

Boundary-scan data register

A test data register which allows the testing of board interconnections, access to input and output of components when testing their system logic and so on.

7.1.3 Instruction register

The instruction register holds the current instruction and its content is used by the TAP controller to decide which test to perform or which data register to access. It consist of at least two shift-register cells.

PIN Type Explanation

TCK Input

The test clock input (TCK) provides the clock for the test logic.

TDI Input

Serial test instructions and data are received by the test logic at test data input (TDI).

TMS Input

The signal received at test mode select (TMS) is decoded by the TAP controller to control test operations.

TDO Output

Test data output (TDO) is the serial output for test instructions and data from the test logic.

nTRST

Input (optional)

The optional test reset (nTRST) input provides for asynchronous initialization of the TAP controller.

Table 7.1: Test access port

Page 91

7.1.4 The TAP controller

The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry.

TAP controller state diagram

7.1.4.1 State descriptions

Reset

The test logic is disabled so that normal operation of the chip logic can continue unhindered. No matter in which state the TAP controller currently is, it can change into Reset state if TMS is high for at least 5 clock cycles. As long as TMS is high, the TAP controller remains in Reset state.

Idle

Idle is a TAP controller state between scan (DR or IR) operations. Once entered, this state remains active as long as TMS is low.

DR-Scan

Temporary controller state. If TMS remains low, a scan sequence for the selected data registers is initiated.

IR-Scan

Temporary controller state. If TMS remains low, a scan sequence for the instruction register is initiated.

Capture-DR

Data may be loaded in parallel to the selected test data registers.

Shift-DR

The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock.

Captu re -DR

Rese t

Update-DR

Exit 2-DR

Paus e-DR

Exit 1-DR

Shift-DR

DR-ScanIdle

Update-IR

Exit 2-IR

Paus e- IR

Exit 1-IR

Shift-IR

Capture-IR

IR-Scan

tms=1

tms=0

tms=1

tms=0

tms=1 tms=1

tms=0 tms=0

tms=0 tm s=0

tms=1 tms=1

tms=0 tms=0

tms=1 tms=1

tms=0 tm s=0

tms=1

tms=0 tm s=0

tms=1 tms=1

tms=1 tm s=1

tms=0

tms=1 tms=1tms=0 tms=0

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Exit1-DR

Temporary controller state.

Pause-DR

The shifting of the test data register between TDI and TDO is temporarily halted.

Exit2-DR

Temporary controller state. Allows to either go back into Shift-DR state or go on to Update-DR.

Update-DR

Data contained in the currently selected data register is loaded into a latched parallel output (for registers that have such a latch). The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.

Capture-IR

Instructions may be loaded in parallel into the instruction register.

Shift-IR

The instruction register shifts the values in the instruction register towards TDO with each clock.

Exit1-IR

Temporary controller state.

Pause-IR

Wait state that temporarily halts the instruction shifting.

Exit2-IR

Temporary controller state. Allows to either go back into Shift-IR state or go on to Update-IR.

Update-IR

The values contained in the instruction register are loaded into a latched parallel output from the shift-register path. Once latched, this new instruction becomes the current one. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process.

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7.2 The ARM core

The ARM7 family is a range of low-power 32-bit RISC microprocessor cores. Offering up to 130MIPs (Dhrystone2.1), the ARM7 family incorporates the Thumb 16-bit instruction set. The family consists of the ARM7TDMI, ARM7TDMI-S and ARM7EJ-S processor cores and the ARM720T cached processor macrocell.

The ARM9 family is built around the ARM9TDMI processor core and incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family includes the ARM920T and ARM922T cached processor macrocells.

7.2.1 Processor modes

The ARM architecture supports seven processor modes.

7.2.2 Registers of the CPU core

The CPU core has the following registers:

Processor mode Description

User usr Normal program execution mode. System sys Runs privileged operating system tasks. Supervisor svc A protected mode for the operating system. Abort abt Implements virtual memory and/or memory protection. Undefined und Supports software emulation of hardware coprocessors. Interrupt irq Used for general-purpose interrupt handling. Fast inter-

rupt

fiq Supports a high-speed data transfer or channel process.flash

Table 7.2: ARM processor modes

User/

System

Supervisor Abort Undefined Interrupt

Fast

interrupt

R0 R1 R2 R3 R4 R5 R6 R7 R8

R8_fiq

R9_fiq

R10

R10_fiq

R11

R11_fiq

R12

R12_fiq

R13

R13_svc R13_abt R13_und R13_irq R13_fiq

R14

R14_svc R14_abt R14_und R14_irq R14_fiq

CPSR

SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

Table 7.3: Registers of the ARM core

= indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode.

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The ARM core has a total of 37 registers:

• 31 general-purpose registers, including a program counter. These registers are 32 bits wide.

• 6 status registers. These are also 32 bits wide, but only 12 bits are allocated or need to be implemented.

Registers are arranged in partially overlapping banks, with a different register bank for each processor mode. At any time, 15 general-purpose registers (R0 to R14), one or two status registers, and the program counter are visible.

7.2.3 ARM / Thumb instruction set

An ARM core starts execution in ARM mode after reset or any type of exception. Most (but not all) ARM cores come with a secondary instruction set, called the Thumb instruction set. The core is said to be in Thumb mode if it is using the thumb instruction set. The thumb instruction set consists of 16-bit instructions, where the ARM instruction set consists of 32-bit instructions. Thumb mode improves code density by approximately 35%, but reduces execution speed on systems with high memory bandwidth (because more instructions are required). On systems with low memory bandwidth, Thumb mode can actually be as fast or faster than ARM mode. Mixing ARM and Thumb code (interworking) is possible.

J-Link / J-Trace fully supports debugging of both modes without limitation.

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7.3 EmbeddedICE

EmbeddedICE is a set of registers and comparators used to generate debug exceptions (such as breakpoints).

EmbeddedICE is programmed in a serial fashion using the ARM core controller. It consists of two real-time watchpoint units, together with a control and status register. You can program one or both watchpoint units to halt the execution of instructions by ARM core. Two independent registers, debug control and debug status, provide overall control of EmbeddedICE operation.

Execution is halted when a match occurs between the values programmed into EmbeddedICE and the values currently appearing on the address bus, data bus, and various control signals. Any bit can be masked so that its value does not affect the comparison.

Either of the two real-time watchpoint units can be configured to be a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). You can make watchpoints and breakpoints data-dependent.

EmbeddedICE is additional debug hardware within the core, therefore the EmbeddedICE debug architecture requires almost no target resources (for example, memory, access to exception vectors, and time).

7.3.1 Breakpoints and watchpoints

Breakpoints

A "breakpoint" stops the core when a selected instruction is executed. It is then possible to examine the contents of both memory (and variables).

Watchpoints

A "watchpoint" stops the core if a selected memory location is accessed. For a watchpoint (WP), the following properties can be specified:

• Address (including address mask)

• Type of access (R, R/W, W)

• Data (including data mask).

Software / hardware breakpoints

Hardware breakpoints are "real" breakpoints, using one of the 2 available watchpoint units to breakpoint the instruction at any given address. Hardware breakpoints can be set in any type of memory (RAM, ROM, flash) and also work with self-modifying code. Unfortunately, there is only a limited number of these available (2 in the EmbeddedICE). When debugging a program located in RAM, another option is to use software breakpoints. With software breakpoints, the instruction in memory is modified. This does not work when debugging programs located in ROM or flash, but has one huge advantage: The number of software breakpoints is not limited.

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7.3.2 The ICE registers

The two watchpoint units are known as watchpoint 0 and watchpoint 1. Each contains three pairs of registers:

• address value and address mask

• data value and data mask

• control value and control mask

The following table shows the function and mapping of EmbeddedICE registers.

For more information about EmbeddedICE, see the technical reference manual of your ARM CPU. (www.arm.com)

0x00 3 Debug control

0x01 5 Debug status

0x04 6 Debug comms control register

0x05 32 Debug comms data register

0x08 32 Watchpoint 0 address value

0x09 32 Watchpoint 0 address mask

0x0A 32 Watchpoint 0 data value

0x0B 32 Watchpoint 0 data mask

0x0C 9 Watchpoint 0 control value

0x0D 8 Watchpoint 0 control mask

0x10 32 Watchpoint 1 address value

0x11 32 Watchpoint 1 address mask

0x12 32 Watchpoint 1 data value

0x13 32 Watchpoint 1 data mask

0x14 9 Watchpoint 1 control value

0x15 8 Watchpoint 1 control mask

Table 7.4: Function and mapping of EmbeddedICE registers

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7.4 Embedded Trace Macrocell (ETM)

Embedded Trace Macrocell (ETM) provides comprehensive debug and trace facilities for ARM processors. ETM allows to capture information on the processor's state without affecting the processor's performance. It can be configured in software to store trace information only after a specific sequence of conditions. When the trigger condition occurs the trace capture stops after a programmable period. The trace information is exported immediately after it has been captured through a special trace port.

J-Trace has a 2 Mbyte trace memory buffer to store the exported trace information. A software debugger provides the user interface to J-Trace and the stored trace data. The debugger enables all the ETM facilities and displays the trace information that has been captured. J-Trace can be seamlessly integrated into the IAR Embedded Workbench® IDE. The advanced trace debugging features can be used with the IAR C-SPY debugger.

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7.5 Embedded Trace Buffer (ETB)

The ETB is a small, circular on-chip memory area where trace information is stored during capture. It contains the data which is normally exported immediately after it has been captured from the ETM. The buffer can be read out through the JTAG port of the device once capture has been completed. No additional special trace port is required, so that the ETB can be read via J-Link. The trace functionality via J-Link is is limited by the size of the ETB. While capturing runs, the trace information in the buffer will be overwritten every time the buffer size has been reached.

The result of the limited buffer size is that not more data can be traced than the buffer can hold. Throu this limitation is an ETB not in every case an fully-fledged alternative to the direct access to an ETM via J-Trace.

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7.6 Flash programming

J-Link / J-Trace comes with a DLL, which allows - amongst other functionalities reading and writing RAM, CPU registers, starting and stopping the CPU, and setting breakpoints. The standard DLL does not have API functions for flash programming. However, the functionality offered can be used to program the flash. In that case, a flashloader is required.

7.6.1 How does flash programming via J-Link / J-Trace work ?

This requires extra code. This extra code typically downloads a program into the RAM of the target system, which is able to erase and program the flash. This program is called RAM code and "knows" how to program the flash; it contains an implementation of the flash programming algorithm for the particular flash. Different flash chips have different programming algorithms; the programming algorithm also depends on other things such as endianess of the target system and organization of the flash memory (for example 1 * 8 bits, 1 * 16 bits, 2 * 16 bits or 32 bits). The RAM code requires data to be programmed into the flash memory. There are 2 ways of supplying this data: Data download to RAM or data download via DCC.

7.6.2 Data download to RAM

The data (or part of it) is downloaded to an other part of the RAM of the target system. The Instruction pointer (R15) of the CPU is then set to the start address of the Ram code, the CPU is started, executing the RAM code. The RAM code, which contains the programming algorithm for the flash chip, copies the data into the flash chip. The CPU is stopped after this. This process may have to be repeated until the entire data is programmed into the flash.

7.6.3 Data download via DCC

In this case, the RAM code is started as described above before downloading any data. The RAM code then communicates with the host computer (via DCC, JTAG and J-Link / J-Trace), transferring data to the target. The RAM code then programs the data into flash and waits for new data from the host. The WriteMemory functions of JLink / J-Trace are used to transfer the RAM code only, but not to transfer the data. The CPU is started and stopped only once. Using DCC for communication is typically faster than using WriteMemory for RAM download because the overhead is lower.

7.6.4 Available options for flash programming

There are different solutions available to program internal or external flashes connected to ARM cores using J-Link / J-Trace. The different solutions have different fields of application, but of course also some overlap.

7.6.4.1 J-Flash - Complete flash programming solution

J-Flash is a stand-alone Windows application, which can read / write data files and program the flash in almost any ARM system. J-Flash requires an extra license from SEGGER.

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100 CHAPTER 7 Background information

1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

7.6.4.2 JLinkArmFlash.dll - A DLL with flash programming capabilities

An enhanced version of the JLinkARM.DLL, which has add. API functions. The additional API functions allow loading and programming a data file. This DLL comes with a sample executable, as well as the source code of this executable and a project file.

This can be an interesting option if you want to write your own programs for production purposes. This DLL also requires an extra license from SEGGER; contact us for more information.

Output of Sample program:

SEGGER JLinkARMFlash for ST STR710FR2T6 V1.00.00 Compiled 11:16:22 on May 4 2005.

Connecting to J-Link Resetting target Loading data file... 1060 bytes loaded. Erasing required sectors... O.K. - Completed after 0.703 sec Programming... O.K. - Completed after 0.031 sec Verifying... O.K. - Completed after 0.031 sec

7.6.4.3 RDI flash loader: Allows flash download from any RDI-compliant tool chain

RDI, (Remote debug interface) is a standard for "debug transfer agents" such as JLink. It allows using J-Link from any RDI compliant debugger. RDI by itself does not include download to flash. To debug in flash, you need to somehow program your application program (debuggee) into the flash. You can use J-Flash for this purpose, use the flash loader supplied by the debugger company (if they supply a matching flash loader) or use the flash loader integrated in the J-Link RDI software. The RDI software as well as the RDI flash loader require licenses from SEGGER.

7.6.4.4 Flash loader of compiler / debugger vendor such as IAR

A lot of debuggers (some of them integrated into an IDE) come with their own flash loaders. The flash loaders can of course be used if they match your flash configuration, which is something that needs to be checked with the vendor of the debugger.

7.6.4.5 Write your own flash loader

Implement your own flash loader using the functionality of the JLinkARM.dll as described above. This can be a time consuming process and requires in-depth knowledge of the flash programming algorithm used as well as of the target system.