Scenix SX Series, SX20AC75, SX20AC, SX18AC, SX28AC User Manual

...

Download

www .scenix.com

Scenix™

SX Family

User’s Manual

SX User’s Manual Rev. 3.1

www. scenix.com

Revision History

REVISION RELEASE DATE SUMMARY OF CHANGES

2.0 February 1 1, 1999 Updated to include SX48/52BD devices

2.01 June 14, 1999 Conyents the same as Rev 2.0 but removed the last chapter (Device Programming)

2.1 May 19, 1999 Updated to reflect the new revision of the SX18/20/28 AC devices (datecode Axyywwxx)

2.2 June 4, 1999 Deleted the recommended component values associated with resonator/crystal oscillator. This information is available in the datasheets.

3.0 January 21, 2000 Updated to reflect the latest revision of the SX48/52BD (Production Part)

3.1 August 24, 2000 Updated to correct errata sheet items.

©2000 Scenix Semiconductor, Inc. All rights reserved. No warranty is provided and no liability is assumed by Scenix Semiconductor with respect to the accuracy of this documentation or the merchantability or fitness of the product for a particular application. No license of any kind is conveyed by Scenix Semiconductor with respect to its intellectual property or that of others. All information in this document is subject to change without notice.

Scenix Semiconductor products are not authorized for use in life support systems or under conditions where failure of the product would endanger the life or safety of the user, except when prior written approval is obtained from Scenix Semiconductor.

Scenix™ and the Scenix logo are trademarks of Scenix S em iconductor, Inc. Virtual Peripheral™

C™ is a trademark of Philips Corpor ation Microwire™ is a tradema rk of National Semicondu ctor Corporation All other trademarks mentioned in this document are property of their respective companies.

is a trademark of Scenix Semiconductor, Inc.

Scenix Inc., 1330 Charleston Road, Mountain View, CA 94043, USA Telephone: +1 650 210 1500, Fax: +1 650 210 8715, Web site: www. scenix.com, E-mail: sales@scenix.com

SX User’s Manual Rev. 3.1

www. s ce nix.com

SX User’s Manual Rev. 3.1

www.scenix.com Contents

Contents

Chapter 1 Overview

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 The Virtual Peripheral Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 The Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.6 P rogramming and Debugging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.8 P art Numbers and Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 2 Architecture

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.2 SX18/20/28AC and SX18/20/28AC75 Addressing Modes and

FSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 SX48/52BD Addressing Modes and FSR Register . . . . . . . . . . . . . . . . . 17

2.3.4 Register Access Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.1 W (Working Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.2 INDF (Indirect through FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.3 RTCC (Real-Time Clock/Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.4 PC (Program Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.5 STATUS (Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.4.6 FSR (File Select Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4.7 RA through RE (Port Data Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4.8 Port Control Registers and MODE Register . . . . . . . . . . . . . . . . . . . . . . 26

2.4.9 OPTION (Device Option Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.5 Instruction Execution Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.2 Pipeline Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.5.3 Read-M o dify-Writ e Co n siderations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6 P rogram Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6.1 Test and Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6.2 Jump Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6.3 Jump Indirect and Jump Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.6.4 Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.6.5 Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SX User’s Manual Rev. 3.1

2.7 Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.8 Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 3 Instruction Set

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.2 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.1 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.2 Arithmetic and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.3 Bitwise Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.4 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.5 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.6 System Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4 Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.5 Equivalent Assembler Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6 Detailed Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6.1 ADD fr,W Add W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.6.2 ADD W,fr Add fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6.3 AND fr,W AND of fr and W into fr . . . . . . . . . . . . . . . . . . . 69

3.6.4 AND W,fr AND of W and fr into W . . . . . . . . . . . . . . . . . . . 70

3.6.5 AND W,#lit AND of W and Literal into W . . . . . . . . . . . . . . . 71

3.6.6 BANK addr8 Load Bank Number into FSR(6:4) . . . . . . . . . . . . 72

3.6.7 CALL add r 8 Call Subr outine . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4

3.6.8 CLR fr Clear fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.6.9 CLR W Clear W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.6.10 CLR !WDT Clear Watchdog Timer . . . . . . . . . . . . . . . . . . . . . 78

3.6.11 CLRB fr.bit Clear Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6.12 DEC fr Decrement fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.6.13 DECSZ fr Decrement fr and Skip if Zero . . . . . . . . . . . . . . . 81

3.6.14 INC fr Increment fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.6.15 INCSZ fr Increment fr and Skip if Zero . . . . . . . . . . . . . . . 83

3.6.16 IREAD Read Word from Instruction Memory . . . . . . . . . 84

3.6.17 JMP addr 9 Jump to Address . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.6.18 MOV fr,W Move W to fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.6.19 MOV M,#l i t Move Literal to MODE Re g i st er . . . . . . . . . . . . . 88

3.6.20 MOV M,W Move W to MODE Register . . . . . . . . . . . . . . . . 89

3.6.21 MOV !OPTION,W Move W to OP TI O N Re g i st er . . . . . . . . . . . . . . . 90

3.6.22 MOV !rx,W Move Data Between W and Control Register . . . 91

3.6.23 MOV W,fr Move fr to W . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.6.24 MOV W,/fr Move Complement of fr to W . . . . . . . . . . . . . . . 94

3.6.25 MOV W,fr-W Move (fr-W) to W . . . . . . . . . . . . . . . . . . . . . . . . 95

3.6.26 MOV W,-- fr Mov e (fr-1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 9 6

3.6.27 MOV W,++fr Move (fr+1) to W . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.6.28 MOV W,<<fr Rotate fr Left through Carry and Move to W . . . 98

3.6.29 MOV W,>>fr Rotate fr Right through Carry and Move to W . . 99

3.6.30 MOV W,<>fr Swap High/Low Nibbles of fr and Move to W . 100

3.6.31 MOV W,#li t Move Li teral to W . . . . . . . . . . . . . . . . . . . . . . . 101

www. s ce nix.comContents

SX User’s Manual Rev. 3.1

www.scenix.com Contents

3.6.32 MOV W,M Move MODE Re g i st e r to W . . . . . . . . . . . . . . . 102

3.6.33 MOVSZ W, --fr Move (fr-1) to W and Skip if Zero . . . . . . . . . . 103

3.6.34 MOVSZ W, ++fr Move (fr+1) to W and Skip if Zero . . . . . . . . . . 104

3.6.35 NOP No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.6.36 NOT fr Complement of fr into fr . . . . . . . . . . . . . . . . . . 106

3.6.37 OR fr,W OR of fr and W into fr . . . . . . . . . . . . . . . . . . . . 107

3.6.38 OR W,fr OR of W and fr into W . . . . . . . . . . . . . . . . . . . 108

3.6.39 OR W,#lit OR of W and Literal into W . . . . . . . . . . . . . . . 109

3.6.40 PAGE addr12 Load Page Number into STATUS(7:5) . . . . . . . 110

3.6.41 RET Return from Subroutine . . . . . . . . . . . . . . . . . . . 111

3.6.42 RETI Return from Interrupt . . . . . . . . . . . . . . . . . . . . . 112

3.6.43 RETIW Return from Interrupt and Adjust RTCC with

W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.6.44 RETP Return from Subroutine Across Page Boundary 114

3.6.45 RETW lit Return from Subroutine with Literal in W . . . . . 115

3.6.46 RL fr Rotate fr Left through Carry . . . . . . . . . . . . . . . 116

3.6.47 RR fr Rotate fr Right through Carry . . . . . . . . . . . . . . 117

3.6.48 SB fr.bit Test Bit in fr and Skip if Set . . . . . . . . . . . . . . . 118

3.6.49 SETB fr.bit Set Bit in fr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.6.50 SLEEP Power D o w n Mo d e . . . . . . . . . . . . . . . . . . . . . . 12 0

3.6.51 SNB fr.bit Test Bit in fr and Skip if Clear . . . . . . . . . . . . . . 121

3.6.52 SUB fr,W Subtract W from fr . . . . . . . . . . . . . . . . . . . . . . . 122

3.6.53 SWAP fr Swap High/Low Nibbles of fr . . . . . . . . . . . . . . 124

3.6.54 TEST fr Test fr for Zero . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.6.55 XOR fr,W XOR of fr and W into fr . . . . . . . . . . . . . . . . . . . 126

3.6.56 XOR W,fr XOR of W and fr into W . . . . . . . . . . . . . . . . . . 127

3.6.57 XOR W,#lit XOR of W and Literal into W . . . . . . . . . . . . . . 128

Chapter 4 Clocking, Power Down, and Reset

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.2 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.2.1 C lock/Instruction Rate Option (Compatible or Turbo Mode) . . . . . . . . 129

4.2.2 Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.2.3 External RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.2.4 External Crystal/Resonator (XT, LP, or HS Mode) . . . . . . . . . . . . . . . . 131

4.2.5 External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4.3 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.3.1 Entering the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.3.2 Waking Up from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 134

4.4 Multi-Input Wakeup/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.4.1 Port B Configuration for Multi-Input Wakeup/Interrupt . . . . . . . . . . . . 134

4.4.2 Reading and Writing the Wakeup Pending Bits . . . . . . . . . . . . . . . . . . 137

4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

4.5.1 Register States Upon Different Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 138

4.5.2 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.5.3 Wakeup from the Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4.5.4 Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

SX User’s Manual Rev. 3.1

4.5.5 Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

4.5.6 MCLR Input Signal (Master Clear Reset) . . . . . . . . . . . . . . . . . . . . . . . 142

Chapter 5 Input/Output Ports

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.2 Reading and Writing the Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.3 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

5.3.1 Accessing the Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.2 MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.3 Port Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.4 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.5 Port Configuration Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.3.6 Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Chapter 6 Tim ers an d Interru p t s

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.2 Real- T ime Clock/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.2.1 Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

6.2.2 Maximum Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

6.2.3 RTCC Operation as a Real-Time Clock or Timer . . . . . . . . . . . . . . . . . 153

6.2.4 RTCC Operation as an Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 153

6.2.5 RTCC Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

6.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6.3.1 Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6.3.2 Watchdog Operation in the Power Down Mode . . . . . . . . . . . . . . . . . . 155

6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.4.1 Single-Level Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.4.2 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.4.3 RTCC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.4.4 Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.4.5 Device-Specific Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.4.6 Return -f rom-Int errupt Ins t ru c t ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.4.7 Interrupt Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

www. s ce nix.comContents

Chapter 7 Analog Comparator

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

7.2 Comparator Enable/Status Register (CMP_B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

7.2.1 Accessing the CMP_B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.3 Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

SX User’s Manual Rev. 3.1

www.scenix.com Contents

Chapter 8 Multi-Function Timers

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

8.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

8.2.1 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

8.2.2 Software Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

8.2.3 External Event Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

8.2.4 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

8.3 Timer Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

8.4 Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

8.4.1 Timer T1 Control A Register (T1CNTA) . . . . . . . . . . . . . . . . . . . . . . . 169

8.4.2 Timer T1 Control B Register (T1CNTB) . . . . . . . . . . . . . . . . . . . . . . . 170

8.4.3 Timer T2 Control A Register (T2CNTA) . . . . . . . . . . . . . . . . . . . . . . . 171

8.4.4 Timer T2 Control B Register (T2CNTB) . . . . . . . . . . . . . . . . . . . . . . . 172

SX User’s Manual Rev. 3.1

www. s ce nix.comContents

List of Figures

Figure 1-1 SX18/20/28 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 1-2 SX48/52BD Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 1-3 Part Numbering Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2-1 SX28AC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 2-2 Regist er Access Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2-3 Program Counter Loading for Jump Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 2-4 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 2-5 Stack Operation for a “Call” Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 2-6 Stack Operation for a “Return” Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 2-7 Devi ce Co n figuratio n Re g i ster Forma t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8

Figure 3-1 Program Counter Loading for Call Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 3-2 Rotate fr Left Through Carry into W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 3-3 Rotate fr Right Through Carry into W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 3-4 Rotate fr Left Through Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 3-5 Rotate fr Right Through Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-1 External RC Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 4-2 Cryst a l o r Ceramic Res o n a t o r Co n n e ct ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 2

Figure 4-3 External Clock Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-5 On-Chip Reset Circuit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 4-6 Power-On Reset Timing, Fast VDD Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 4-7 Power-On Reset Timing, VDD Rise Time Too Slow . . . . . . . . . . . . . . . . . . . . 141

Figur e 4-8 Ext e rnal Pow er-On MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 4-9 Power-On Reset Timing, Separate MCLR Signal . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 5-1 Port B Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 6-1 RTCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 6-2 Interrupt Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 7-1 Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 8-1 Multi-Function Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

SX User’s Manual Rev. 3.1

www.scenix.com Contents

List of Tables

Table 1-1 Device P a ck a g e Na m e s .. ................ ........ ......... ........ ................ ........ ........ ........ ............17

Table 1-2 Pin Desc ri p t i o n s ........... ........ ................ ......... ........ ........ ................ ........ ........ ........ .. ....20

Table 2-1 SX18/20/28AC and SX18/20/28AC75 RAM Register Map ......................................24

Table 2-2 Regist e r S u mmary .......... ........ ........ ................. ........ ........ ........ ................ ........ ........ ....30

Table 2-3 STATUS Register Bits ................................................................................................32

Table 2-4 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75 ........................35

Table 2-5 MODE Register Settings for SX48/52BD ..................................................................36

Table 2-6 Prescaler Divide-By Factors .......................................................................................38

Table 2-7 Pipeline Execution Sequence ......................................................................................39

Table 2-8 Return-from-Subroutine/Interrupt Instructions ...........................................................45

Table 2-9 FUSE Word Register Configuration Bits for SX18/20/28AC ....................................49

Table 2-10 FUSEX Word Register Configuration Bits for SX18/20/28AC &

SX18/20/28AC75 ....... ........ ........ ........ ................. ........ ........ ........ ................ ........ ........51

Table 2-11 FUSE Word Configuration Bits for SX48/52BD .......................................................52

Table 2-12 FU SE X Wo rd Re g i ster Confi g u ration Bits fo r SX48/52BD .......... ........ ........ ........ ....54

Table 3-1 Logic Instructions .......................................................................................................60

Table 3-2 Arithmetic and Shift Instructions ................................................................................60

Table 3-3 Bitwise Operation Instructions ...................................................................................61

Table 3-4 Data Move m e n t In structio n s .. ................ ......... ........ ........ ................ ........ ........ ........ ....61

Table 3-5 Program Control Instructions ......................................................................................63

Table 3-6 System Control Instructions ........................................................................................63

Table 3-7 Equivalent Assembler Mnemonics .............................................................................64

Table 3-8 Key to Abbreviations and Symbols ............................................................................66

Table 4-1 Register States Upon Different Resets ......................................................................139

Table 5-1 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75 ......................146

Table 5-2 MODE Register Settings for SX48/52BD ................................................................146

Table 6-1 Watchdog Timeout Settings ......................................................................................155

Table 8-1 Timer T1/T2 Pin Assignments ..................................................................................168

Table 8-2 T1CNTA Reg ister Bits .......... ........ ........ ......... ................ ........ ........ ........ ................ ..169

Table 8-3 T1CNTB Register Bits ..............................................................................................170

Table 8-4 T2CNTA Reg ister Bits .......... ........ ........ ......... ................ ........ ........ ........ ................ ..171

Table 8-5 T2CNTB Register Bits ..............................................................................................172

SX User’s Manual Rev. 3.1

www. s ce nix.comContents

SX User’s Manual Rev. 3.1

www .scenix.com

Chapter 1

Overview

1.1 Introduc t io n

The Scenix SX family of configurable communications controllers are fabricated in an advanced CMOS process technology. The advanced process, c ombined with a RI SC-base d ar chitecture, a llows high-speed computation, flexible I/O control, and efficient data manipulation. Throughput is enhanced by operating the device at frequencies up to 100 MHz and by optimizing the instruction set to include mostly single-cycle instructions. In addition, the SX architecture is deterministic and totally reprogramable. The unique combination of these characteristics enables the device to implement realtime functions as software modules (Virtual PeripheralTM) to replace traditional hardware functions.

On-chip core functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a brown-out detector, a watchdog timer, a power-save mode with multi-source wakeup capability, an internal R/C oscillator, user- selectab le clock modes, and high-current outputs. Additional fe atures are provided by individual members of the SX family according to the system requirements, such as PWM timers and additional I/O ports.

1.2 Key Features

50/75/100 MIPS Performance

• DC - 100 MHz operation

• 10 ns instruction cycle, 30 ns internal interrupt response at 100 MHz

• 1 instruction per clock (branches 3)

EE/FLASH Program Memory and SRAM Data Memory

• Access time of < 10 ns provides single cycle access

• EE/Flash rated for > 10,000 rewrite cycles

• SX18/20/28AC and SX18/20/28AC75:

– 2048 words of EE/Flash program memory – 136 bytes of SRAM data memory

• SX48/52BD:

– 4096 words of EE/Flash program memory – 262 bytes of SRAM data memory

SX User’s Manual Rev. 3.1

CPU Features

• Compact instruction set

• All instructions are single cycle except branch

• Eight-level push/pop hardware stack for subroutine linkage

• Fast table lookup capability through run-time readable code (IREAD instruction)

• Predictable program execution flow for hard real-time applications

Fast and Deterministic Interru p t

• Jitter-free 3-cycle internal interrupt response

• Hardware context save/restore of key resources such as PC, W, STATUS, and FSR

cycle interrupt res pon se t ime

• External wakeup/interrupt capability on Port B (8 pins)

Flexible I/O

• All pins individually programmable as I/O

• Inputs are TTL or CMOS level selectable

• All pins have selectable internal pull-ups

• Selectable Schmitt Trigger inputs on Ports B, C, D, and E

• All outputs capable of sourcing/sinking 30 mA

• Port A outputs have symmetrical drive

• Analog comparator support on Port B (RB0 OUT, RB1 IN-, RB2 IN+)

• I/O operation synchronous to the oscillator clock (user selectable)

www. s ce nix.comChapter1 Overview

within the 3-

Hardware Peripheral Features

• Two 16-bit timers with 8-bit prescalers supporting (SX48/52BD devices only):

– Software Timer mode – PWM mode – Simultaneous PWM/Capture mode – External Event mode

• One 8-bit Real Time Clock/Counter (RTCC) with programable 8-bit prescaler

• Watchdog Timer (shares the RTCC prescaler)

• Analog comparator

• Brown-out detector

• Multi-Input Wakeup logic on 8 pins

• Internal RC oscillator with configurable rate from 31.25 KHz to 4 MHz

• Power-On-Reset

Packages

• SX18/2028AC and SX18/20/28AC75: 18pin SO/DIP, 20-pin SSOP, 28-pin SO/DIP

• SX48/52BD family: 48-pin Tiny PQFP, and 52-pin PQFP

• SX52BD75: 52-pin PQFP

• SX52BD100: 52-pin PQFP

SX User’s Manual Rev. 3.1

www.scenix.com Chapt er 1 Ov er v ie w

Programming and Debugging Support

• On- chip in-system programming support through serial or parallel interface

• In-system serial programming via oscillator pins

• On-chip in-system debugging support logic

• Real-time emulation, full program debug, and integrated development environment offered by third

party tool vendors

Software Support

• Library of off-the-shelf Virtual Peripheral modules

• Examples of Virtual Peripheral integration

• Evaluation Kits for communication intensive applications

1.3 Architectur e

The SX devices use a modified Harva rd architecture. This architectur e uses two separate memories with separate address buses, one for the pr ogram and one for data, while allowing transfer of data from program memory to SRAM. This ability allows accessing data tables from program memory. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped with a multi-stage pipeline, which means the next instruction can be fetched from program memory while the current instruction is being executed using data from the data memory.

Scenix has developed a revolutionary RISC-based architecture and me mory desi gn techniques that is 20 times faster than conventional MCUs, deterministic, jitter free, and totally reprogramable.

The SX family implements a four-stage pipeline (fetch, decode, execute, and write back), which results in execution of one instruction per clock cycle. At the operating frequency of 100 MHz, instructions are executed at the rate of one per 10-ns clock cycle.

1.4 The Virtual Peripheral Concept

Virtual Peripheral concept enables the “soft ware system on a chip” appr oach. Virtual Peripheral, a software module that replaces a tr aditional har dwar e per ipher al, takes advantage of the Scenix architecture’s high performance and deterministic nature to produce same results as the hardware peripheral with much greater flexibility.

The speed and flexibility of the Scenix architecture complemented with the availability of the Virtual Peripheral library, simultaneously address a wide range of engineering and product development concerns. They decrease the product development cycle dramatically, shortening time to production to as little as a few days.

Scenix’s time-saving Virtual Peripheral library gives the system designers a choice of ready-made solutions, or a head start on developing their own peripherals. So, with Virtual Peripheral modules handling established functions, design engineers can concentrate on adding value to other areas of the application.

The concept of Virtual Peripheral combined with in-system re-programmability provides a powerful development platform ideal for the communications industry because of the numerous and rapidly evolving standards and protocols.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter1 Overview

Overall, the concept of Virtual Peripheral provides benefits such as using a more simple device, reduced component count, fast time to production, increased flexibility in design, customization to your application, and ultimately overall system cost reduction.

Some examples of Virtual Peripheral modules are:

• Communication interfaces such as I2C™, Microwire/Plus™ , SPI, IrDA stack, UART, and Modem

functions

• Internet Connectivity protocols such as UDP, TCP/IP stack, HTTP, SMTP, POP3

• Frequency generation and measurement

• PPM/PWM generation

• Delta/Sigma ADC

• DTMF generation/detection

• PSK/FSK generation/detection

• FFT/DFT based algorithms

1.5 The Communications Controller

The combination of the Scenix hardware architecture and the Virtual Peripheral concept create a powerful, creative platform for the communications design communities: SX communications controller. Its high processing power, re-cofigurability, cost-effectiveness, and overall design freedom give the designer the power to build products for the future with the c onfidence of knowing that they can keep up with innovation in standards and other areas.

1.6 Progr amming and D ebugging Support

The SX devices are currently supported by third party tool vendors. On-boar d in-system de bug capabilities have been added, allowing tools to provide an integrated development environment including editor, macro assembler, debugger, and programmer. Un-obtrusive in-system programming is provided through the OSC pins. For emulation purposes, there is no need for a bond-out chip, so the user does not have to worry about the potential variations in electrical characteristics of a bond-out chip and the actual chip used in the target application. The user can test and revise the fully debugged code in the actual SX, in the actual application, and get to production much faster.

1.7 Applications

Emerging applications and advances in existing ones require higher performance while maintaining low cost and fast time-to-production.

The SX device provides solutions for many fa miliar applications such as process controllers, electronic appliances/tools, security/monitoring systems, consumer automotive, sound generation, motor control, and personal communication devices. In addition, the device is suitable for applications that require DSP-like capabilities, such as closed-loop servo control (digital filters), digital answering machines, voice notation, interactive toys, and magnetic-stripe readers.

SX User’s Manual Rev. 3.1

www.scenix.com Chapt er 1 Ov er v ie w

Furthermore, the growing Virtual Peripheral library features new components, such as the Internet Protocol stack, and communication interfaces, that allow design engineers to embed Inter net connectivity into all of their products at extremely low cost and very little effort.

Scenix’s complete network connectivity protocol stack implementation (SX-Stack), enables singlechip Web servers and E-mail appliances in embedded applications. The implementation includes the physical layer interface with the TCP/IP network connectivity protocols, enabling system designers to produce cost-effective embedded Internet devices without external physical access or a gateway PC.

The hardware platform for SX-Stack is the SX52BD communications controller. The device allows implementation of the entire TCP/IP protocols, physical interface, and other relevant high-speed communication interfaces as Virtual Peripheral modules.

1.8 Part Numbers and Pinout Diagrams

This user’s guide describes the following Scenix SX devices:

• SX18AC/SX20AC/ SX28AC and SX18AC75/SX20AC75/SX28AC75 devices (with 2K program memories)

• SX48BD/SX52BD devices (with 4K program memories and multi-function timers)

The SX18AC/20AC/28AC and SX18AC75/SX20AC75/SX28AC75 devices are available in the pin configurations shown in Figure 1-1. These devices are functionally the same except that the 18-pin and 20-pin devices do not have the port pins RC0 through RC7. Therefore, Port C cannot be used in the smaller packages.

RA2

RA3 RTCC MCLR

Vss RB0 RB1 RB2 RB3

SX 18-PIN

1 2 3 4 5 6 7 8

9 DIP/SOIC

18 17 16 15 14 13 12 11 10

RA1 RA0

OSC1 OSC2 Vdd RB7 RB6 RB5 RB4

RA2

RA3 RTCC MCLR

Vss

Vss RB0 RB1 RB2 RB3

SX 20-PIN

1 2 3 4 5 6 7

8 9 10

20 19 18

17 16 15

SSOP

RA1 RA0

OSC1 OSC2 Vdd Vdd RB7 RB6 RB5 RB4

RTCC

Vdd

n.c. Vss n.c.

RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4

SX 28-PIN

1 2 3 4 5 6 7

8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18

17 16 15

MCLR OSC1 OSC2 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5

RTCC

Vss

Vdd

Vdd RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4

Vss

SX 28-PIN

1 2 3 4 5 6 7

8 9 10 11 12 13 14

28 27 26 25 24 23

22 21 20 19 18

17 16 15

MCLR OSC1 OSC2 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5

Figure 1-1 SX18/20/28 Pin Assignments

DIP/SOIC

SX User’s Manual Rev. 3.1

SSOP

www. s ce nix.comChapter1 Overview

The SX48/52BD devices are available in the pin configurations shown in Figure 1-2. These devices are functionally the same except that the 48-pin device does not have the port pins RA4 through R A7. Therefore, the upper four pins of Port A are not available in the smaller package.

RTCC

Vss

Vdd

RE6

RE5

RE4

RE3

RE2

RE1

RE0

RD7

RD6

RD5

RD4

Vss

Vdd

RD3

RD2

RD1

RD0

RC7

RC6

RC5

MCLR OSC1 OSC2

Vdd

Vss RA0 RA1 RA2 RA3 RB0 RB1 RB2

___

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

___

RE7

48 - PIN

TQFP

___

RA6 RA7

MCLR

OSC1 OSC2

Vdd

Vss RA0 RA1 RA2 RA3 RB0 RB1

RB3

RB4

RB5

RA5

RA4

RTCC

___

52 51 50 49 48 47 46 45 44 43 42 41 40

13 14 15 16 17 18 19 20 21 22 23 24 25 26

RB2

RB3

___

RB4

RB6

Vss

RB5

Vdd

RB7

T op View

Vdd

RE7

52 - PIN

PQFP

RB6

RB7

T op View

RE6

Vdd

RC0

RE5

Vss

RC1

RE4

RC0

RC2

RE3

RC1

RC3

RE2

RC2

Vss

RE1

RC3

RC4

RE0

39 38 37 36 35 34 33 32 31 30 29 28 27

_ _ _ _ _ _ _ _ _ _ _ _ _

RC4

RD7 RD6 RD5 RD4 Vss Vdd RD3 RD2 RD1 RD0 RC7 RC6 RC5

SX User’s Manual Rev. 3.1

Figure 1-2 SX48/52BD Pin Assignments

www.scenix.com Chapt er 1 Ov er v ie w

Table 1-1 is a list of the available SX device packages and the corresponding number of pins, number

of I/O pins, program (flash) memory size, and general-purpose RAM size. Use this table as a guide for ordering the parts that fit your requirements.

Table 1-1 Device Package Names

Device Pins I/O

SX18AC/SO SX18AC-I/SO SX18AC75/SO

SX18AC/DP SX18AC-I/DP SX18AC75/DP

SX20AC/SS SX20AC-I/SS SX20AC75/SS

SX28AC/SO SX28AC-I/SO SX28AC75/SO

SX28AC/DP SX28AC-I/DP SX28AC75/DP

SX28AC/SS SX28AC-I/SS SX28AC75/SS

18 18 18

20 20 20

28 28 28

12 12 12

20 20 20

Operating

Frequency (M Hz )

50 50 75

EE/Flash

(Words )

2K 2K 2K

RAM

(Bytes)

136 136 136

Operating

Temp. (°C)

0°C to +70°C

-40°C to +85°C 0°C to +70°C

0°C to +70°C

-40°C to +85°C 0°C to +70°C

0°C to +70°C

-40°C to +85°C 0°C to +70°C

0°C to +70°C

-40°C to +85°C 0°C to +70°C

0°C to +70°C

-40°C to +85°C 0°C to +70°C

0°C to +70°C

-40°C to +85°C 0°C to +70°C

SX48BD/TQ 48 36 50 4K 262 0°C to +70°C SX52BD/PQ 52 40 50 4K 262 0°C to +70°C SX48BD-I/TQ 48 36 50 4K 262 -40°C to +85°C SX52BD-I/PQ 52 40 50 4K 262 -40°C to +85°C SX52BD75/PQ 52 40 75 4K 262 0°C to +70°C SX52BD100/PQ 52 40 100 4K 262 0°C to +70°C

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter1 Overview

Figure 1-3 is a diagram showing the gener al naming conventions for SX family devices. The par t

number consists of several fields that specify the manufacturer, pin count, feature set, memory size, supply voltage, operating temperature range, and package type, as indicated in Figure 1-3.

DP = SDIP SO = SOP

SX18ACXX-I/SO

Package Type

SS = SSOP TQ = Tiny PQFP PQ = PQFP

Feature S et

Pin C ount

SceniX

Extended Tem perature

Speed

Memor

Figure 1-3 Part Numbering Referen ce Guide

Size

Blank = 50 MHz

75 = 75 MHz

100 = 100 MHz

A = 512 word B = 1k word C = 2k word D = 4k word

Blank = 0°C to +70°C

I = -40°C to +85°C

Throughout this manual, the term “SX” refers to all the devices listed in Table 1 - 1 , except where indicated otherwise.

SX User’s Manual Rev. 3.1

www.scenix.com Chapt er 1 Ov er v ie w

1.9 Pin Des crip tio ns

Table 1-2 describes the SX device pins. For each pin, the table shows the pin type (input, output, or

power), the input voltage levels (TTL, CMOS, or Schmitt trigger), and the pin function. Note that not all of these pins are available on all the devices. For example, some devices have fewer I/O pins. Also note that only the core functions of the pins are shown in the table. Some pins have additional f unctions in certain SX devices.

The following abbreviations are used in the table:

• I = device input

• O = device output

• I/O = bidirectional I/O pin

• P = power supply pin

• NA = not applicable

• TTL = TTL input levels

• CMOS = CMOS input levels

• ST = Schmitt trigger input

• MIWU = Multi-Input Wakeup

SX User’s Manual Rev. 3.1

Table 1-2 Pin Descriptions

www. s ce nix.comChapter1 Overview

Name

Type

Input

Levels

Description

RA0-RA7 I/O TTL/CMOS Port A bidirectional I/O pin; symmetrical source / sink

capability

RB0 I/O TTL/CMOS/ST Port B bidirectional I/O pin; MIWU input; comparator

output

RB1 I/O TTL/CMOS/ST Port B bidirectional I/O Pin; MIWU input; comparator

negative input

RB2 I/O TTL/CMOS/ST Port B bidirectional I/O pin; MIWU input; comparator

positive input RB3-RB7 I/O TTL/CMOS/ST Port B bidirectional I/O pins; MIWU inputs RC0-RC7 I/O TTL/CMOS/ST Port C bidirectional I/O pins

RD0-RD7 I/O TTL/CMOS/ST Port D bidirectional I/O pins

RE0-RE7 I/O TTL/CMOS/ST Port E bidirectional I/O pins

RTCC I ST Input to Real Time Clock/Counter

MCLR I ST Master Clear reset input – active low

OSC1/In/Vpp I ST Crystal oscillator input - external clock source input

OSC2/Out O CMOS Crystal oscillator output – in R/C mode, internally

pulled to Vdd through weak pullup

Vdd P NA Positive supply pins

Vss P NA Ground pins

SX User’s Manual Rev. 3.1

www .scenix.com

(

)

gging

Chapter 2

Architecture

2.1 Introduc t io n

The SX device is a complete RISC communica tions controller with an elect rically erasable (flash) program memory and in-system programming capability. The device can operate with a clock rate of up to 75 MHz and can execute instructions at a rate of up to 75 million instructions per second.

The SX device has multi-pin I/O ports, an internal os cillator, a Watchdog timer, a Real-Time Clock/ Counter, an analog comparator, power-on and brownout reset control, and Multi-Input Wakeup capability. Figure 2-1 is a block diagram showing the core features of the basic device. Additional features are available with some SX family members. For example, some devices offer more RAM, a larger EEPROM program memory, or additional peripheral modules such as multi-function timers.

OSC1

Instruction

Pipeline

OSC2

OSC

Driver 4MHz

Internal

RC OSC

System Clock

Power-On

Reset

Brown-Out

Fetch

Decode

Executive

Write Back

Clock

Select

4 or ÷ 1

MCLR

RESET

3 Level

Stack

MIWU

8-bit W atchdo

Timer

System

Clock

FSR

PC STATUS OPTION

MODE

WDT

Pre sc ale r for R T C C

Prescaler for WD T

Inte rn a l D a ta B u s

Address

Write Data

RTCC

8-bit Timer

RTCC

Inte rr up t

Read Data

ALU

136 Bytes

SRAM

Instruction

Inter ru pt Sta c k

Analo

MIWU Port B Comp

In-System

Debu

In-System

rammin

Pro

2k Words EEPROM

IREAD

Port A

888

Port C

SX User’s Manual Rev. 3.1

Figure 2-1 SX28AC Block Diagram

www. s ce nix.comChap te r 2 A r chitec tu r e

The SX device uses a modified Harvard architecture, in which the program and data are stored in separate memory spaces. The advantage of this architecture is that instruction fetches and data transfers can be overlapped with a multi-stage pipeline, which means the next instruction can be fetched from program memory while the current instruction is being executed uses data from the data memory. This device has a “modified” Harvard architecture because instructions are available for transferring data from the program memory to the data memory.

2.2 Program Memory

The program memory holds the application program for the device. It is an electrically erasable, flashprogrammed memory containing 2,048 words for the SX18/20/28AC and SX18/20/28AC75 devices or 4,096 words for the SX48/52BD, with 12 bits per word. Each memory location holds a single 12bit instruction opcode or 12 bits of fixed data that can be accessed by the program. The memory can be programmed and reprogrammed through the device oscillator pins, even with the device ins talled in the target system.

The program memory is addressed by the program counter, a register of 1 1 bits for the SX18/20/ 28AC and SX18/20/28AC75 or 12 bits for the SX48/52BD. Operation of the program counter is described in detail in Section 2.6.

2.3 Data Memory

The data memory is a RAM-based register set consisting of general-purpose registers and dedicatedpurpose registers. The number of registers depends on the SX device type. The SX18/20/28AC and SX18/20/28AC75 devices have 136 general-purpose registers and eight dedicated-purpose registers. The SX48/52BD has 262 general-purpose registers and ten dedicated-purpose registers. All of these registers are eight bits wide. The registers are organized into banks, allowing the SX ins tructions to address the registers using just five bits of the 12-bit instruction opcode.

Because the registers are organized into banks or “f iles,” these memory-mapped registers are called “file registers.” In the descriptions of the SX instructions in Chapter 3, the abbreviation “fr” represents a 5-bit register selection value encoded into the instruction opcode.

2.3.1 Banks

The SX device can be programmed to use any one of the data memory banks at any given time. The high-order bits in the File Select Register (FSR) specify the current bank number. T o change from one bank to another, the program can either write an eight-bit value to the FSR register or us e the “bank” instruction. The “bank” instruction writes the three high-order bits in the FSR register without affecting the other bits in the register.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

The organization of the data memory banks is somewhat different for the various SX family 8 members:

• SX18/SX20/SX28AC and SX18/20/28AC75: eight banks of 16 bytes per bank, with 8 global registers mapped to bank 0

• SX48BD/SX52BD: 16 banks of sixteen bytes per bank, with 16 global r egisters mapped into a separate bank

The following sections describe the bank organization in detail.

2.3.2 SX18/20/28AC and SX18/20/28AC75 Addressing Modes and FSR Register

The data memory of the SX18AC, SX20AC, SX28AC, SX18AC75, SX20AC75, or SX28AC75 is a RAM-based register set consisting of 136 general-purpose registers and eight dedicated-purpose registers. All of these registers are eight bits wide. The registers are organized into eight banks, designated Bank 0 through Bank 7.

Each SX instruction that accesses a data memory register contains a 5-bit field in the instruction opcode that specifies the register to be accessed. The abbreviation “fr” represents the 5-bit register address designator. For example, the instruction description “mov fr,W” means that a 5-bit value or label must be substituted for “fr ” in the instruction, such as “mov $0F,W” (to move the contents of the working register W into file register 0Fh).

The SX device can be programmed to use any one of the eight banks at any given time. The three highorder bits in the File Select Register (FSR) specify the current bank number. T o change from one bank to another, the program can either write an eight-bit value to the FSR register or use the “bank” instruction. The “bank” instruction writes the three bank-selection bits in the FSR register without affecting the other bits in the register. Bank 0 is selected by default upon power-up or reset.

Within each bank, there are 32 available addresses, ranging from 00h to 1Fh. Table 2-1 shows the organization of file registers in the memory-mapped address space. The numbers along the left side the table (ranging from $00 to $1F) show the 32 possible register addresses that can be specified in the instruction. The bank numbers listed across the top (ranging from 0 to 7) are the number s that can be programmed into the three high-order bits of the FSR register. The entries inside the table show the registers accessed by each combination of register addres s and bank selecti on.

The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the table, the register addresses are shown as 8-bit hexadecimal values.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Table 2-1 SX18/20/28AC and SX18/20/28AC75 RAM Regi ster Map

Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

$00 INDF INDF INDF INDF INDF INDF INDF INDF $01 RTCC RTCC RTCC RTCC RTCC RTCC RTCC RTCC $02 PC PC PC PC PC PC PC PC $03 Status Status Status Status Status Status Status Status $04 FSR FSR FSR FSR FSR FSR FSR FSR $05 RA RA RA RA RA RA RA RA $06 RB RB RB RB RB RB RB RB $07 RC RC RC RC RC RC RC RC $08 08h 08h 08h 08h 08h 08h 08h 08h $09 09h 09h 09h 09h 09h 09h 09h 09h $0A 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah $0B 0Bh 0Bh 0Bh 0Bh 0Bh 0Bh 0Bh 0Bh $0C 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch $0D 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh $0E 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh $0F 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh $10 10h 30h 50h 70h 90h B0h D0h F0h $11 11h 31h 51h 71h 91h B1h D1h F1h $12 12h 32h 52h 72h 92h B2h D2h F2h $13 13h 33h 53h 73h 93h B3h D3h F3h $14 14h 34h 54h 74h 94h B4h D4h F4h $15 15h 35h 55h 75h 95h B5h D5h F5h $16 16h 36h 56h 76h 96h B6h D6h F6h $17 17h 37h 57h 77h 97h B7h D7h F7h $18 18h 38h 58h 78h 98h B8h D8h F8h $19 19h 39h 59h 79h 99h B9h D9h F9h $1A 1Ah 3Ah 5Ah 7Ah 9Ah BAh DAh FAh $1B 1Bh 3Bh 5Bh 7Bh 9Bh BBh DBh FBh $1C 1Ch 3Ch 5Ch 7Ch 9Ch BCh DCh FCh $1D 1Dh 3Dh 5Dh 7Dh 9Dh BDh DDh FDh $1E 1Eh 3Eh 5Eh 7Eh 9Eh BEh DEh FEh $1F 1Fh 3Fh 5Fh 7Fh 9Fh BFh DFh FFh

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

For the first 16 addresses that can be specified in an instruction (00h through 0Fh), the same 16 registers are accessed, irrespective of the bank setting. Therefore, these 16 “global” registers are always accessible. The first ei ght are dedicated- purpose register s (INDF, RTC C, PC, and so on), and the next eight are general-purpose registers. In Table 2-1, th ese registers are shown s haded in Bank 1 through Bank 7 to indicate that they are the same registers as in Bank 0.

For the upper 16 addresses that can be specified in an instruction (10h through 1Fh), a different set of registers is accessed in each bank. This allows as many as 128 different registers to be accessed in this memory range, although only 16 are accessible at any given time.

The total number of general-purpose registers is 24 in Bank 0 (from 08h to 1Fh) and 16 in each of the remaining seven banks (from 10h to 1Fh in each bank), for a total of 136 registers. In the SX18AC/ SX18AC75 and SX20AC/SX20AC75 devices, an additional general-purpose register is available at address 08h because there is no Port C register occupying that address.

There are two addressing modes for the SX18/20/28AC and SX18/20/28AC75 devices, called the indirect and direct modes. The addressing mode used for register access depends on the 5-bit “fr” value used in the instruction:

• indirect mode: fr = 00h

• direct mode: fr = 01h through 1Fh

For indirect addressing (fr= 00), the File Select Register (FS R) specifies the register to be accessed. FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data memory for indirect addressing.

For direct addressing with bit 4 of “fr” equal to 0 (fr=01-0F), Bank 0 is accessed and the value of “fr” itself specifies the register to be accessed. In this case, a “global” register in Bank 0 is accessed (01h through 0Fh) and the FSR register is ignored.

For direct addressing with bit 4 of “fr” equal to 1 (fr=10-1F), the three high-order bits of the FSR register specify the bank number accessed, and the five bits of “fr” specify which register in that bank is accessed. In this case, the upper half of a bank is accessed.

2.3.3 SX48/52BD Addressing Modes and FSR Register

Each SX instruction that accesses a data memory register contains a 5-bit field in the instruction opcode that specifies the register to be accessed. The abbreviation “fr” (file register ) represent s the 5bit register address designator . For example, the instruction description “mov fr,W” means that a 5-bit value or label must be substituted for “fr” in the instruction, such as “mov $0F,W” (to move the contents of the working register W into file register 0Fh).

There are three different addressing modes, called the indirect, direct, and semi-direct modes. The addressing mode used for register access depends on the 5-bit “fr” value used in the instruction:

• indirect mode: fr = 00h

• direct mode (fr bit 4 = 0): fr = 01h through 0Fh

• semi-direct mode (fr bit 4 = 1): fr = 10h through 1Fh

Figure 2-2 illustrates the data memory addressing scheme.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

memory for indirect addressing. In this mode, the global register bank and Bank 1 through Bank F are accessible. Bank 0 is not accessible.

For direct addressing (fr=01-0F), the value of “fr” itsel f specifies the register to be acces sed, and the FSR register is ignored. For this addressing mode, only the global register bank is accessible. To gain access to any other bank, you must use either indirect or semi-direct addressing.

For semi-direct addressing (fr=10-1F), the bank number is selected by the four high-order bits of FSR, and the register within that bank is selected by the four low- order bits of “fr.” In other words, the register address is obtained by combining the four high-order bits of FSR with the four low-order bits of “fr”. In this addressing mode, the low-order bits of FSR are ignored. Bank 0 through Bank F are accessible, but the global register bank is not accessible.

Figure 2-2 shows how register addressing works in the indirect, dir ect, and semi- direct modes. T he 16

global registers are always accessible by direct addressing, regardless of what is contained in the FSR register. The global registers are also accessible with indirect addressing, but they are not accessible with semi-direct addressing. Of the 16 global registers, nine are special-purpose registers (RTCC, PC, STATUS, and so on), and six are general- purpose registers. Location 00 is used f or indirect addressing (INDF). All of the registers in Bank 0 though Bank F are general-purpose registers.

To change the contents of the FSR register, the program can either write an eight-bit value to the FSR register or use the “bank” instruction. The “bank” instruction writes the three high-order bits (4, 5, and 6) in the FSR register. Bit 7 of FSR is used to select the upper or lower “bank” of memory banks. Thus, to change from one upper bank to another, only a single “bank” instruction is required. To change from one upper bank to a lower bank, the “bank” instruction must be followed by “setb FSR.7”.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

5-Bit “fr” Value

of Instruction

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

FSR

Indirect Addressin

Direct Addressin

00 INDF 01 RTCC 02 PC 03 STATUS 04 FSR 05 RA 06 RB 07 RC 08 RD 09 RE 0A 0B 0C 0D 0E 0F

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

Global

Registers

User

Configured

FSR

Semi-Direct Addressin

FSR bits 7:0 select one of the registers in the global register set or a register in Bank 1 through Bank F. Bank 0 is not accessible.

“fr” bits 3:0 select one of 15 registers in the global register set. The FSR register is ignored. Bank 0 through Bank F are not accessible.

10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF

F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

Bank 0 Bank 1 Bank 2 B ank E Bank F

Modified by BANK instruction

FSR bits 7:4 select one of

XXXX

16 banks, and “fr” bits 3:0 select one of 16 registers in that bank. The four low-order bits of FSR are ignored. All 256 registers in Bank 0 through Bank F

are accessible. The global registers are not accessible.

Figure 2-2 Register Access Modes

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

2.3.4 Register Access Examples

Here is an example of an instruction that uses direct addressing:

inc $0F ;increment file register 0Fh

This instruction increments the contents of file register 0Fh in the global register bank. It does not matter what is contained in the FSR register.

To gain access to any r egister outside of the global register bank, it is ne cessary to use semi-direct or indirect addressing. In that case, you need to make sur e that the FSR register contains the correct value for accessing the desired bank.

Here are 2 examples that use semi-direct addressing:

mov W,#$F0 ;load W with F0h mov FSR,W ;load W into FSR (Bank F) inc $1F ;increment file register FFh

Or, to access bank 0,

mov W,#$00 ;load W with 00h mov FSR,W ;load W into FSR (Bank 0) inc $1F ;increment file register 0Fh

In these examples, “FSR” is a label that represents the value 04h, which is the address of the FSR register in the global register bank. Note that the FSR register is itself a memory-mapped global register, which is always accessible using direct addressing.

The “banked” data memory is divided into upper and lower blocks, each consisting of 8 banks of data memory. The range for the lower block is from $00 to $7F, while the range for the upper block is from $80 to $FF. Bit 7 of the FSR is used to select the upper or lower block. The BANK instruction is used to select the bank within that block.

To use the “bank” instruction, in the syntax of the assembly language, you specify an 8-bit value that corresponds to the desired bank number. The assembler encodes bits 4, 5, and 6 of the specified value into the instruction opcode and ignores bit 7 and the low-order bits. For example, if another lower bank was being used to increment file register 2Fh, you could use the following instructions:

bank $20 ;select Bank 2 in FSR inc $1F ;increment register 2F

Note that the “bank” instruction only modifies bits 4, 5, and 6 the FSR register. Therefore, to change from a lower block to an upper block bank, the “bank” instruction will not work. Instead, you need to write the whole FSR register using code such as the following:

mov W,#$80 ;load W with 80h mov FSR,W ;select Bank 8 in FSR

Another approach is to set bit 7 of t he FSR register individually after the “bank” instruction to address an upper block bank.

bank $80 ;set bits in 4, 5, and 6 FSR setb FSR.7 ;select Bank 8 in FSR

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

To change from an upper block to a lower block bank, bit 7 of FSR must be cleared. With i ndirect addressing, you specify the full 8-bit address of the regis ter using FS R as a pointer. This

addressing mode provides the flexibility to acces s different registers or multiple regi sters using the same instruction in the program.

You invoke indirect addressing by using fr=00h. For example:

mov W,#$F5 ;load W with F5h mov $04,W ;move value F5h into FSR mov W,#$01 ;load W with 01h mov $00,W ;move value 01h into register F5h

In the second “mov” instruction, FSR is loaded with the desired 8-bit register address. In the fourth “mov” instruction, fr = 00, so the device looks at FSR and moves the result to the register addressed by FSR, which is the register at F5h (Bank F, register number 5).

A practical example that uses indirect addressing is the following program, which clears the upper eight registers in the global register bank and the upper 8 registers in all banks from Bank 1 through Bank F:

clr FSR clear FSR to 00h (at address 04h)

:loop setb FSR.3 ;set FSR bit 3

clr $00 ;clear register pointed to by FSR incsz FSR ;increment FSR and test

;skip jmp if 00h

jmp:loop ;jump back and clear next reg.

This program initially clears FSR to 00h. At the beginning of the loop, it sets bit 3 of FSR so that it starts at 08h. The “clr $00” instruction clears the register pointed to by FSR (initially, the file register at 08h in the global register bank). Then the program increments FSR and clears consecutive file registers, always in the upper half of each bank: ( 08h, 09h, 0Ah... 0Fh, 18h, 19h... FFh). The loop ends when FSR wraps back to 00h.

For addresses from 01h through 0Fh, the global register bank is accessed. For higher addresses, Bank 1 through Bank F are accessed. This program does not affect Bank 0, which is not accessi ble in the indirect addressing mode. Bank 0 can be accessed only using the semi-direct mode.

2.4 Special-Function Registers

The SX instructions can access a set of dedicated file registers at the bottom of the data memory and the general-purpose file registers at higher addresses . Many instructions can also acces s certain nonmemory-mapped registers: the Working register (W), the port control registers, the MODE register, and the OPTION register. All of these registers are eight bits wide.

Table 2-2 lists and briefly describes the dedicated file registers and non-memory-mapped registers that

are accessible to SX instructi ons.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Table 2-2 Register Summary

W Working Register . This is the main working register used by many instructions

as the source or destination of the operation.

INDF (00h) Indirect through FSR. There is no actual register at this memory location. When

this address (00h) is specified as the source or destination of an operation, the register location pointed to by FSR is accessed.

RTCC (01h) Real-Time Clock/Counter . This register can be used to keep track of elapsed

time or occurrences of transitions on the RTCC input pin.

PC (02h) Program Counter. Only the lower eight bits of the program counter are available

at this register location.

STATUS (03h) Status. This register contains the status bits for the device such as the C bit, Z

bit, and program memory page selection bits.

FSR (04h) File Select Register. This register specifies the bank number for direct address-

ing or the full 8-bit address for indirect addressing.

RA (05h) Port A Data Register. This register is used to control output signals and read

input signals on the RA0-RA7 I/O pins.

RB (06h) Port B Data Register. This register is used to control output signals and read

input signals on the RB0-RB7 I/O pins.

RC (07h) Port C Data Register. This register is used to control output signals and read

input signals on the RC0-RC7 I/O pins. I n devices without Port C , the register at 07h is a general-purpose register.

RD (08h) Port D Data Register. This register is used to control output signals and read

input signals on the RD0-RD7 I/O pins. In devices without Port D, the register at 08h is a general-purpose register.

RE (09h) Port E Data Register. This register is used to control output signals and read

input signals on the RE0-RE7 I/O pins. In devices without Port E, the register at 09h is a general-purpose register.

Port Co ntrol Registers

The port control registers are used to control the configuration of the port I/O pins. These registers are accessed by a special-purpose instruction,

“mov !rx,W”.

MODE MODE Register. This register controls access to the port control registers when

you use the “mov !rx,W” instruction.

OP T ION Option Register. This register sets some device configuration options such as

the Real-Time Clock/Counter incrementing mode.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

2.4.1 W (Working Register)

The W register is the main working register used by many instructions as the source or destination of the operation. It is often used as a temporary storage area for intermediate operations. For example, to add the contents of two file registers, you must first move the contents of one file register to W and then execute an “add” instruction to perform an addition between W and the other file register.

For SX18/20/28AC and SX18/20/28AC75 devices, in the default device configuration, W is not memory-mapped and can only be accessed by instructions that work specifically with W as the source or destination. However, you can optionally make the W available as a memory-mapped register at address 01h. To do this, first program the OPTIONX bit to 0 in the FUSEX word in the program memory . Then have your program clear the R TW bit in the OP TION register . If you do this, the RT CC register normally at address 01h becomes unavailable.

2.4.2 INDF (Indirect through FSR)

The INDF register location (address 00h) is used for indirect addressing. Wheneve r this address is specified as the source or destination of an operation, the device uses the register pointed to by the FSR register (address 04h). There is no actual register or data stored at address 00h.

For more information on indirect addressing, see Section 2.3.

2.4.3 RTCC (Real-Time Clock/Counter)

The RTCC register (address 01h) is an 8-bit Real-Time Clock/Counter used to keep track of elapsed time or to keep a count of transitions on the RTCC input pin. The timer operating configuration is determined by control bits in the OPTION register.

To keep track of time, you configure the timer register to be incremented once per instruction cycle or once per multiple of the instruction cycle. To count external events, you configure the timer register to be incremented once per rising edge or falling edge on the RTCC input pin.

The program can read or write the register at any time. A rollover from FFh to 00h generates an interrupt to the CPU if that condition is enabled as an interrupt.

For more information on the operation of the timer, see Section 6.2. In the Sx18/20/28AC and Sx18/20/28AC75 devices, if you do not need to use the RTCC register, you

can optionally make the working register (W) available as a memory-mapped register at address 01h. For details, see the description of the W register.

2.4.4 PC (Program Counter)

The PC register (a ddress 02h) contains t he lower eight bi ts of the 11-bit or 12-bit program counter . The program counter is a pointer register that points to the current instruction being executed in the 2,048word or 4,096-word program memory. During regular program execution, the program counter is incremented automatically once per instruction cycle. This regular sequence is altered in order to perform skips, jumps, and subroutine calls in the application program.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

For detailed information on program counter operation, see Section 2.6.

2.4.5 STATUS (Status Register)

The STATUS register (address 03h) contains the device status bits, which are automatically set or cleared by the device when certain events occur. The program can read this register at any time to determine the status of the device. The format of the register is shown below, and Table 2-3 briefly describes each of the register bit fields.

PA2 PA1 PA0 TO PD Z DC C

Bit 7 Bit 0

Table 2-3

STATUS Register Bits

Status Bits Description

PA2:PA0 Program memory page selection bits. You set or clear these bits to specify the

program memory page number for a jump or call instruction.

TO Watchdog timeout bit. This bit is set to 1 upon power-up and cleared to 0 when a

W a tchdog timeout occurs.

PD Power Down bit. This bit is set to 1 upon power-up and cleared to 0 when the

“SLEEP” instruction is executed. Z Zero bit. This bit is set when the result of an operation is zero. DC Di git Carry bit. This bit is set when there is a carry out from bit 3 to bit 4 in an

addition operation and cleared when there is a borrow out from bit 3 to bit 4 in a

subtraction operation. C Carry bit. This bit is set when there is a carry out of bit 7 in an addition operation

and cleared when there is a borrow out of bit 7 during a subtraction operation. It is

also affected by the rotate-through-carry instructions.

The STATUS register is a read/write register except for the TO and PD bits, which are read-only bits. Those two bits cannot be changed by writing to the STAT US register address.

When you write to the STATUS register, it is recommended that you use the “setb” (set bit) and “clrb” (clear bit) instructions to control the individual bits rather than “mov” ( move) instructions to move whole register values. This is because the CPU of ten modifies the STATUS register bits, possibly resulting in register values that are different from what you expect.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

The individual bits of the STATUS register are described below.

PA2:PA0 (Program Memory Page Selection Bits)

PA2:PA0 are the program memory page selection bits. They are used to set the high-order bits of the program counter for jump and call instructions. You can set them without affecting the other bits in the STATUS register by using the “page” instruction. For details, see Section 2.6.

T0 (Watchdog Timeout Bit)

T0 is the W atchdog Timeout bit. It is set to 1 upon power-up and cleared to 0 when a watchdog timeout occurs. It is set back to 1 upon execution of the “clrwdt” (clear Watchdog timer) instruction or “SLEEP” instruction. For details, see Section 6.3.

PD (Power Down Bit)

PD is the Power Down bit. It is set to 1 upon power-up and cleared to 0 upon execution of the “SLEEP” instruction. It is set back to 1 upon execution of the “clrwdt” (clear Watchdog timer) instruction. For details, see Section 4.3.

Z (Zero Bit)

Z is the Zero bit. This bit is affected by the execution of many types of instructions (add, subtract, increment, decrement, move, logic operations, and so on). When one of these instructions is executed, the Z bit is set to 1 if the result is zero or cleared to 0 if the result is nonzero.

DC (Digit Carry Bit)

DC is the digit carry bit. This bit is affected by the execution of instructions that add or subtract. For an instruction that performs addition, the C bit is set to 1 if a carry occurs out of bit 3 to bit 4, or is cleared to 0 otherwise. For instructions that perform subtraction, the C bit is cleared to 0 if a borrow occurs out of bit 3 to bit 4, or is set to 1 othe rwise. This bit can be used to implement carry -bit functions with single hexadecimal digits.

C (Carry Bit)

C is the carry bit. This bit is affected by the execution of the addition, subtraction, and rotate-throughcarry instructions. For an instruction that performs addition, the C bit is set to 1 if overflow occurs (a carry out of bit 7), or is cleared to 0 other wise. For an instruction that pe rforms s ubtraction, the C bit is cleared to 0 if underflow occurs (a borrow out of bit 7), or is set to 1 otherwise.

The device can be configured either to use or not use the C bit as an implicit input to addition and subtraction operations. This option is controlled by the CF bit in the FUSEX Word (a word that is programmed at the same time as the program memory). An implicit addition of the C bit can be used to implement multiple-byte addition and subtraction algorithms.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

In the default configuration, the carry bit is not used as an input to addition and subtraction operations. In that case, the carry bit can still be added or subtracted explicitly by using a separate “test carry bit and skip” instruction in conjunction with an “increment” or “decrement” instruction.

For rotate (RR or RL) instructions, the carry bit is loaded with the bit 0 or bit 7 respectively.

2.4.6 FSR (File Select Register)

The FSR register (address 04h) is the File Select Register used to specify the bank number for semidirect addressing of file registers, or the full 8-bit address for indirect addressing of file registers. The file registers are addressed as foll ows:

• For semi-direct addressing, the high-order bits of FSR specify the bank number, and the ins truction opcode specifies the register within the selected bank. The low-order bits of FSR are ignored in this addressing mode.

• For indirect addressing, the FSR register specifies the full 8-bit address of the register being accessed. To invoke this mode, the instruction specifies address 00h (INDF) as the source or destination of the operation.

For more information on using the FSR register for addressing the data registers, see Section 2.3.

2.4.7 RA through RE (Port Data Registers)

The RA, RB, RC, RD, and RE registers (addresses 05h, 06h, 07h, 08h, and 09h) are the I/O port data registers for Port A through Port E. When a port is configured to operate as an output, writing to its port data register sets the output values of the port pins. In the default operating mode, reading from one of these register locations reads the port pins directly (not necessarily returning the values contained in the port data register).

For the SX48/52BD, a control bit called PORTRD in the T2CNT2 register determines how the device reads data from its I/O ports. Set this bit to 1 to have the device read data directly from the port I/O pins (the default operating mode). Clear this bit to 0 to have the device read data from the port data registers.

For detailed information on configuring and using the I/O ports, see Chapter 5.

2.4.8 Port Control Registers and MODE Register

The MODE register controls access to the port control register s for subsequent uses of the “MOV !rx,W” instruction. For example, ther e are three registers for controlli ng Port A: the RA Direction register, the PLP_A (pullup enable A) register, and the LVL_A (level selection A) register. One of these three registers is accessed by the “MOV !RA,W” instruction, depending on the value contained in the MODE register. For the SX48/52BD, use MODE values of 0Fh, 0Eh, or 0Dh, respectively to read the RA Direction, PLP_A, and LVL_A registers; or 1Fh, 1Eh, or 1Dh, respectively to write these same registers. On the SX18/20/28AC and SX18/20/28AC75 devices, the port control registers are write-only registers, and bit 4 of the MODE register is a “don’t care” bit.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

Upon reset, the MODE register is initialized to 0Fh for the SX18/20/28AC and SX18/20/28AC75 or to 1Fh for the SX48/52BD. This makes the port direction registers write-accessible to the “MOV !rx,W” instructions. In order to access the other port control registers, you first need to write the appropriate value into the MODE register , as indicated in Table 2-4 for the SX18/20/28AC and SX18/ 20/28AC75 or in Table 2-5 for the SX48/52BD. MODE register values not listed in the tables are reserved for future expansion.

Table 2-4 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75

MODE

Reg.

mov !RA,W

mov !RB,W

mov !RC,W

X8h Exchange CMP_B

X9h Exchange WKPND_B XAh WKED_B XBh WKEN_ B XCh ST_B ST_C XDh LVL_A LVL _B LVL_C

XEh PLP_A PLP_B PLP_C

XFh RA Direction RB Direction RC Direction

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Table 2-5 MODE Register Settings for SX48/52BD

MODE Reg. m ov !RA,W mov !RB,W mov !RC,W mov !RD,W mov !RE,W

00h Read T1CPL Read T2CPL 01h Read T1CPH Read T2CPH 02h Read T1R2CML Read T2R2CML 03h Read T1R2CMH Read T2R2CMH 04h Read T1R1CML Read T2R1CML 05h Read T1R1CMH Read T2R1CMH 06h Read T1CNTB Read T2CNTB 07h Read T1CNTA Read T2CNTA 08h Exchang e CMP_B

09h Exchange WKPND_B 0Ah Write WKED_B 0Bh Write WKEN_B 0Ch Read ST_B Read ST_C Read ST_D Read ST_E 0Dh Rea d LVL_A Read LV L_B Read LVL_ C Read LVL_D Read LVL_ E 0Eh Read PLP_A Read PLP_B Read PLP_C Read PLP_D Read PLP_E

0Fh Read RA

Direction 10h Clear Timer T1 Clear Timer T2 11h 12h Write T1R2CML Write T2R2CML 13h Write T1R2CMH Write T2R 2CMH 14h Write T1R1CML Write T2R1CML 15h Write T1R1CMH Write T2R 1CMH 16h Write T1 C NTB Wr i te T2 CN T B 17h Write T1 C NTA Write T2CNTA 18h Exchang e CMP_B 19h Exchange WKPND_B

1Ah Wr ite WKE D_B 1Bh Write WKEN_B 1Ch Write ST_B Write ST_C Write ST_D Write ST_E 1Dh Write LVL_A Write LVL_B Write LVL_C W rite LVL_D Write LVL_E 1Eh Write PLP_A Write PLP_B Write PLP_C Write PLP_D Write PLP_E

1Fh Write RA

Direction

Read RB Direction

Write RB Direction

Read RC Direction

Write RC Direction

Read RD Direction

Write RD Direction

Read RE Direction

Write RE Direction

After you write a value to the MODE register, that setting remains in effect until you change it by writing to the MODE register again. For example, you can write the value 1Eh to the MODE register just once, and then write to each of the three pullup configuration registers using the three “mov !rx,W” instructions shown at the top of Table 2-4.

For detailed information on configuring and using the I/O ports, see Chapter 5.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

2.4.9 OPTION (Device Option Register)

The OPTION register sets several device configuration options, mostly related to operation of the Real-Time Clock/Counter. The format of the register is shown below. Upon reset, all bits in this register are set to 1.

RTW RTE_IE RTS RTE_ES PSA PS2 PS1 PS0

Bit 7 Bit 0

NOTE:

For SX18/20/28AC and SX18/20/28AC75 devices, the upper 2 bits (RTW and RTE-IE) of the OP T ION register are available only when the OPTIONS bit in the FUSEX register is cleared. For SX48/52BD devices, these bits are always available.

RTW Bit: RTCC or W at address 01h

For SX18/20/28AC and SX18/20/28AC75 devices, clear the RTW bit to 0 to make W available as a memory-mapped register at address 01h. Set the RTW bit to 1 for the default register configuration, with RTCC at address 01h. Before you can clear the RTW bit, the option must be enabled by programming the OPTIONX bit to 0 in the FUSEX word in the program memory.

For SX48/52BD devices, the RTW function is always available.

RTE_IE Bit: RTCC Rollover Interrupt Enable

Clear the R T E_IE bit to 0 to enable the interrupt that occurs upon rollover of the RTCC counter, or set this bit to 1 to disable the interrupt. Before you c an clea r the RTE_IE bit, the option must be enabled by programming the OPTIONX bit (SX18/20/28AC and SX18/20/28AC75 devices only) to 0 in the FUSEX word register. For SX48/52BD devices, the RTE-IW function is always available.

RTS Bit: RTCC Trigger Selection

Clear the R TS bit to 0 to have the R TCC counter incremented automatically with each instruction cycle (or a specified number of instruction cycles) . This mode can be used to implement a real- time clock. Set the RT S bit to 1 to have the RTCC counter incremented once each time a transition is detected on the RTCC input pin (or a specified number of transitions). This mode can be used as an external event counter.

RTE_ES: RTCC Input Edge Select

When the RTCC counter is configured to count transitions received on the RTCC pin (when RT S=1), the RTCC bit specifies the type of signal edges detected on the RTCC pin. Set RTE_ES to 1 to detect high-to-low transitions on the RTCC pin. Clear RTE_ES to 0 to detect low-to-high transitions on the RTCC pin.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

PSA Bit: Pre sc a l er Assignme n t

Clear the PSA bit to 0 to have the internal prescaler operate with the Real-Time Clock/Counter . In that case, the R T CC counter is incremented once every n ins truction cycles, with the number n determined by the PS2:PS0 bits; and the Watchdog timer operates at the default rate.

Set the PSA bit to 1 to ha ve the internal prescaler oper ate with the Watchdog timer. In that case, a Watchdog reset is generated after n timeouts of the Watchdog timer register, with the number n determined by the PS2:PS0 bits; and the RTCC register is incremented once per instruction cycle or external event.

PS2:PS0 Field: Prescaler Divide-By Factor

Use this bit field in conjunction with the PSA bit to specify an operating rate for the RTCC timer or Watchdog timer that is lower than the default rate. Ta b le 2 -6 shows the clock divide-by factors determined by these bits. Note that for a given setting, the divide-by factor depends on whether you use the prescaler register with the RTCC timer (PSA=0) or with the Watchdog timer (PSA=1). For the R TCC timer, the timer is incremented once every 2, 4, 8, ... or 256 instruction cycles or external events. For the Watchdog timer, a Watchdog reset is triggered after 1, 2, 4, ... or 128 overflows of the Watchdog timer register.

Table 2-6 Prescaler Divide-By Factors

PS2:PS0

RTCC Timer Input

Divide-By Factor (PSA=0)

W a tchdog T imer Output

Divide-By Factor (PSA=1)

000 2 1 (timeout = 0.016 sec) 001 4 2 (timeout = 0.032 sec) 010 8 4 (timeout = 0.064 sec)

011 16 8 (timeout = 0.128 sec) 100 32 16 (timeout = 0.256 sec) 101 64 32 (timeout = 0.5 sec)

110 128 64 (timeout = 1.0 sec)

111 256 128 (timeout = 2.0 sec)

For detailed information on the Real-Time Clock/Counter and Watchdog timer, see Chapter 6.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

2.5 Instruction Execution Pipeline

The CPU executes in program in a 4-stage pipeline consisting of the following stages:

• Fetch the instruction from program memory.

• Decode the instruction opcode.

• Execute the operation.

• Write the res ult to destinat ion registe r.

Each execution stage requires one instruction cycle. Although it takes four cycles to complete the execution of each instruction, an overall throughput of one instruction per clock cycle is achieved by overlapping successive operations in the pipeline. For example, Ta b le 2 -7 shows the sequence of operations carried out as the CPU executes the first six instructions of a program.

Table 2-7 Pipeline Execution Sequence

Program

Instruction

Clock

Cycle 1

Clock

Cycle 2

Clock

Cycle 3

Clock

Cycle 4

Clock

Cycle 5

Clock

Cycle 6 etc.

1st instruction Fetch Decode Execute Write 2nd instruction Fetch Decode Execute Write 3rd instruction Fetch Decode Execute Write 4th instruction Fet ch Deco de Execute ... 5th instruction Fetch Decode ... 6th instruction Fetch ...

As long as the normal flow of the program is not interrupted, the device performs four pipeline operations in parallel, thus achieving an overall throughput of one instruction per clock cycle, or 50 MIPS with a 50 MHz clock in the “turbo” clocking mode.

2.5.1 Clocking Modes

The SX device can be configured to operate in either the “turbo” or “compatible” mode. In the “turbo” mode, instructions are executed at the rate of one per clock cycle, and one clock cycle is the same as one instruction cycle. In the “compatible” mode (SX18/20/28AC and SX18/20/28AC75 devices only), instructions are executed at the rate of one per four clock cycles, and four devic e clock cycles are required for each instruction cycle. For more information on these clocking modes, see Section 4.2.1.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

2.5.2 Pipeline Delays

Any instruction or interrupt condition that alters the normal program flow will take at least one additional instruction cycle. For example, when a test -and-skip instruction is exec uted and the tested condition is true, the next instruction in the program is skipped. The next instruction occupies space and takes up time in the pipeline whether or not it is skipped. As a result, a skipped instruction causes a delay of one instruction cycle when a skip occurs. The test-and-skip instruction is described as taking one cycle if the tested condition is false or two cycles if the tested condition is true.

The call, jump, and return-from-interrupt instructions reload the program counter and cause the program to jump to an entirely new location in program memory. As a result, the instructions in the pipeline are discarded, causing a multi-cycle delay in program execution. Each call, jump, and returnfrom-interrupt instruction takes two, three, or four cycles for execution, depending on the specific instruction and the device clocking mode. For details, see the instruction descriptions in Chapter 3.

For the same reason, the triggering of an interrupt causes a pipeline delay. For an RTCC interrupt, the delay is three cycles. For a Multi-Input Wakeup interrupt, the delay is five cycles (two cycles for interrupt synchronization and a three-cycles pipeline delay).

2.5.3 Read-Modify-Write Considerations

A “read-modify-write” instruction is an instruction that operates by reading a register, modifying the value, and writing the result back to the r egister. Any instruction that writes a new value to a register that depends on the existing value is a read-modify-write instruction. Some examples are “clrb fr.bit” (clear bit), “setb fr.bit” (set bit), “add fr,w” (add W to file register), and “dec fr” (decrement file register). The “set bit” instruction, for example, does not simply set one bit a nd ignore the others. Instead, it reads the whole register, sets the specified bit to “1”, and writes the whole result back to the register.

When you use successive read-modify-write instructions on a port data register, you might get unexpected results at very high clock rates (such as 50/75 MHz ). When you write to an I/O port, you write to the port data register; but when you read a port, you read the actual voltage on the I/O port pin (in the default operating mode). There is a slight delay from the time that the data port is written and the time that the output voltage changes to the programmed level.

When you use two successive read-modify-write instructions on the same I/O port, the “write” part of one instruction might not occur soon enough before the “read” part of the very next instruction, resulting in getting “old” data for the second instruction. (Remember that successive instructions are executed in parallel, one behind the next in the pipeline.)

To ensure predictable results, avoid using two successive read-m odify-write instructions that access the same port data register. For example, you can insert a “nop” instruction between two such instructions in the program.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

2.6 Program Counter

The program counter is an 11-bit or 12-bit register that points to the current instruction being executed in the 2,048-word or 4,096-word program memory (depending on the SX device type). The eight loworder bits of the program counter are directly accessible as a file register called the PC register, at address 02h. The higher-order bits are not directly accessible, except through the STATUS register.

During regular program execution, the whole 11-bit or 12-bit program counter is incremented automatically once per instruction cycle. This regular sequence is altered in order to perform skips, jumps, subroutine calls, and interrupt processing.

Upon power-up or reset, the program counter is loaded with the highest program address (7FFh or FFFh). This memory location typically contains an instruction to jump to an initialization routine.

All interrupts cause the program counter to be loaded with 000h, the bottom program address. Therefore, if interrupts are used, the bottom memory segment must contain the interrupt service routine.

2.6.1 Test and Skip

There are several instructions that test a condition a nd cause the next instruction to be skipped if the condition is true. For example, the “S B fr.bit” instruction tests a bit in a file register and sk ips the ne xt instruction if that bit is set to 1.

When a skip occurs, the program counter is incremented by two rather than one upon conclusion of the test-and-skip instruction, and the skipped instruction (which is already being processed in the pipeline) is canceled. There is a delay of one clock cycle caused by the skip operation.

2.6.2 Jump Absolute

The “JMP addr9” instruction causes the program to jump to a new location by loading a new value into the program counter. The lower nine bits of the new value come from a 9-bit field in the instruction opcode. The upper bits of the new value come from the PA2:PA0 bits of the STATUS register. Therefore, the PA2:PA0 bits of the STATUS register must be pre-loaded with the desired 512-word page number before the jump instruction is executed.

For example, if the jump destination is address 7E0h in the program memory , the PA2:PA0 bits in the STATUS register must be set to 011 before you execute the “JMP addr9” instruction. You can use the following sequence of instructions to perform the jump:

setb $03.5 ;set bit 5 in STATUS register (PA0) setb $03.6 ;set bit 6 in STATUS register (PA1) clrb $03.7 ;clear bit 7 in STATUS register (PA2) jmp $1E0 ;jump to program memory address 7E0h

In this example, the desired jump address is 7E0h. The lower nine bits of this address are specified by the “JMP addr9” instruction as 1E0h, and the upper three bits are obtained from the PA2:PA0 bits (bits 7:5) in the STATUS register, which are set to 011 prior to the “jmp” instructi on.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Another way to achieve the same effect faster and with fewer instructions is to use the “page” instruction to set the PA2:P A0 bits in the STATUS register:

page $600 ;set page to 600h (PA2:PA0 = 011 binary) jmp $1E0 ;jump to program memory address 7E0h

The “page” instruction sets the values of the PA2:P A0 bits without affecting other bits in the STATUS register. It does this in just one clock cycle. You specify a 12-bit value in the instruction and the assembler encodes the three high-order bits of the value into the instruction (and ignores the lowerorder bits). When you execute the instruction, it sets the PA2:PA0 bits in the STATUS register accordingly.

Note that is necessary to set the PA2:PA0 bits prior to the “jmp” instruction only if they do not already contain the desired page number. You can set them just once and then use any number of “jmp” instructions as long as you stay within the same 512-word page in the program memory.

A “JMP addr9” instruction takes two clock cycles in the “compatible” clocking mode (SX18/20/28AC and SX18/20/28AC75 devices only) or three clock cycles in the “turbo” clocking mode. (For information on clocking modes, see Section 4.2).

2.6.3 Jump Indirect and Jump Relative

Instead of using the “JMP addr9” to s pecify an absolute jump destination, you can cause a jump by modifying the PC register (file register address 02h), which holds the lower eight bits of the program counter.

For example, to perform an indirect jump, you can move a new value from W to PC, as in t he following example:

mov W,$0B ;load W with 8-bit jump address from file reg. mov $02,W ;load PC with new address (lower 8 bits only)

To perform an indirect relative jump (a jump of a certain number of memory locations forward or backward from the next instruction), you can add W to PC or subtract W from PC, as in the following example:

mov W,#$04 ;load W with the immediate value 04h add $02,W ;increase PC by 4 (jump forward 5 instructions)

You can use an indirect jump to implement a multiple-branch conditional jump (for example, to jump to one of four different routines based on a calculation result).

If you perform a jump by modifying the PC register, you can only jump to a location within the same 256-word segment in the program memory. This is because you can only modify the lower eight bits of the program counter. To jump across a 256-word boundary, use the “PAGE addr12” and “JMP addr9” instructions.

A jump performed by modifying the PC register with a “mov” or “add” instruction takes four clock cycles in the “compatible” clocking mode (SX18/28/28AC and SX18/20/28AC75 devices only) or three clock cycles in the “turbo” clocking mode.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

2.6.4 Call

The “CALL addr8” instruction calls a subroutine. It works just like a “JMP addr9” instruction, with the following differences:

• The “call” instruction saves the full program counter value, incremented by one, on the program stack. This allows the program to later return from the s ubroutine and continue exec ution with the instruction immediately following the call.

• The “call” instruction only specifies the lower eight bits (rather than the lower nine bits) of the jump address. The ninth bit (bit 8) of the jump address is always 0. Therefore, the subroutine must start in the bottom half of a 512-word page in the program memory (000h to 0FFh, 200h to 2FFh, etc.).

Figures 2-3 and 2-4 show how the program counter is loaded for a “jmp” instruction and for “call”

instruction, respectively. In either case, the PA2:PA0 bits must contain the desired 512-word page of the program memory before the “jmp” or “call” instruction is executed. These bits can be easily changed with the “page” instruction.

PA2 PA1 PA0 TO PD Z DC C

BITS 1 1:8 OF

PROGRAM COUNTER

Figure 2-3 Program Counter Loading for Jump Instruction

PA2 PA1 PA0 TO PD Z DC C

ZERO

BITS 1 1:8 OF

PROGRAM COUNTER

ST ATUS REGISTER

PC (7:0)

ST ATUS REGISTER

PC (7:0)

9-BIT VALUE IN JMP INSTRUCTION

PROGRAM COUNTER

8-BIT VALUE IN CALL INSTRUCTION

PROGRAM COUNTER

Figure 2-4 Program Counter Loading for Call Instruction

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

When a “call” instruction is executed, the CPU does the following:

• Increments the stack pointer and stores the full program counter contents on the program stack.

• Loads the lower eight bits of the program counter (the PC register) with the 8-bit value specified in the instruction opcode.

• Clears the ninth bit (bit 8) of the program counter to 0.

• Copies the PA2:PA0 bits into the high-order bit positions of the stack pointer (bits 11:9).

Like the “jmp” instruction, the “call” instruction takes two clock cycles in the “compatible” mode (SX18/20/28AC and SX18/20/28AC75 devices only) or three clock cycles in the “turbo” clocking mode.

2.6.5 Return

A subroutine called by the “call” instructi ons is terminated by a “return” instruct ion. The “return” instruction restores the full value to the program counter from the stack. This causes the program to jump back to the instruction immediately following the “call” instruction that called the subroutine.

It is not necessary to s et the PA2:P A0 bi ts in the STATUS register in order to retur n to the co rrect pla ce in the program. This is bec ause the full pr ogram addres s is saved on the stack in a “ca ll” instruction and fully restored by a “return” instruction. Therefore, the program always returns to the instruction immediately following the “call” instruction, even for a subroutine call across page boundaries. The PA2:PA0 bits are ignored by “return” instructions.

There are severa l different “return” type instructions available in the instruction set. Some are for returning from subroutines and other are for returning from interrupts. All of them are listed and described in Table 2-8. For more information on interrupts, see Chapter 6.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

Table 2-8 Return-from-Subroutine/Interrupt Instructions

Option Bits Description

RET Return from Subroutine. This is an ordinary return from subroutine. It does not

affect any registers or bits.

RETP Return from Subroutine Across Page Boundary. This instruction works like the

RET instruction, but also writes bits 11:9 of the return address (the address of the instruction immediately following the CALL instruction) to the PA2:PA0 bits of the STATUS register. This automatically configures the PA2:PA0 bits to select the current page, allowing a subsequent same-page jump or call to be executed without another “page” instruction.

RETW #lit Return from Subroutine with Literal in W. This instruction works like the RET

instruction, except that it loads a literal value into W before returning from the subroutine. A sequence of these instructions can be used in conjunction with a PC-adjustment instruction to implement a data-lookup table.

RETI Return from Interrupt. This instruction restores the program counter and the W,

STAT US, and FSR registers that were saved upon occurrence of the interrupt. (Note that the program stack is not used for interrupt processing.)

RETIW Return from Interrupt and Adjust RTCC with W. This instruction works like the

RETI instruction, but also adds W to the RTCC register. This can be used to adjust the RTCC counter back to the value in contained upon occurrence of the interrupt.

2.7 Stack

When a “call” instruction is executed, the full address of the instruction immediately following the “call” instructions is pushed onto the program stack. Upon return fr om the subroutine, the full address is popped from the stack and restored to the program counter, causing execution to resume with the instruction immediately following the “call” instruction.

The stack is a last-in, first-out (LIFO) data buffer, 12 bits wide (11 bits wide for the SX18/20/28AC and SX18/20/28AC75) and eight levels deep. The eight levels of the stack allow subroutines be nested, one within another, up to eight levels deep.

For the SX18/20/28AC and SX18/20/28AC75 devices, in the default device configuration, the stack is limited to two levels. In general, however, the stack should be configured to eight levels because there is no reason to limit the stack size. This option is controlled by the STACKX bit in the FUSEX word register (a register programmed at the same time as the program memory).

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

The stack is not memory-mapped and there are no “push” or “pop” instr uctions in the instruction set. Therefore, the program stack is not directly accessible to the program and is not used for any purpose other than to save and restore progr am memory addresses, which is done implicitly by “call” and “return” instructions.

There is no “stack pointer” for this stack. Instead, the device simply moves all the data words down or up the stack for each “call” or “return” instruction executed, as indicated in Figures 2-5 and 2-6.

PROGRAM COUNTER (11:0)

STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 STACK 8

STACK 8 CONTENTS ARE DISCARDED

Figure 2-5 Stack Operation for a “Call” Instruction

PROGRAM COUNTER (11:0)

STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7 STACK 8

STACK 8 CONTENTS ARE LEFT UNCHANGED

Figure 2-6 Stack Operation for a “Return” Instruction

For a “call” instruction, the device copies the contents of the whole program counter to the top stack location, and existing words in the stack are moved down by one stack location. Any data word in the bottom stack location is lost.

For any type of return-from-subroutine instruction (RET, RETP, or RETW lit), the device copies the contents of the top-level stack location into the program counter, and existing words in the stack are moved up by one stack location. The bottom stack location is left unchanged.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

If you attempt to nest subroutines beyond eight leve ls, or if you execute a return-from-subroutine instruction without a prior corresponding “call” instruction, unpredictable results will occur because an incorrect address will be copied to the program counter.

The stack is not used for interrupt processing and is therefore not involved in the return-from-interrupt instructions (RETI and RETIW). For information on interrupt processing, see Chapter 6.

2.8 Device Configuration Options

The SX device has three 12-bit configuration registers that can be read or written at the same time that the instruction memory is programmed:

• FUSE word register, accessible by a device programming command

• FUSEX word register, accessible by a device programming command

• DEVICE word register, a read-only word accessible by a device programming command

These registers are not accessible to the appli cation program at run time. T hey can only be read or written when the device is set up for programming the instruction memory.

The register formats are shown in Figure 2-7 and the configuration fields within the registers are explained in Table 2-9, Table 2-10, Table 2-11 and Table 2-12. Note that the format of the FUSEX register depends on the SX device type (SX18/20/28AC and SX18/20/28AC75 or SX48/52BD).

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

FUSE Word for SX18/20/28AC and SX18/20/28AC75

TURBO SYNC Reserved Reserved IRC DIV1/IFBD DIV0/FOSC2 Reserved CP WDTE FOSC1 FOSC0

Bit 11 Bit 0

FUSE Word for SX48/52BD

Unused SYNC Unused Unused IRC DIV1/IFBD DIV0/FOSC2 XTLBUF_EN CP WDTE FOSC1 FOSC0

Bit 11 Bit 0

FUSEX Word for SX18/20/28AC and SX18/20/28AC75

IRCTRIM2 PINS IRCTRIM1 IRCTRIM0

Bit 11 Bit 0

OPTIONX

STACKX

CF BOR1 BOR0 BORTRIM1 BORTRIM0 BP1 BP0

FUSEX Word for SX48/52BD

IRCTRIM2 SLEEPCLK

Bit 11 Bit 0

IRCTRIM1 IRCTRIM0 Unused CF BOR1 BOR0 BORTR1 BORTR0 DRT1 DRT0

DEVICE Wor d (H ar d-W i re d Re a d-O n ly )- Part ID

Part ID Code: FCEh for the SX18/20/28AC or 001h for the SX48/52BD

Bit 11 Bit 0

Figure 2-7 Device Configuration Register Formats

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

Table 2-9 FUSE Word Register Configuration Bits for SX18/20/28AC (Sheet 1 of 2)

Option Bits Description

TURBO Turbo Mode. Set to 1 for “compatible” mode, in which the instruction rate oper-

ates at one-fourth the oscillator clock rate. Set to 0 for the turbo mode, in which the instruction rate is equal to the oscillator clock rate.

SYNC Synchronous Input Mode (for turbo mode operation). Set to 1 to disable or clear

to 0 to enable.This bit allows an input signal to be synchronized with internal clock through two internal flip-flops.

IRC Internal RC Oscillator. Set to 1 to disable the internal oscillator and have the

OSC1 and OSC2 pins operate as defined by the FOSC2:FOSC0 bits. Clear to 0 to enable the internal oscillator, and to have the OSC1 pin pulled low by weak pullup and the OSC2 pin pulled high by weak pullup.

DIV2:DIV0 Internal RC Oscillator Divider. This field sets the divide-by factor for generating

the instruction clock from the internal oscillator when the internal oscillator is enabled (IRC = 0). The nominal instruction rate is determined by DIV1:DIV0 as follows: 00 = 4 MHz 01 = 1 MHz 10 = 128 KHz 11 = 32 KHz

IFBD Internal Feedback Disable. If IRC = 1, and IFBD = 1, the crystal/resonator oscil-

lator can rely on the internal feedback resistor between the OSC1 and OSC2 pins. If IFBD = 0, an external feedback resistor is required between the OSC1 and OSC2 pins.

CP Code Protection. Set to 1 for no code protection. Clear to 0 for code protection.

With code protection, the program code and configuration registers read back as scrambled data. This prevents reverse-engineering of your proprietary code and configuration options.

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Table 2-9 FUSE Word Register Configuration Bits for SX18/20/28AC (Sheet 2 of 2)

Option Bits Description

WDTE Watchdog timer enable. Set to 1 to enable the Watchdog timer. Clear to 0 to dis-

able the W atchdog timer.

FOSC1: FOSC0

External Oscillator Configuration. This combination of three register bits sets up the device to operate with a particular type of external oscillator when the device is configured to operate with an external oscillator (IRC = 1). Note that bit 5, the DIV0/FOSC2 bit, operates as DIV0 with IRC=0, or as FOSC2 with IRC=1. The type of external oscillator is determined by FOSC2:FOSC0 as follows: 000 = LP1 – low-power crystal (32 KHz) 001 = LP2 – low-power crystal/resonator (32 KHz to 1 MHz) 010 = XT1 – low-power crystal/resonator (32 KHz to 10 MHz) 011 = XT2 – normal crystal/resonator (1 MHz to 24 MHz) 100 = HS1 – normal crystal/resonator (1 MHZ to 50 MHz) 101 = HS2 – normal crystal/resonator (1 MHZ to 50 MHz) 110 = HS3 – normal crystal/resonator (1 MHZ to 50 MHz) 111 = External RC (OSC2 is pulled high with a weak pullup (no CLKOUT output) Note: The frequency ranges have not been characterized. These are target values.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

Table 2-10 FUSEX Word R egister Confi guration Bits for SX18/20/28A C & SX18/20/28AC75

Option Bits Description

PINS Selects the number of pins. IRCTRIM2 :

IRCTRIM

Internal RC Oscillator Trim. This 3-bit field adjusts the operation of the internal RC oscillator to make it operate within the target frequency range of 4.0 MHz (typical) plus or minus 8%. Parts are shipped from the factory untrimmed. The device relies on the programming tool to provide the trimming function. 000b = minimum frequency 111b = maximum frequency

OPT IONX/ STACKX

OPTION Register Extension and Stack Extension. Set to 1 to disable the programmability of bit 6 and bit 7 in the OPTION register, the RTW and RTE_IE bits (in other words, to force these two bits to 1); and to limit the program stack size to two locations. Clear to 0 to enable programming of the R TW and RTE_IE bits in the OPTION register, and to extend the stack size to eight locations.

CF Carry bit Input. Set to 1 to ignore the carry bit as an input to addition and subtrac-

tion operations. Clear to 0 to add the carry bit into all addition operations (ADD fr,W means fr = fr + W + C); and to subtract the complement of the carry bit from all subtraction operations (SUB fr, W means fr = fr – W – /C).

BOR1: BOR0

Brown-Out Reset. The BOR1:BOR0 bits enable or disable the brown-out reset function and set the brown-out threshold voltage as follows: 00 = 4.2V 01 = 2.6V 10 = 2.2V 11 = Disable Brown-Out Reset

BORTRIM1: BORTRIM0

BP1: BP0

Brown-Out trim bits (parts are shipped out of the factory untrimmed).

Configured Memory Size. These two factory-configured bits should not be changed unless you want to reduce the configured amount of program memory in the device. To do so, use one the following BP1:BP0 settings: 00 = 1 page, 1 bank 01 = 1 page, 2 banks 10 = 4 pages, 4 banks 11 = 4 pages, 8 banks (default)

SX User’s Manual Rev. 3.1

www. s ce nix.comChap te r 2 A r chitec tu r e

Table 2-11 FUSE Word Configuration Bits for SX48/52BD

Option Bits Description

SYNC Synchronous Input Mode Enable. Set to 1 to disable or clear to 0 to enable.This

bit allows an input signal to be synchronized with internal clock through two internal flip-flops. If enabled, port data must be read more than 2 cycles after a change to the input level mode or Schmitt trigger mode. 0 = enabled 1 = disabled

IRC Internal RC oscillator enable:

0 = enabled - OSC1 is pulled low by a weak pullup, OSC2 is pulled high by a weak pullup 1 = disabled - OSC1 and OSC2 behave according to FOSC2: FOSC0

DIV1: DIV0 Internal RC oscillator divider (if IRC = 0):

00b = 4 MHz 10b = 1 MHz 01b = 125 KHz 11b = 31.25 KHz

IFBD Internal crystal/resonator oscillator feedback resistor (10 M):

0 = Internal feedback resistor disable (external feedback required for crystal/resonator operation) 1 = Internal feedback resistor enabled (valid only when IRC = 1)

XTLBUF_EN Crystal Buffer enable (disable when not using a resonator/crystal to reduce Idd):

0 = Crystal/resonator Buffer disabled 1 = Crystal/resonator Buffer enabled

CP Code protect enable:

0 = enabled (FUSE, code, and ID memories read back as scrambled data) 1 = disabled (FUSE, code, and ID memories can be read normally)

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 2 Architecture

Option Bits Description

WDTE Watchdog timer enable:

0 = disabled 1 = enabled

FOSC2: FOSC0

External oscillator configuration (valid when IRC = 1): 000b = LP1 – low power crystal (32KHz) 001b = LP2 – low power crystal (32KHz - 1MHz) 010b = XT1 – normal crystal (32KHz - 8MHz) 011b = XT2 – normal crystal (1MHz - 24MHz) 100b = HS1 – high speed crystal (1MHz - 32MHz) 101b = HS2 – high speed crystal (1MHz - 50MHz) 110b = HS3 – high speed crystal (1MHz - 100MHz) 111b = RC network - OSC2 is pulled high by a weak pullup (no CLKOUT output) Note: The frequency ranges indicate target values.

SX User’s Manual Rev. 3.1

Table 2-12 FUSEX Word Register Configuration Bits for SX48/52BD

Option Bits Description

www. s ce nix.comChap te r 2 A r chitec tu r e

IRCTRIM2 IRCTRIM0

Internal RC Oscillator Trim. This 3-bit field adjusts the operation of the internal

RC oscillator to make it operate within the target frequency range of typically 4.0 MHz plus or minus 8% (typical). Parts are shipped from the factory untrimmed. The device relies on the programming tool to provide trimming. 100 = maximum frequency 111 = typical 011 = minimum frequency

SLEEPCLK Sleep Clock Disable.

0 = enable crystal/resonator based clock operation during power down mode (to allow fast start-up). 1 = disable crystal/resonator based clock operation during power down mode (to reduce power consumption).

CF Carry Flag ADD/SUB enable

0 = carry bit input to ADD and SUB instructions 1 = ADD and SUB without carry

BOR1: BOR0 Sets the Brown Out Reset threshold voltage

00b = 01b = 10b =

4.1V

2.4V

2.2V

11b = BOR disabled

BORTR1: BORTR0

WDR T1: WDR T0

Brown-Out trim bits (parts are shipped out of factory untrimmed). 00b = minimum threshold voltage 11b = maximum threshold voltage

Delay Reset Timer (DRT) timeout period 10b = 0.25 msec 11b = 18 msec 00b = 60 msec 01b = 1 sec

SX User’s Manual Rev. 3.1

www .scenix.com

Chapter 3

Instruction Set

3.1 Introduction

The Scenix SX configurable communications controllers use a RISC (Reduced Instruction Set Computer) architecture. In this type of architecture, the instruction set is limited in complexity and diversity, but the instructions can be executed very fast, typically at a rate of one instruction per clock cycle. High performance is achieved by executing many simple instructions very fast.

The instruction set consists entirely of single-word (12-bit) instructions, most of which can be executed at a rate of one instruction per clock cycle, for a total throughput of up to 50 MIPS (million instructions per second) when the device operates with a 50 MHz clock. The only common instructions that take more than one clock cycle to exe cute are those that control program flow, such as call and return instructions, and test-and-skip instructions that result in a skip.

3.2 Instruction Oper ands

An SX program consists of a sequence of instructions stored in the device program memory. Each instruction, when executed, changes the data contained in one or more device registers. All data registers are eight bits wide.

Most of the device registers are memory-mapped. Each memory-mapped register occupies an address in the data memory address space, and can be accessed by the “mov” ins tructions of the SX ins truction set. An instruction refers to a memory-mapped register by specifying a 5-bit “fr” (file register) value in the instruction. Multiple se ts or “banks” of registers are available, as specif ied by the File Select Register (FSR). For more information on register addressing modes, see Section 2.3.

The W (Wor king) register is used in many of the instructions but is not memory-mapped. It is often used as the source or destinat ion of an oper ation. T he lett er “W” repr esents this register in the syntax of the assembly language.

There are several dedicated-purpose registers and many general-purpose registers in the data memory address space, organized as described in Chapter 2. The exact number of registers and their organization depend on the specific SX device type.

The source data for an operation can be provided by the instruction opcode itself rather than a register . An operand provided this way is called an “immediate” operand. In the syntax of the assembly language, the “number” or “pound” character (#) indicates an immediate value. Here is one example:

mov W,#$0F ;move immediate value 0Fh into W

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

The immediate value 0Fh is loaded into the W register. The 8-bit immediate value occupies an eightbit field in the instruction opcode.

3.3 Instruction Types

The instructions are divided into the following categories:

• Logic Instructions

• Arithmetic and Shift Instructions

• Bitwise Operation Instructions

• Data Movement Instructions

• Program Control Instructions

• System Control Instructions

The following subsections describe the characteristics of the instructions in these categories.

3.3.1 Logic Instructions

Each logic instruction performs a standard logical operation (AND, OR, exclusive OR, or logical complement) on the respective bits of the 8-bit operands. The result of the logic operation is written to W or to a file register.

All of these instructions take one clock cycle for execution.

3.3.2 Arithmetic and Shift Instructions

Each arithmetic or shift instruction performs an operation such as add, subtract, rotate left or right through carry, increment, decrement, clear to zero, or swap high/low nibbles.

The device can be configured either to use or not use the carry bit as an implicit input to addition and subtraction operations. This option is controlled by the CF bit in the FUSEX Word (a word that is programmed at the same time as the program memory). In the default configuration, the carry bit is not used as an input to these operations. In that case, the carry bit can still be added or s ubtracted explicitly by using a separate “test carry bit” instruction in conjunction with an “increment” or “decrement” instruction.

There are instructions are available that increment or decrement a register and simultaneously test the result. If the 8-bit result is zero, the next instruction in the program is skipped. These instructions can be used to make program loops.

All of the arithmetic and shift instruc tions take one c lock c ycle f or e xec ution, ex ce pt in the case of the test-and-skip instructions when the tested condition is true and a skip occurs.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.3.3 Bitwise Operation Instructions

There are four bitwise operation instructions:

• “setb” sets a single bit to 1 in a data register without affecting other bits

• “clrb” clears a single bit to 0 in a data register without affecting other bits

• “sb” tests a single bit in a data register and skips the next instruction if the bit is set to 1

• “snb” tests a single bit in a data register and skips the next instruction if the bit is cleared to 0

Any bit in any memory-mapped register can be set, cleared, or tested individually, including bits in the program counter, FSR register, and STATUS register. These instructions are often used to set, clear, and test bits in the STATUS register.

All of the bitwise operation instr uctions take one clock cycle for execution, except in the case of the test-and-skip instructions when the tested condition is true and a skip occur s. If a skip instruction is immediately followed by a PAGE or BANK instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles. This is useful for conditional branching to another page where a PAGE instruction precedes a JMP. If several PAGE and BANK instructions immediately follow a skip instruction then they are all skipped plus the next instruction and a cycle is consumed for each.

3.3.4 Data Movement Instructio ns

Each data movement instruction moves a byte of data from one register to another, or performs an operation on the contents of a source register and s imultaneously moves the result into W (without affecting the source register). The f ollowing operations can be performed simultaneously with data movement into W : a dd, subtract, c omplement, incr ement, decrement, rotate left , rotat e right, and swap high/low nibbles.

Instructions are also available that simultaneously increment or decrement the contents of a register, move the result into W, and test the result. If the 8-bit resul t is zero, the next instr uction in the program is skipped.

Additional data movement instructions are provided to access the port control registers, the MODE register, and the OPTION regis t er, which are not accessible as ordinary file registers.

All of the data movement instructions take one clock cycle for execution, except in the case of the tes tand-skip instructions when the tested condition is true and a skip occurs.

3.3.5 Program Control Instructions

Each program control instruction alters the flow of the program by changing the contents of the program counter. Included in this category are the jump, call, and return-from-subroutine instructions.

The “jmp” instruction has a single operand that specifies the new address at which to resume execution. The new address is typically specified as a label, as in the following example:

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

snb STATUS.0 ;check carry bit and skip next if C=0 jmp do_carry ;jump to do_carry routine if C=1 ... do_carry ;jump destination label ... ;program execution continues here

If the carry bit is set to 1, the “jmp” instruction is executed and progr am execution continues where the “do_carry” label appears in the program.

The “call” instruction works in a similar manner, except that it saves the contents of the program counter before jumping to the new address. Therefore, it calls a subroutine that can be terminated by any of several “return” instructions, as shown in the following example:

... call add_2bytes ;call subroutine add_carry ... ;subroutine results used here add_2bytes ;subroutine label ... ;subroutine code here ret ;return from subroutine

Returning from a subroutine restores the saved program counter contents, which causes program to resume execution with the instruction immediately following the “call” instruction.

A program memory address contains 12 bits (or 11 bits for the SX18/20/28AC and SX18/20/28AC75). The “jmp” instruction specifies only the lowest nine bits of the jump address and the “call” instruction specifies only the lowest eight bits of the call address. For information on how the device handles the higher-order program address bits, see Section 2.6.

An indirect (register-specified) jump can be accomp lished by moving the desired jump address from W to the PC register (mov $02,W). An indirect relative jump can be accomplished by adding W to the PC register (add $02,W).

Program control instructions such as “jmp,” “call,” and “ret” alter the normal program sequence. Therefore, when one of these instr uctions is exec ut ed, the execution pipeline is automatically cleared of pending instructions and refilled with new instructions, starting at the new program address. Because the pipeline must be cleared, multiple clock cycles are required for execution. The typical execution time for one of these instructions is two or three clock cycles, depending on the specific instruction and the device configuration mode (“compatible” or “turbo” clocking mode). The “compatible” mode is available only in the SX18/20/28AC and SX18/20/28AC75 devices. For the exact number of clock cycles required, see t he instruction set summary tables or the detailed instruction descriptions.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.3.6 System Control Instructions

A system control instruction performs a special-purpose operation that sets the operating mode of the device or reads data from the program memory. Included in this category are the following instructions:

• “bank” loads a bank number into the FSR register

• “iread” reads a word from the program memory

• “page” writes the page number bits in the STATUS register

• “sleep” places the device in the power down mode

All of these instructions take one clock cycle for execution, except in the case of the “iread” instruction in the “turbo” device clocking mode, which takes four clock cycles.

3.4 Instruction Summary Tables

Tables 3-1 through 3-6 list all of the SX instructions, organized by category. For each instruction, the

table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycl es required for e xecution, the binary opc ode, and the status Bits affected by the instruction.

The “Cycles” column typically shows a value of 1, which means that the overall throughput for the instruction is one per clock cycle. In some cases, the exact number of cycles depends on the outcome of the instruction (such as the test-and-skip instructions).

The instruction execution time is derived by dividing the oscillator frequency be either one (Turbo mode) or four (Compatible mode). The divide-by-four option is available only in the SX18/20/28AC and SX18/20/28AC75 devices. This option is selected through the FUSE Word register

The detailed instruction descriptions in Section 3.5 fully explain the oper ation of each instruction, including the Bits affected, the number of cycles required for execution, and usage examples.

SX User’s Manual Rev. 3.1

Table 3-1 Logic Instructions

Syntax Description

www. s ce nix.comChapter 3 Instruction Set

Cycles

Opcode Bits

Comp. Turbo

AND fr, W AND of fr and W into fr 1 1 AND W, fr AND of W and fr into W 1 1 AND W,#lit AND of W and Literal into W 1 1 NOT fr Complement of fr into fr 1 1 OR fr,W OR of fr and W into fr 1 1 OR W,fr OR of W and fr into fr 1 1 OR W,#lit OR of W and Literal into W 1 1 XOR fr,W XOR of fr and W into fr 1 1 XOR W,fr XOR of W and fr into W 1 1 XOR W,#lit XOR of W and Literal into W 1 1

Table 3-2 Arithmetic and Shift Instructions (Sheet 1 of 2)

Cycles

Syntax Description

Comp. Turbo

0001 011f ffff 0001 010f ffff 1110 kkkk kkkk 0010 011f ffff 0001 001f ffff 0001 000f ffff 1101 kkkk kkkk 0001 101f ffff 0001 100f ffff 1111 kkkk kkkk

Opcode Bits

Z Z Z Z Z Z Z Z Z Z

ADD fr,W Add W to fr 1 1 ADD W,fr Add fr to W 1 1 CLR fr Clear fr 1 1 CLR W Clear W 1 1 CLR !WDT Clear Watchdog Timer 1 1 DEC fr Decrement fr 1 1 DECSZ fr Decrement fr and Skip if

Zero

1 or

2 (skip)

1 or

2 (skip) INC fr Increment fr 1 1 INCS Z fr Incre ment fr a n d Skip if

Zero

1 or

2 (skip)

1 or

2 (skip) RL fr Rotate fr Left through Carry 1 1

0001 111f ffff 0001 110f ffff 0000 011f ffff 0000 0100 0000 0000 0000 0100 0000 111f ffff 0010 111f ffff

0010 101f ffff 0011 111f ffff

0011 011f ffff

C, DC, Z C, DC, Z

Z Z

TO, PD

none

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

Table 3-2 Arithmetic and Shift Instructions (Sheet 2 of 2)

Cycles

Syntax Description

Opcode Bits

Comp. Turbo

RR fr Rotate fr Right through

Carry SUB fr,W Subtract W from fr 1 1 SWAP fr Swap High/Low Nibbles of

Table 3-3 Bitwise Operation Instructions

Cycles

Syntax Description

Comp. Turbo

CLRB fr.bit Clear Bit in fr 1 1 SB fr .bit Test Bit in fr and Skip if Set 1 or

2 (skip)

1 or

2 (skip) SETB fr.bit Set Bit in fr 1 1 SNB fr .bit Tes t Bit in fr and Skip if Clear 1 or

2 (skip)

1 or

2 (skip)

0011 001f ffff

0000 101f ffff 0011 101f ffff

Opcode Bits

0100 bbbf ffff 0111 bbbf ffff

0101 bbbf ffff 0110 bbbf ffff

C, DC, Z

none

none none

Table 3-4 Data Movement Instructions (Sheet 1 of 2)

Cycles

Syntax Description

Comp. Turbo

MOV fr,W Move W to fr 1 1 MOV W,fr Move fr to W 1 1 MOV W,fr-W Move (fr-W) to W 1 1 MOV W,#lit Move Literal to W 1 1 MOV W,/fr Move Compleme nt

of fr to W MOV W,--fr Move (fr-1) to W 1 1 MOV W,++fr Move (fr+1) to W 1 1

Opcode Bits

0000 001f ffff 0010 000f ffff 0000 100f ffff 1100 kkkk kkkk 0010 010f ffff

0000 110f ffff 0010 100f ffff

none

C, DC, Z

none

Z Z

SX User’s Manual Rev. 3.1

Table 3-4 Data Movement Instructions (Sheet 2 of 2)

Syntax Description

www. s ce nix.comChapter 3 Instruction Set

Cycles

Opcode Bits

Comp. Turbo

MOV W,<<fr Rotate fr Left

through Carry and

Move to W MOV W,>>fr Rotate fr Right

through Carry and

Move to W MOV W,<>fr Swap High/Low

Nibbles of fr and

move to W MOV W,M Move MODE Reg-

ister to W MOVSZ W,--fr Move (fr-1) to W

and Skip if Zero MOVSZ W,++fr Move (fr+1) to W

and Skip if Zero MOV M,W Move W to MODE

1 or

2 (skip)12 (skip)

1 or

2 (skip)12 (skip)

0011 010f ffff

0011 000f ffff

0011 100f ffff

0000 0100 0010

0010 110f ffff

0011 110f ffff

0000 0100 0011

none

MOV M,#lit M ove Literal to

MODE Register MOV !rx,W Move W to Port Rx

Control Register MOV !OPTION, W Move W to

OPTION Register TEST fr Test fr fo r Zero 1 1

0000 0101 kkkk

0000 0000 ffff

0000 0000 0010

0010 001f ffff

none

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

Table 3-5 Program Control Instructions

Cycles

Syntax Description

Opcode Bits

Comp. Turbo

CALL addr8 Call Subroutine 2 3 JMP addr9 Jump to Address 2 3 NOP No Operation 1 1 RET Return from Subroutine 2 3 RETP Return from Subroutine

Across Page Boundary RETI Return from Interrupt 2 3 RETIW Return from Interrupt and

Add RTCC to W RETW lit Return from Subroutine

with Literal in W

Table 3-6 System Control Instructions

Cycles

Syntax Description

Comp.

Turb

1001 kkkk kkkk 101k kkkk kkkk 0000 0000 0000 0000 0000 1100 0000 0000 1101

none none none none PA1,

PA0

0000 0000 1110 0000 0000 1111

1000 kkkk kkkk

all Status all Status

none

Opcode Bits

BANK addr8 Load Bank Number into

FSR(7:5)

IREAD Read W ord from Ins tru c -

tion Memory

PAGE addr12 Load Page Number into

STA TUS(7:5)

SLEEP Power Down Mode 1 1

0000 0001 1nnn

0000 0100 0001

0000 0001 0nnn

0000 0000 0011

none

PA2, PA1,

PA0

TO, PD

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.5 Equivalent Assembler Mnemonics

Some assemblers support additional instruction mnemonics that are special cases of existing instructions or alternative mnemonics for standard ones. For example, an assembler might support the mnemonic “CLC” (clear carry), which is interpreted the same as the instruction “clrb $03.0” (clear bit 0 in the STAT US register). Some of the commonly supported equivalent assembler mnemonics are described in Table 3-7.

Table 3-7 Equivalent Assembler Mnemonics

Syntax Description Equivalent Cycles

CLC Clear Carry Bit CLRB $03.0 1 CLZ Clear Zero Bit CLRB $03.2 1 JMP W Jump Indirect W MOV $02,W 4 or 3 (note 1) JMP PC+W Jump Indirect W Relative ADD $02,W 4 or 3 (note 1) MODE imm4 Move Immediate to MODE Register MOV M,#lit 1 NOT W Complement W XOR W,#$FF 1 SC Skip if Carry Bits Set SB $03.0 1 or 2 (note 2) SKIP Skip Next Instruction SNB $02.0 or SB $02.0 4 or 2 (note 3)

NOTES: 1.

The JMP W or JMP PC+W instruction takes 4 cycles in the “compatible” clocking mode or 3 cycles in the “turbo” clocking mo de. “Compatible” mode is available only in the SX18/20/28AC and SX18/20/28AC75 devices.

The SC instruction takes 1 cycle if the tested condi tion is fa lse or 2 cycl es if t he tested condition is true.

The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit of the program counter, choosing SNB or SB s o that the tested condition is always true . The instruction take s 4 cycles in the “c ompatible” clocking mode or 2 cycles in the “turbo” clocking mode. “Compatible” mode is available only in the SX18/20/28AC and SX18/20/28AC75 devices.

3.6 Detailed Instruction Descriptions

Each instruction in the SX instruction se t is described in de tail in the following page s. The instructi ons are described in alphabetical order by mnemonic name.

Each description starts on a new page of the manual. The heading at the top of the page shows the syntax of the command and a brief description of what the command does.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

In the syntax description, the parts that are to be used literally are shown in upper case and the variable parts are shown in lower case. For example, the “add W to file register” command is shown as follows:

ADD fr,W

The “ADD” and “W” should be used exactly as shown in the command syntax, whereas the lower-case notation “fr” means that you should use a f ile register address, which can be a ny value from $00 to $1F, or an equivalent symbol. In an actual program, you can use either upper-case or lower-case characters. Here is an example of an actual “add W to register” command:

add $0F,W ;add contents of W to file register 0Fh

The text after the semicolon is a comment, which is ignored by the assembler. Each instruction description includes the following information:

• Operation. This section describes the effects of the command in equation form. For example, the “add W to file register” command shows the operation as “fr = fr + W” (fr is set equal to the sum of fr plus W).

• Bits affected. This is a list of the status bits that are affected by execution of the command, such as the carry (C) and zero (Z) bits.

• Opcode. This is the 12-bit opcode of the encoded instruction, shown in binary format. Bits that depend on variables are shown as letters rather than 0 or 1. For example, the opcode for the “ADD fr,W” instruction is shown as 0001 110f ffff. The sequence of five “f” characters represents the five-bit file register address specified in the instr uc tion. The le tter “ k” or “n” is similarly used to represent the constant or number specified in the instruction.

• Description. This is a verbal description of what the instruction does.

• Cycles. This is the number of clock cycles required to execute the instruction. In cases where this number depends on certain conditions, those conditions and the resulting num bers are explained. In some cases, the number depends on the clocking mode ( “turbo” or “compatible” mode). In the “compatible” mode, the number shown is the number of r egular instruction cycles re quired for execution, each cycle consisting of four device clocks. The “compatible” mode is only offered in the SX18/20/28AC and SX18/20/28AC75 devices.

• Example. At least one example of the instruction is provided, together with an explanation of how the example operates.

In some cases, there is an additional section called “Config. Option,” whic h explains how the be havior of the instruction is affected by the device configuration.

Some assemblers support additional instruction mnemonics that are special cases of existing instructions. Also, some assemblers support “macro” mnemonics, which are assembled into multiple instructions. These additional assembler mnemonics are beyond the scope of this section. For more information, see the documentation provided with the assembler.

Table 3-8 is a quick reference to the abbreviations and symbols used in the instruction descriptions.

SX User’s Manual Rev. 3.1

Table 3-8 Key to Abbreviations and Symbols

Symbol Description

W Working register

fr File register value (a 5-bit file register address specified in the instruction)

PC Lower eight bits of program counter (global file register 02h)

STATUS STATUS register (global file register 03h)

FSR File Select Register (global file register 04h)

C Carry bit in STA TUS register (bit 0)

DC Digit Carry bit in STATUS register (bit 1)

Z Zero bit in STATUS register (bit 2

PD Power Down bit in STA T US register (bit 3)

TO Watchdog Timeout bit in STATUS register (bit 4) PA2:PA0 Page select bits in STATUS register (bits 7:5) OPT ION OPTION register (not memory-mapped)

WDT Watchdog Timer register (not memory-mapped)

www. s ce nix.comChapter 3 Instruction Set

MODE MODE register (not memory-mapped)

rx Port control register pointer (RA, RB, RC, RD, or RE)

! Non-memory-mapped register designator

f File register address bit in opcode k Constant value bit in opcode n Numerical value bit in opcode b Bit position selector bit in opcode

. File register / bit selector separator in assembly language instruction # Immediate literal designator in assembly language instruction

lit Literal value in assembly language instruction addr8 8-bit address in assembly language instruction addr9 9-bit address in assembly language instruction

addr12 12-bit address in assembly language instruction

/ Logical 1’s complement | Logical OR

^ Logical exclusive OR

& Logical AND

<> Swap high and low nibbles (4-bit segments) << Rotate left through carry bit >> Rotate right through carry bit

- - Decrement file regi s te r

++ Increment file register

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.1 ADD fr,W Add W to fr

Operation: fr = fr + W

Bits affected: C, DC, Z

Opcode: 0001 111f ffff

Description: This instruction adds the contents of W to the contents of the specified file register

and writes the 8-bit result into the same file register. W is left unchanged. The register contents are treated as unsigned values.

If the result of addition exceeds FFh, the C bit is set and the lower eight bits of the result are written to the file register. Otherwise, the C bit is cleared.

If there is a carry from bit 3 to bit 4, the DC (digit carry) bit is set. Otherwise, the bit is cleared.

If the result of addition is 00h, the Z bit is set. Otherwise, the bit is cleared. An addition result of 100h is considered zero and therefore sets the Z bit.

Config. Option: If the CF bit in the FUSEX configuration register has been programmed to 0, this

instruction also adds the C bit as a carry-in input: fr = fr + W + C

Cycles: 1

Example: add $12,W

This example adds the contents of W to file register 12h. For example, if the file register contains 7Fh and W contains 02h, this instruction adds 02h to 7Fh and writes the result, 81h, into the file register; and clears the C and Z bits. It sets the DC bit because of the carry from bit 3 to bit 4.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.2 ADD W,fr Add fr to W

Operation: W =W + fr

Bits affected: C, DC, Z

Opcode: 0001 110f ffff

Description: This instruction adds the contents of the specified file register to the contents of W

and writes the 8-bit result into W. The file register is left unchanged. The register contents are treated as unsigned values.

If the result of addition exceeds FFh, the C bit is set and the lower eight bits of the result are written to W. Otherwise, the C bit is cleared.

If there is a carry from bit 3 to bit 4, the DC (digit carry) bit is set. Otherwise, the bit is cleared.

If the result of addition is 00h, the Z bit is set. Otherwise, the bit is cleared. An addition result of 100h is considered zero and therefore sets the Z bit.

Config. Option: If the CF bit in the FUSEX reg ister has been progra mmed to 0, this instruction also

adds the C bit as a carry-in input: W = W + fr + C

Cycles: 1

Example: add W,$12

This example adds the contents of file register 12h to W. For example, if the file register contains 81h and W contains 82h, this instruction adds 81h to 82h and writes the lower eight bits of the result, 03h, into W. It sets the C bit because of the carry out of bit 7, and clears the DC bi t becau se there is no carry from bit 3 to bit 4. The Z bit is cleared because the result is nonzero.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.3 AND fr,W AND of fr and W into fr

Operation: fr = fr & W

Bits affected: Z

Opcode: 0001 011f ffff

Description: This instruction performs a bitwise logical AND of the contents of the specified file

register and W, and writes the 8-bit result into the same file register. W is left unchanged. If the result is 00h, the Z bit is set.

Cycles: 1

Example: and $10,W ;perform logical AND and overwrite fr

This example performs a bitwise logical AND of the w orking register W with a value stored in file register 10h. The result is written back to the file register 10h.

For example, suppose that the file register 10h is loaded with the value 0Fh and W contains the value 13h. The instruction take s the logical AND of 0Fh and 13h and writes the result, 03h, into the same file register. The result is nonzero, so the Z bit is cleared.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.4 AND W,fr AND of W and fr into W

Operation: W = W & fr

Bits affected: Z

Opcode: 0001 010f ffff

Description: This instruction performs a bitwise logical AND of the contents of W and the spec-

ified file register, and writes the 8-bit result into W. The file register is left unchanged. If the result is 00h, the Z bit is set.

Cycles: 1

Example: and W,$0B ;perform logical AND and overwrite W

This example performs a bitwise logical AND of the value stored in file register 0Bh with W. The result is written back to W.

For example, suppose that the file register 0Bh is loaded with the value 0Fh and W contains the value 13h. The instruction take s the logical AND of 0Fh and 13h and writes the result, 03h, into W. The result is nonzero, so the Z bit is cleared.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.5 AND W,#lit AND of W and Literal into W

Operation: W = W & lit

Bits affected: Z

Opcode: 1110 kkkk kkkk

Description: This instruction performs a bitwise logical AND of the contents of W and an 8-bit

literal value, and writes the 8-bit result into W. If the result is 00h, the Z bit is set.

Cycles: 1

Example: and W,#$0F ;mask out four high-order bits of W

This example performs a bitwise logical AND of W with the literal value #0Fh. The result is written back to W.

For example, suppose that W contains the value 50h. The instruction takes the logical AND of this value with 0Fh and writes the result, 00h, into W. The result is zero, so the Z bit is set.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.6 BANK addr8 Load Bank Number into FSR(6:4)

Operation: FSR(6:4) = addr8(6:4)

Bits affected: none

Opcode: 0000 0001 1nnn

Description: This instruction loads bits 4, 5, and 6 of the File Select Register (FSR). The high-

order bits of FSR specify the data memory bank number for subsequent memory access instructions. You can specify any 3-bit value from 0 to 7.

In the syntax of the assembly language, you specify the bank using a full 8-bit data memory address. The assembler encodes the three high-order bits of this address into the instruction opcode and ignores the five low-order bits.

For the SX18/20/28AC, the bits 4:0 of FSR are left unchanged. For the SX48/52BD, bit 7 and bits 3:0 of FSR are left unchanged. To switch

between upper and lower bank blocks, you need to set bit 7 of FSR by using the instruction “setb $04.7” or clear bit 7 by us ing the instruction “clrb $04.7” after the “bank” instruction.

If a skip instruction is immediately followed by BANK instruction (and tested condition is true) then two instructions are skipped and the operation consumes three cycles. This is useful for conditional branching to another page where a P AGE instruction precedes a JMP. If several BANK instructions immediately follow a skip instruction then they are skipped plus the next instruction and a cycle is consumed for each. Special attention required when switching betwee n upper and lower bank blocks.

Cycles: 1

Example: SX18/20/28AC and SX18/20/28AC75:

bank $E0 ;select highest bank This example writes the three high-order bits of FSR with 111 and selects Bank 7,

the highest bank.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

SX48/52BD:

bank $07 ;select highest bank setb $04.7

This example wrires bits 4, 5, 6 of FSR with 111. The BANK instruction is immediately followed by “setb $04.7” to select the upper block of 8 banks.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.7 CALL addr8 Call Subrouti ne

Operation: top-of-stack = program counter + 1

PC(7:0) = addr8 program counter (8) = 0 program counter (11:9) = PA2:PA0

Bits affected: none

Opcode: 1001 kkkk kkkk

Description: This instruction calls a subroutine. The full 12-bit address of the next program in-

struction is saved on the stack and the program counter is loaded with a new address, which causes a jump to that program address.

Bits 7:0 come from the 8-bit constant value in the instruction, bit 8 i s always 0, and bits 11:9 come from the PA2:PA0 bits in the STATUS register. Therefore, the subroutine must start in the bottom half of a 512-word page in the program memory (000h to 0FFh, 200h to 2FFh, etc.).

The subroutine is terminated by any one of the “return” instructions, which restores the saved address to the program counter. Execution proceeds from the instruction following the “call” instruction.

Cycles: 2 in “compatible” mode (SX18/20/28AC and SX18/20/2 8AC75 only), or 3 in “tur-

bo” mode

Example: page $600 ;set page of subroutine in STAT US reg.

call addxy ;call subroutine addxy mov $0C,W ;use addxy subroutine results ... ;more of program (not shown)

addxy ;subroutine address label

mov W,$0E ;subroutine instructions start here add W,$0F ... ret ;return from subroutine

The “call” instruction in this example calls a subroutine called “addxy.” When the “call” instruction is executed, the address of the following instruction (the “mov $0C,W” instruction) is pushed onto the stack and the program jumps to the “addxy” routine. When the “ret” in struction is exec uted, the 12-bit program addr ess saved on the stack is popped and restored to the program counter, which causes the

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

program to continue with the instruction immediately following the “call” instruction.

The “addxy” routine must start in the lower half of a 512-word page of the program memory. This is because bit 8 of the subr outine address must be 0. The PA2:PA0 bits of the STAT US register must contain the three high-order bits of the subroutine address prior to the “call” inst ruction. This is the purpos e of the “page” instruction.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.8 CLR fr Clear fr

Operation: fr = 0

Bits affected: Z

Opcode: 0000 011f ffff

Description: This instruction clears the specified file register to zero. It also sets the Z bit uncon-

ditionally.

Cycles: 1

Example: clr $0A

This example clears file register 0Ah to 00h and sets the Z bit.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.9 CLR W Clear W

Operation: W = 00h

Bits affected: Z

Opcode: 0000 0100 0000

Description: This instruction clears W, the working register. It also sets the Z bit.

Cycles: 1

Example: clr W

This example clears W to 00h and sets the Z bit.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.10 CLR !WDT Clear Watchdog Timer

Operation: Clears Watchdog timer counter and prescaler counter

Bits affected: Z, TO, PD

Opcode: 0000 011f ffff

Description: This instruction clears the Watchdog Timer counter to zero. It also clears the

Watchdog prescaler register to zero, and sets the Z, TO, and PD bits to 1 (the Zero, Watchdog T imeout, and Power Down bits in the STATUS register).

If the Watchdog circuit is enabled, the application software must execute this instruction periodically in order to prevent a Watchdog reset.

Cycles: 1

Example: clr !WDT

This example clears the Watchdog Timer counter and the Watchdog prescaler register to zero; and sets the Z, TO, and PD bits.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.11 CLRB fr.bit Clear Bit in fr

Operation: Clear a specified bit in fr

Bits affected: none

Opcode: 0100 bbbf ffff

Description: This instruction clears a bit in the specified file register to 0 without changing the

other bits in the register. The file register address (00h through 1Fh) and the bit number (0 through 7) are the instruction operands.

Cycles: 1

Example: clrb $1F.7

This example clears the most significant bit of file register 1Fh.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.12 DEC fr Decrement fr

Operation: fr = fr -1

Bits affected: Z

Opcode: 0000 111f ffff

Description: This instruction decrements the specified register file by one.

If the file register contains 01h, it is decremented to 00h and the Z bit is set. Otherwise, the bit is cleared.

If the file register contains 00h, it is decremented to FFh.

Cycles: 1

Example: dec $18

This example decrements file register 18h.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.13 DECSZ fr Decrement fr and Skip if Zero

Operation: fr = fr - 1

if 0, then skip next instruction

Bits affected: none

Opcode: 0010 111f ffff

Description: This instruction decrements the specified register file by one and tests the new reg-

ister value. If that value is zero, the next program instruction is skipped. Otherwise, execution proceeds normally with the next instruction.

Cycles: 1 if tested condition is false, 3 if tested condition is true

Example: decsz $18

jmp back1 mov $19,W

The “decsz” instruction decrements file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.14 INC fr Increment fr

Operation: fr = fr +1

Bits affected: Z

Opcode: 0010 101f ffff

Description: This instruction increments the specified register file by one.

If the file register contains FFh and is incremented to 00h, the Z bit is set. Otherwise, the bit is cleared.

Cycles: 1

Example: inc $18

This example increments file register 18h.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.15 INCSZ fr Increment fr and Skip if Zero

Operation: fr = fr + 1

if 0, then skip next instruction

Bits affected: none

Opcode: 0011 111f ffff

Description: This instruction increments the specified register file by one and tests the new reg-

ister value. If that value is zero, the next program instruction is skipped. Otherwise, execution proceeds normally with the next instruction.

Cycles: 1 if tested condition is false, 2 if tested condition is true

Example: incsz $18

jmp back1 mov $17,W

The “incsz” instruction increments file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.16 IREAD Read Word from Instruction Memory

Operation: MODE:W = data at (MODE:W)

Bits affected: none

Opcode: 0000 0100 0001

Description: This instruction allows the device to transfer data from instruction memory into

data memory. It concatenates the lower four bits of the MODE register with W to make a 12-bit address, using the MODE register bits for the high-order part and W for the low-order part. It r eads the 12-bit word from program memory at that address. Then it writes the four high-order bits of the word into the lower four bits of the MODE register , and writes the eight low-order bits of the word into W. The four high-order bits of the MODE register are cleared to zero.

MODE Register

000

Hardwired to 0 for all devices

Figure 3-1 shows how the MODE and W regi ster are us ed to specify t he program

memory address and to contain the 12-bit result.

Program Memory Address Pointer

Upper 4 bits Lower 8 bits

Lower 8 bitsUpper 4 bits

= Hardwired to 0 for SX28AC

Programmable with MOV M, W for SX48/52BD

W Register

Program Memory

Program Data

Figure 3-1 Program Counter Loading for Call Instruction

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

Cycles: 3

Example: mov W, #$03 ;load W with the value 03h

mov M,W ;move value 03h into MODE register mov W,#$80 ;load W with the value 80h iread ;read program address 380h into W & MODE mov $0E,W ;move lower byte of data to reg 0Eh mov W,M ;move upper 4 bits of data to W mov $0F,W ;move upper 4 bits of data to reg 0Fh

This example reads the 12-bit data stored the program address 380h. The program first loads the MODE register and W with the 12-bit program address, 380h. After the “iread” instruction, the MODE register and W contain the 12-bit value stored in the program memory at address 380h. The program then stores the lower eight bits of the result into file register 0Eh and the upper four bits of the result into file register 0Fh.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.17 JMP addr9 Jump to Address

Operation: PC(7:0) = addr9(7:0)

program counter (8) = addr9(8) program counter (11:9) = PA2:PA0

Bits affected: none

Opcode: 101k kkkk kkkk

Description: This instruction causes the program to jump to a specified address. It loads the pro-

gram counter with the new address. The new 12-bit address is generated from two different sources. Bits 8:0 come fr om the 9-bit constant value in the instruction and bits 11:9 come from the PA2:PA0 bits in the STATUS register. The STATUS register must contain the appropriate value prior to the jump instruction.

Cycles: 2 in “compatible” mode (SX18/20/28AC and SX18/20/2 8AC75 only), or 3 in “tur-

bo” mode

Example: page $600 ;set page of jump addr. in STAT US reg.

snb $03.0 ;test carry bit and skip if clear jmp overflo ;jump to overflo routine if C=1 ... ;more of program (not shown)

overflo ;

mov W,$09 ;routine executed if C=1 ...

This example shows one way to implement a conditional jump. The “jmp” instruction, if executed, causes a jump to the address of the “overflo” program label. The “snb” instruction (test bit and skip if clear) causes the “jmp” instruction to be either executed or skipped, depending on the state of the carry bit.

The PA2:PA0 bits of the STATUS register must contain the three high-order bits (bits 11:9) of the “overflo” routine address prior to the “jump” instruction. This is the purpose of the “page” instruction.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.18 MOV fr,W Move W to fr

Operation: fr = W

Bits affected: none

Opcode: 0000 001f ffff

Description: This instruction moves the contents of W into the specified file register. W is left

unchanged.

Cycles: 1

Example: bank $E0 ;select bank

mov $10,W ;move W to reg. 10h in bank This example moves the contents of W into file register 10h in Bank 7 (for the

SX18/20/28AC) or Bank E (for the SX48/52BD).

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.19 MOV M,#lit Move Literal to MODE Register

Operation: MODE = lit

Bits affected: none

Opcode: 0000 0101 kkkk

Description: For SX18/20/28AC and SX18/20/28AC75 devices, this instruction writes a 4-bit

value to the lower four bits of the MODE register. For SX48/52BD devices, this instruction writes a 5-bit value to the lower five bits of the MODE registe r . These bits select the port control registers accessed by the “MOV !rx,W” instructions. For information on the specific MODE register values to use for accessing the port control registers, see Section 5.3.2.

Cycles: 1

Example: mov W,#$1D ;1Dh to control level sensitivity

mov M,W ;put 1Dh into MODE register mov W,#$00 ;W = 0000 0000 mov !RA,W ;select CMOS levels for Port A mov M,#$E ;1Eh to control pullups mov W,#$03 ;W = 0000 11 11 mov !RA,W ;disconnect pullups for RA3:RA0 mov M,#$F ;1Fh to control data direction mov W,#$0F ;W = 1111 0000 mov !RA,W ;make RA3:RA0 operate as outputs

This example sets the configuration of Port A pins: the level sensitivity, the pullup connections, and the data direction. The “mov M,W” instruction is us ed to load the MODE register the first time because it controls the four lower bits of the MODE register ( SX18/20/28AC and SX18/20/28AC75 devices) and the five lower bitsof the MODE register for the SX48/52BD devic es. The two s ubsequent “ mov M ,#lit” instructions change the lower four bits of the MODE register.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.20 MOV M,W Move W to MODE Register

Operation: MODE = W

Bits affected: none

Opcode: 0000 0100 0011

Description: This instruction moves the lower four bits of W register into the lower four bits of

the MODE register on the SX18/20/28AC and SX18/20/28AC75 devices. The instruction moves the lower five bits of W into the lower five bits of the MODE register on the SX48/52BD devices. W is left unchanged. The MODE register operates as a pointer to the port control registers for subsequent accesses to those registers using the “MOV !rx,W” instruction.

Cycles: 1

Example: mov W, $0B ;move value from file reg 0Bh to W

mov M,W ;move W into MODE register This example moves a value from file register 0Bh to W, and then from W into the

MODE register.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.21 MOV !OPTION,W Move W to OPTION Register

Operation: OPTION = W

Bits affected: none

Opcode: 0000 0000 0010

Description: This instruction moves W to the OPTION register. W is left unchanged. The OP-

TION register sets the Real-Time Clock/Counter (RTCC) configuration options such as RTCC interrupt enable, RTCC increment event control, and prescaler assignment. For information on the format of the OPTION register, see Section 2.4.9.

Cycles: 1

Example: mov W,#$3F ;load W with 3Fh

mov !OPTION,W ;write value to OPTION register This example moves programs the OP T ION register with the value 3Fh.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.22 MOV !rx,W Move Data Between W and Control Register

Operation: rx = W (move W to rx)

W = rx (move rx to W)

or or

rx <=> W (exchange W and rx)

Bits affected: none

Opcode: 0000 0000 ffff

Description: This instruction moves data between W and one of the port control registers (rx).

The port control register is specified in the instruction mne monic as !RA, !RB, !RC, !RD, or !RE. This corresponds to a 4- bit f ield in the opcode that is set to 5, 6, 7, 8 or 9 to access a port control register for Port A, B, C, D, or E, respectively.

To access the port data register rath er than a port control register, use the “MOV fr,W” or similar instruction, addressing the port as “fr” rather than “!rx”.

Each port has a set of control registers: one each for setting the data direction, the pullup configuration, the Schmitt trigger configuration, and so on. The MODE register setting determines the port control register acces sed by the “MOV !rx,W” instruction, as well as the type of access (read, write, or exchange).

For information on the specific MODE register values to use for accessing the port control registers, see Section 5.3.2.

Cycles: 1

Example 1: mov W,#$1F ;1Fh to select data direction

mov M,W ;write 1Fh to MODE register mov W ,#$3F ;pins 0-5 Hi-Z inputs, pins 6-7 outputs mov !RB,W ;configure Port B pin data directions mov W,#$FF ;all pins Hi-Z inputs mov !RC,W ;configure Port C pin data directions

This example configures the data direction for each pin of Port B and Port C. The first two instructions program the MODE register to allow access to the port data direction registers. The third instruction loads W with the value 3Fh. The fourth instruction writes this value to the RB direction register, which configures pins 0 through 5 to operate as high-impedance inputs and pins 6 and 7 to operate as outputs. The last two instructions configure all Port C pins to operate as inputs.

SX User’s Manual Rev. 3.1

Example 2: mov M,#$8 ;load MODE register to select CM P_B

clr W ;clear W mov !RB,W ;00h into CMP_B and old CMP_B into W

;enables comparator and its output pin

This example enables the comparator and its output pin. The “mov !RB,W” instruction does an exchange of data between the CMP_B register and W. For access to the C MP_B register, the four upper bits of the MODE register are all “don’t care” bits, so the “mov M,#lit” instruction (which only af fects the four lower bits of the MODE register) is sufficient to select access t o the CMP_B register.

www. s ce nix.comChapter 3 Instruction Set

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.23 MOV W,fr Move fr to W

Operation: W = fr

Bits affected: Z

Opcode: 0010 000f ffff

Description: This instruction moves the contents of the specified file register into W. The file

If the value is 00h, the Z bit is set. Otherwise, the bit is cleared.

Cycles: 1

Example: bank $E0 ;select bank

mov W,$1F ;move register to W This example moves the contents of a specific file regist er int o W. The Z bit is set

if the value is zero or cleared if the value is nonzero.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.24 MOV W,/fr Move Complement of fr to W

Operation: W = fr ^ FFh

Bits affected: Z

Opcode: 0010 010f ffff

Description: This instruction loads the one’s complement of the specified file register into W.

The file register is left unchanged. If the value loaded into W is 00h, the Z bit is set. Otherwise, the bit is cleared.

Cycles: 1

Example: mov W, / $0F

This example moves the one’s complement of global file register 0Fh into W. For example, if the file register contains 75h, the complement of this value, 8Ah, is loaded into W, and the Z bit is cleared. The file register is left unchanged.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.25 MOV W ,fr-W Move (fr-W) to W

Operation: W = fr - W

Bits affected: C, DC, Z

Opcode: 0000 100f ffff

Description: This instruction subtracts the contents of W from the contents of the specified file

register and writes the 8-bit result into W. The file register is left unchanged. The register contents are treated as unsigned values.

If the result of subtraction is negative (W is larger than fr), the C bit is cleared to 0 and the lower eight bits of the result are written to W . Otherwise, the C bit is set to 1.

If there is a borrow from bit 3 to bit 4, the DC (digit carry) bit is cleared to 0. Otherwise, the bit is set to 1.

If the result of subtraction is 00h, the Z bit is set. Otherwise, the bit is cleared.

Config. Option: If the CF bit in the FUSEX configuration register has been programmed to 0, this

instruction also subtracts the complement of the C bit as a borrow-in input: W = fr - W - /C

Cycles: 1

Example: mov W,$0D-W

This example subtracts the contents of W from global file register 0Dh and moves the result into W . For example, if the file register contains 35h and W contains 06h, this instruction subtracts 06h from 35h and writes the result, 2Fh, into W . It also sets the C bit, clears the DC bit, and clears the Z bit. The file register is left unchanged.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.26 MOV W,--fr Move (fr-1) to W

Operation: W = fr -1

Bits affected: Z

Opcode: 0000 110f ffff

Description: This instruction decrements the value in the specified register file by one and moves

the 8-bit result into W. The file register is left unchanged. If the file register contains 01h, the value moved into W is 00h and the Z bit is set.

Otherwise, the bit is cleared.

Cycles: 1

Example: mov w,--$18

This example decrements the value in file register 18h and moves the result into W. For example, if the file register contains 75h, the value 74h is loaded into W, and the Z bit is cleared. The file register still contains 75h after execution of the instruction.

SX User’s Manual Rev. 3.1

www.scenix.com Chapter 3 Instruction Set

3.6.27 MOV W,++fr Move (fr+1) to W

Operation: W = fr + 1

Bits affected: Z

Opcode: 0010 100f ffff

Description: This instruction increments the value in the specified register file by one and moves

the 8-bit result into W. The file register is left unchanged. If the file register contains FFh, the value moved into W is 00h and the Z bit is set.

Otherwise, the bit is cleared.

Cycles: 1

Example: mov w,++$18

This example increments the value in file register 18h and moves the result into W. For example, if the file register contains 75h, the value 76h is loaded into W, and the Z bit is cleared. The file register still contains 75h after execution of the instruction.

SX User’s Manual Rev. 3.1

www. s ce nix.comChapter 3 Instruction Set

3.6.28 MOV W,<<fr Rotate fr Left through Carry and Move to W

Operation: W = << fr

Bits affected: C

Opcode: 0011 010f ffff

Description: This instruction rotates the bits of the specified file register left using the C bit and

moves the 8-bit result into W. The file register is left unchanged. The bits obtained from the register are shifted left by one bit position. C is shifted

into the least significant bit position and the most significant bit is shifted out into C, as shown in the diagram below.

Figure 3-2 Rotate fr Left Through Carry into W

Cycles: 1

Example 1: mov W,<<$18

File Register

Carry Bit

This example rotates the bits of file register 18h left through the C bit and moves the result into W. If the file register contains 14h and the C bit is set to 1, after this instruction is executed, W will contain 29h and the C bit will be cleared to 0. The file register will still contain 14h after execution of the instruction.

SX User’s Manual Rev. 3.1

Scenix SX Series, SX20AC75, SX20AC, SX18AC, SX28AC User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual